CN111427857B - FPGA configuration file compression and decompression method based on partition reference technology - Google Patents
FPGA configuration file compression and decompression method based on partition reference technology Download PDFInfo
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Abstract
The invention discloses a Field Programmable Gate Array (FPGA) configuration file compression and decompression method based on a partition reference technology, which defines an FPGA configuration file f i = (h, d, r), i =1,2,3, \8230;, n, header information h contains engineering name, compilation time, and target chip model information; the configuration data information d comprises binary codes of various resources in the target chip; the tail redundant information r comprises a plurality of null instruction operations and partitions the FPGA configuration file; and carrying out compression and decompression operation on the head information h, the configuration data information d and the tail redundant information r by adopting different compression strategies. The FPGA configuration files are partitioned according to functions, corresponding compression and decompression strategies are designed for different partitions, application scenes of multiple FPGA configuration files need to be transmitted at one time during large-scale neural network cooperative processing, repeated information among the configuration files is analyzed, and the compression rate is further improved by adopting a reference compression method.
Description
Technical Field
The invention belongs to the technical field of electronics, and particularly relates to an FPGA configuration file compression and decompression method based on a partition reference technology.
Background
The Field Programmable Gate Array (FPGA) uses a reconfigurable technology, and solves the problem of low flexibility caused by hardware function determination of an Application Specific Integrated Circuit (ASIC) after tape-out. Therefore, FPGAs are applied to embedded systems where hardware devices are expensive and frequently need to be upgraded or changed in function, and are widely applied in the fields of aerospace, large-scale medical devices, auto-driving of automobiles, internet of things and the like.
The general process of FPGA development is: developers are in integrated development environments such as: the method comprises the steps that hardware design is carried out in tools such as ISE and VIVADO of Xilinx, after operations such as layout and wiring are completed, the tools automatically generate an FPGA configuration binary file, hardware design information is stored in the file, the file is transmitted to a target chip and then the file content is electrified and read, and normal operation of FPGA functions is achieved.
In recent years, the integration level of an FPGA Chip technology is improved, on-Chip (On-Chip) resources are more and more, and accordingly, the capacity of an FPGA configuration file is increased: the XILINX-Spartan3 series chip contains 53712 Logic Cells (LCs), while the Virtex UltraScale series chip has a number of LCs of 4432680, taking into account other types of resources, such as: I/O, ROUTING, DSP, BRAM, etc., FPGA profile size has increased hundreds of times in the last 10 years.
With the rapid development of artificial intelligence and deep learning technology, the requirement of training a neural network model on computing power increases exponentially. In order to solve the problem of insufficient computing power of the isomorphic calculation of the CPU, heterogeneous coprocessing technologies such as the CPU + GPU and the CPU + GPU + FPGA come along, and the FPGA chip obtains more and more attention in the field of artificial intelligence because of the parallelism and the flexibility brought by reconfiguration of special hardware.
The neural network is huge in scale, a single FPGA chip cannot meet the demand of required computing power often, and multiple FPGA chips are required to be called to assist in operation, fig. 1 shows a multi-chip configuration flow of an FPGA cloud computing platform, and a multi-FPGA chip configuration file F = { F = generated by local compilation 1 ,f 2 ,f 3 ,...,f n The data are transmitted to an FPGA cloud computing platform through the internet, task distribution is carried out by a management node, and each chip configuration file f is transmitted to the FPGA cloud computing platform through the internet i I =1,2,3, \ 8230, n is distributed to different FPGAs to implement different functions.
Each chip needs to be configured for one time of task updating of the cloud computing platform, and configuration time is too long due to the fact that a huge configuration file F of multiple FPGA chips is faced. And the configuration file F generated by local compilation is transmitted to the FPGA cloud computing platform through the public internet for downloading and configuration, due to the limitation of the bandwidth of the public network and excessive transmitted data, configuration time consumption is further increased, and the loading speed of the configuration file is too low, so that the configuration speed and the operation efficiency of the FPGA chip cluster are influenced.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a method for compressing and decompressing an FPGA configuration file based on a partition reference technology, aiming at the above deficiencies in the prior art, so as to solve the problem of long time consumption in the configuration process.
The invention adopts the following technical scheme:
a FPGA configuration file compression and decompression method based on a partition reference technology comprises the following steps:
s1, defining FPGA configuration file f i = (h, d, r), i =1,2,3, \8230;, n, header information h contains engineering name, compilation time, and target chip model information; the configuration data information d comprises binary codes of various resources in the target chip; the tail redundant information r comprises a plurality of null instruction operations and partitions the FPGA configuration file;
s2, carrying out compression and decompression operation on the head information h, the configuration data information d and the tail redundant information r by adopting different compression strategies.
Specifically, in step S1, the header information h includes 16 sequences, and has a fixed length and content: sequences 1,2,3,6,9, 12 and 15; the length is fixed, and the content is the length of the next sequence: sequences 4, 7, 10 and 13; the length and the content are not fixed: sequences 5, 8, 11, 14, 16.
Further, the compression policy of the header information h is:
deleting the fixed part of the length and the content aiming at the fixed part of the length and the content, and not counting the transmission file f i The preparation method comprises the following steps of (1) performing;
for the fixed length part, sequences 4, 7 are numbered f i In (2), since the length of the sequences 10 and 13, represented by sequence 11 and sequence 14, is fixed, they are: 10 bytes and 8 bytes, delete sequences 10, 13, not counting f i Performing the following steps;
for parts of indefinite length and content, the reserve count f i Redundant information (0 x 00) in sequences 5, 8, 11 and 14 is not counted in f i In (1).
Further, the decompression policy for the header information h is:
setting a special decompression unit for header information h, and storing the contents of the sequences 1,2,3,6,9, 10, 12, 13 and 15; for configuration file f 1 The decompression process of (a) is as follows:
adding sequences 1,2,3 to f from dedicated decompression units 1 A file header; taking 4 bytes of the compressed file, and intercepting f according to the content of the 4 bytes 1 Corresponding length, and adding 0x00 as sequence 5 content at the end; current f 1 A position addition sequence 6; taking 4 bytes of the compressed file, and intercepting f according to the content of the 4 bytes 1 Corresponding length, and adding 0x00 at the end as the sequence 8 content; current f 1 Position addition sequences 9 and 10; intercept f 1 Adding 0x00 as the content of the sequence 11 at the end with the length of 10 bytes after the current position, and storing the content of the sequence 11 in a special decompression unit for reference decompression; current f 1 Position addition sequences 12 and 13; intercept f 1 Adding 0x00 as the content of the sequence 14 at the end with the length of 8 bytes after the current position, and storing the content of the sequence 14 in a special decompression unit for reference decompression; current f 1 Position addition sequence 15.
Further, for the configuration file f i I =2,3, \8230, decompression of n:
adding the sequence 1,2,3 to f from a dedicated decompression unit 1 A file header; taking 4 bytes of the compressed file, and intercepting f according to the content of the 4 bytes 1 Corresponding length, and adding 0x00 as sequence 5 content at the end; current f 1 A position addition sequence 6; taking 4 bytes of the compressed file, and intercepting f according to the content of the 4 bytes 1 Corresponding length, and adding 0x00 at the end as the sequence 8 content; current f 1 Position addition sequences 9 and 10; adding sequence 11 content to f from a dedicated decompression unit i A current location; adding sequences 12 and 13 to the current fi position; adding sequence 14 content from a dedicated decompression unit to f i A current location; current f 1 Position addition sequence 15.
Specifically, in step S2, the compression policy of the configuration data information d is:
for configuration file f i I =2,3, \ 8230;, n, in units of 4 bytes, refers to the configuration file f 1 Compressing; for configuration file f 1 The compression is performed by means of run-length encoding.
Further, the decompression policy of the configuration data information d is as follows:
for configuration file f i I =2,3, \ 8230;, n, judgment profile f i If the current flag bit is 0, the configuration file f is set 1 Write f of 4 bytes data i (ii) a If the value is 1, the result indicates that the subsequent 4-byte data does not refer to the configuration file f 1 Compressing, outputting as it is, and circulating the above operations until the configuration file f i And finishing the decompression process after the configuration data information is finished.
Specifically, in step S2, the compression policy of the tail redundant information r is: and traversing r, counting the occurrence frequency n of 0x20 00, deleting the content of r, writing n, and realizing compression.
Further, the decompression strategy of the tail redundant information r is as follows: reading the number of occurrences of 0x20 00 n, reading 0x20 00 repeating n times, writing r completes decompression.
Compared with the prior art, the invention at least has the following beneficial effects:
the invention discloses a compression and decompression method for FPGA (field programmable gate array) configuration files based on a partition reference technology, which aims at the problem of overlong configuration time consumption caused by the fact that a huge plurality of FPGA configuration files need to be transmitted for one-time configuration in an FPGA cloud computing platform.
Further, the content in the header information h has regularity, and the present invention sets 16 sequences for the purpose of representing each item of content. And (4) making different compression and decompression rules according to the sequence.
Further, different from general compression, the invention makes a targeted compression strategy according to the content characteristics of the header information h, and improves the compression effect.
Furthermore, the decompression strategy setting of the header information h aims to realize the decompression process of the compression method established by the invention and ensure the normal reading of the configuration file.
Furthermore, aiming at the multi-FPGA configuration files transmitted at one time, the repeatability among the files of the configuration data information d is analyzed, a reference compression strategy is made, and the compression rate is improved.
Furthermore, the decompression strategy setting of the configuration data information d aims to realize the decompression process of the compression method formulated by the invention and ensure the normal reading of the configuration file.
Furthermore, aiming at the characteristics of the tail redundant information r, only the occurrence frequency of the repeated data (0x20 00) is recorded, so that the compression is realized, and the compression rate is improved.
Furthermore, the decompression strategy setting of the tail redundant information r aims to realize the decompression process of the compression method established by the invention and ensure the normal reading of the configuration file.
In summary, the FPGA configuration files are partitioned according to functions, corresponding compression and decompression strategies are designed for different partitions, and when a large-scale neural network is cooperatively processed, an application scenario of multiple FPGA configuration files needs to be transmitted at one time, repeated information among the configuration files is analyzed, and a reference compression method is adopted to further improve the compression rate.
The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.
Drawings
FIG. 1 is a flow diagram of a multi-chip configuration of an FPGA cloud computing platform;
FIG. 2 is a diagram of an FPGA configuration file according to the present invention.
Detailed Description
The invention relates to a FPGA configuration file compression and decompression method based on a partition reference technology, which comprises the following steps of:
s1, partitioning an FPGA configuration file;
the FPGA configuration file can be divided into three parts according to contents: header information, configuration data information, and trailer redundancy information.
Referring to FIG. 2, the present invention defines an FPGA configuration file f i = h, d, r, i =1,2,3, \ 8230;, n, first part header information h, including information irrelevant to configuration contents such as an engineering name, a compilation time, a target chip model, and the like; the second part is configuration data information d which comprises binary codes of various resources in the target chip; the third part is tail redundant information r which comprises a plurality of null instruction operations.
According to the content classification of the configuration files, the FPGA configuration file f is subjected to compression preprocessing in the invention i And partitioning, and adopting different compression strategies according to different parts of the configuration file.
S2, compressing and decompressing strategies;
s201, compressing and decompressing the header information h;
the header information h is composed as shown in table 1:
table 1 header information h is composed in sequence
The method consists of 16 sequences in total, and is divided into three types:
a) The length and the content are fixed: sequences 1,2,3,6,9, 12 and 15.
b) The length is fixed, and the content is the length of the next sequence: sequences 4, 7, 10 and 13.
c) The length and the content are not fixed: sequences 5, 8, 11, 14, 16.
S2011 compression strategy of header information h
Aiming at the part a, the invention deletes the part during compression without counting the transmission file f i In (1).
For part b, the invention formulates a compression rule as follows: sequences 4, 7 take into account f i In (2), since the lengths of the sequence 11 (configuration date) and the sequence 14 (configuration time) represented by the sequences 10 and 13 are fixed, respectively: 10 bytes and 8 bytes, so the invention deletes sequences 10, 13, not counting f i In (1).
For part c, the contents of the part are different due to different chip models, so that the part c is reserved and counted into f i However, sequences 5, 8, 11 and 14 contain redundant information (0 x 00), and the present invention deletes the redundant information, not counting f i In (1).
S2012, decompression strategy of header information h
The invention sets special decompressing units for header information h at the management node, and stores the contents of sequences 1,2,3,6,9, 10, 12, 13 and 15.
For configuration file f 1 The decompression process of (a) is as follows:
1) Adding sequences 1,2,3 to f from dedicated decompression units 1 A file header;
2) Taking 4 bytes (sequence 4) of the compressed file, and intercepting f according to the content of the compressed file 1 Corresponding length, and adding "0x00" as sequence 5 content at the end;
3) Current f 1 A position addition sequence 6;
4) Taking a compressed file 4byte (sequence 7), and intercepting f according to the content of the compressed file 1 Corresponding length, and adding "0x00" as the sequence 8 content at the end;
5) Current f 1 Position addition sequences 9 and 10;
6) Intercept f 1 Adding '0 x 00' as the content of the sequence 11 at the end with the length of 10 bytes after the current position, and storing the content of the sequence 11 in a special decompression unit for reference decompression;
7) Current f 1 Position addition sequences 12 and 13;
8) Intercept f 1 8 bytes length after current position, at junctionAdding '0 x 00' as the sequence 14 content at the tail and storing the sequence 14 content in a special decompression unit for reference decompression;
9) Current f 1 A position addition sequence 15;
for configuration file f i I =2,3, \8230, decompression process of n:
steps 1 to 5 are as above
6) Adding sequence 11 content to f from a dedicated decompression unit i The current position.
7) The current fi position adds sequences 12 and 13.
8) Adding sequence 14 content from a dedicated decompression unit to f i The current position.
9) Current f 1 Position addition sequence 15.
S202, configuring a compression and decompression strategy of the data information d;
the configuration data information d is behind the header information h and is the expression of resources on the FPGA chip, each resource is configured in a mode of instruction + data, and the instructions and the data are all in units of 4 bytes, so that the configuration data information of each chip is consistent in size no matter how many resources are occupied.
S2021, configuring a compression strategy of the data information d;
as multiple FPGAs for realizing a certain neural network together, the configuration file information has higher similarity in function. Thus, the present invention is directed to a configuration file f i I =2,3, \8230, n, in units of 4 bytes, refers to the configuration file f 1 Compressing; for configuration file f 1 And compressing in a run length coding mode.
S2022, decompression strategy of configuration data information d
The invention sets a special decompressing unit for the configuration data information d at the management node.
For configuration file f 1 Adopting common run length coding decompression operation to aim at configuration file f i I =2,3, \ 8230;, n, reference profile f 1 The file content is decompressed: the special decompression unit judges f i Current marking of filesBit, if 0, will f 1 4byte data write f of a file i (ii) a If 1, it indicates that the following 4byte data is not referred to f 1 And compressing the file, outputting the file as it is, and circulating the operation until the configuration data information of fi is finished to finish the decompression process.
S203, compressing and decompressing the tail redundant information r;
the tail redundancy information is composed of a plurality of 0x20 00 00, the operations are null operations, the part of information is irrelevant to FPGA configuration, is not loaded in the FPGA and is used as storage and reading buffer.
The compression strategy of the invention for the tail redundant information r is as follows:
and traversing r, counting the occurrence frequency n of 0x20 00 00, deleting the content of r, writing n, and realizing compression.
The decompression strategy for the tail redundant information r of the invention is as follows:
the dedicated decompression unit reads n,0x20 00 00 and repeats n times, and writes r to complete decompression.
And S3, the configuration files are compressed and then transmitted to the FPGA cloud computing platform through the internet, after the special decompression unit completes decompression, the configuration files of the chips are distributed to different FPGAs, and the configuration files are configured and then operated.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Compression strategy for header information h
The invention aims at a multi-FPGA chip configuration file F = { F } generated by local compilation 1 ,f 2 ,f 3 ,...,f n And performing reference compression on the n pieces of header information contained in the header information: because the configuration dates and times of the n FPGAs are the same, only f needs to be saved 1 The sequence 11, 14 contents of the middle header information h, and f i I =2,3, \ 8230, the header information sequence 11, 14 of n does not need to be saved.
Judging the current file, if f i Deleting the contents corresponding to the sequences 1,2,3,6,9, 10, 12, 13 and 15 of the header information h to finish compression; if is f i I =2,3, \8230;, n, deleting contents corresponding to the sequences 1,2,3,6,9, 10, 11, 12, 13, 14, and 15 of the header information h, completing the compression.
Taking v5_ crossbar. Bit configuration file as an example, the header information h is divided in sequence as shown in table 2:
table 2 header information h content
Assume the profile is f 1 With the compression method of the present invention, h after compression is divided in sequence as shown in table 3:
table 3 header information h compressed content
Bit compression 65.33%. Other profiles f i I =2,3, \ 8230, the compression rate of the header information h of n is up to 41.33% with reference to the decompression policy of the header information after compression.
Compression strategy for configuration data information d
Go through f i I =2,3, \8230, n, taking 4byte data and f of fi configuration data information d 1 Comparing the 4byte data at the corresponding position, and replacing f with a flag bit 0 if the data are the same i The corresponding data; if different, at f i Adding a flag bit 1 corresponding to the data head, and repeating the operation until f i And completing the traversal of the configuration data information d. For all f i I =2,3, \ 8230, n compression is complete, pair f 1 The configuration data information d of (a) is compressed by run length coding.
Taking v2_ crossbar.bit as an example, the total 47656 data can be compressed by reference, and the compression ratio is as follows: 65.83 percent.
Decompression strategy for configuration data information d
To f 1 The configuration data information d is decompressed by adopting a run-length coding decompression technology, and then f is traversed i I =2,3, \8230, n, is taken as f i Configuring the flag bit of the data information d, if the flag bit is 0, deleting the flag bit, and converting f into 1 The corresponding position 4byte data is stored in f i The original flag bit position; if the value is 1, deleting the flag bit. Repeating the above operation until f i And completing traversal of the configuration data information d.
Compression of tail redundancy information r
The number of occurrences of 0x20 00 is represented by dividing the length of r by 32, and the number is used instead of the data within r to complete compression.
Bit, for example, v2_ crossbar, the content of its tail redundancy information r: 0x20 00 20 00 00 20 00, the results after compression using the present invention are: the compression ratio is: 3.125 percent.
Decompression of tail redundancy information r
And reading the compressed times data n, repeating the writing of the 0x20 00 into the r for n times, and completing the decompression.
Test data: three bit files were collected in a standard test set at the department of computer science, university of erlang-new enburg, germany: v2_ crossbar.bit, v2_ des56.Bit, v2_ fft.bit, the specific compression results are given in the following table:
in summary, the invention provides a partition reference technology-based compression and decompression method for an FPGA configuration file, which aims at the problem of too long configuration time caused by the fact that multiple FPGA configuration files need to be transmitted for one configuration in an FPGA cloud computing platform.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and so forth) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The above-mentioned contents are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and any modification made on the basis of the technical idea of the present invention falls within the protection scope of the claims of the present invention.
Claims (6)
1. An FPGA configuration file compression and decompression method based on a partition reference technology is characterized by comprising the following steps:
s1, defining FPGA configuration file f i = (h, d, r), i =1,2,3, \ 8230;, n, header information h contains an engineering name, a compile time, and target chip model information; the configuration data information d comprises binary codes of various resources in the target chip; the tail redundant information r comprises a plurality of null instruction operations and partitions the FPGA configuration file, and the compression strategy of the head information h is as follows:
deleting the fixed part of the length and the content aiming at the fixed part of the length and the content, and not counting the transmission file f i Performing the following steps;
for the fixed length part, sequences 4, 7 are numbered f i Because the length of the sequences 11 and 14 represented by the sequences 10 and 13 is fixed, the sequences are divided intoRespectively, the following steps: 10 bytes and 8 bytes, deletion of sequences 10, 13, not counting f i Performing the following steps;
for parts of indefinite length and content, the reserve count f i Redundant information (0 x 00) in sequences 5, 8, 11 and 14 is not counted in f i Performing the following steps;
s2, carrying out compression and decompression operation on the head information h, the configuration data information d and the tail redundant information r by adopting different compression strategies, wherein the compression strategy of the configuration data information d is as follows:
for configuration file f i I =2,3, \ 8230;, n, in units of 4 bytes, refers to the configuration file f 1 Compressing; for configuration file f 1 Compressing in a run length coding mode;
the compression strategy of the tail redundant information r is as follows: and traversing r, counting the occurrence frequency n of 0x20 00 00, deleting the content of r, writing n, and realizing compression.
2. The partition reference technology-based FPGA configuration file compression and decompression method according to claim 1, wherein in step S1, the header information h comprises 16 sequences, and has a fixed length and content: sequences 1,2,3,6,9, 12 and 15; the length is fixed, and the content is the length of the next sequence: sequences 4, 7, 10 and 13; the length and the content are not fixed: sequences 5, 8, 11, 14, 16.
3. The partition reference technology-based FPGA configuration file compression and decompression method according to claim 1, wherein the decompression policy of the header information h is as follows:
setting a special decompression unit for header information h, and storing the contents of the sequences 1,2,3,6,9, 10, 12, 13 and 15; for configuration file f 1 The decompression process of (a) is as follows:
adding sequences 1,2,3 to f from dedicated decompression units 1 A file header; taking 4 bytes of the compressed file, and intercepting f according to the content of the 4 bytes 1 Corresponding length, and adding 0x00 as sequence 5 content at the end; current f 1 A position addition sequence 6; taking 4 bytes of the compressed file, and intercepting f according to the content of the 4 bytes 1 Of corresponding length, and inEnding with 0x00 as sequence 8 content; current f 1 Position addition sequences 9 and 10; intercept f 1 Adding 0x00 as the content of the sequence 11 at the end with the length of 10 bytes after the current position, and storing the content of the sequence 11 in a special decompression unit for reference decompression; current f 1 Position addition sequences 12 and 13; intercept f 1 Adding 0x00 as the content of the sequence 14 at the end with the length of 8 bytes after the current position, and storing the content of the sequence 14 in a special decompression unit for reference decompression; current f 1 Position addition sequence 15.
4. The FPGA configuration file compression and decompression method based on the partitioned reference technology as claimed in claim 3, wherein the configuration file f is subjected to i I =2,3, \8230, decompression of n:
adding sequences 1,2,3 to f from dedicated decompression units 1 A file header; taking 4 bytes of the compressed file, and intercepting f according to the content of the 4 bytes 1 Corresponding length, and adding 0x00 as sequence 5 content at the end; current f 1 A position addition sequence 6; taking 4 bytes of the compressed file, and intercepting f according to the content of the 4 bytes 1 Corresponding length, and adding 0x00 at the end as the sequence 8 content; current f 1 Position addition sequences 9 and 10; adding sequence 11 content to f from a dedicated decompression unit i A current location; adding sequences 12 and 13 to the current fi position; adding sequence 14 content from a dedicated decompression unit to f i A current location; current f 1 Position addition sequence 15.
5. The partition reference technology-based FPGA configuration file compression and decompression method according to claim 1, wherein in step S2, the decompression policy for the configuration data information d is:
for configuration file f i I =2,3, \ 8230;, n, judgment profile f i If the current flag bit is 0, the configuration file f is set 1 Write f of 4 bytes data i (ii) a If the value is 1, the result indicates that the subsequent 4-byte data does not refer to the configuration file f 1 Compressing, outputting as it is, and circulating the above operations until the configuration file f i In a mixing tankAnd finishing the data information setting and completing the decompression process.
6. The partition reference technology-based FPGA configuration file compression and decompression method according to claim 1, wherein in step S2, the decompression policy of the tail redundant information r is as follows: reading the number of occurrences of 0x20 00 n,0x20 00 repeats n times, and writing r completes decompression.
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