CN111416630A - Coding and decoding method and system - Google Patents
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Abstract
The invention discloses a coding and decoding method and a system, which relate to the technical field of communication, and the method comprises the following steps: establishing a plurality of independent channels, wherein each channel corresponds to a cache space; each channel receives the data frame and caches the data frame to a corresponding cache space; according to a preset scheduling strategy, completing the transmission and coding of data frames in each buffer space one buffer space at a time; wherein, the transmission and coding and decoding of the data frame comprises: and reading a data frame in a cache space, transmitting the data frame to an RS codec, finishing the coding and decoding work of the data frame in the cache space, and obtaining a coded data frame. The invention can carry out coding and decoding work on the data of multiple channels and meet the various work requirements at the present stage.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a coding and decoding method and system.
Background
With the increasing bandwidth capacity of the 5G bearer network, the service types and the access paths of the FlexE, the FlexO and the OTUk are more and more, and the transmission of various services needs to be supported by the FEC to ensure the reliable transmission.
In the related art, RS codes are widely applied to load FEC, however, the RS coding algorithm has high complexity, and the scale of the circuit logic is large, if one codec is used for each service, the scale of the circuit logic is too large, and the cost of a chip stream slice is too high, so that a single-path RS codec cannot meet the application requirement, and an RS codec supporting parallel access of multiple services is required.
However, the RS code is a block code, and one codeword is an integral and inseparable whole. The rate of each service is different, so the multiplexing method has certain particularity, in addition, the RS coding and decoding are used as an intermediate link of the processing flow of the bearing network node, the time delay of data from the inlet to the outlet is required to be fixed in some occasions, and the envelope of the output data is required to be kept uniform, so that the RS coding and decoding scheme supporting the parallel access of the multi-service cannot be provided at the present stage.
Therefore, a new coding and decoding method is needed to solve the above problems.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a coding and decoding method and a coding and decoding system, which can carry out coding and decoding work on multi-channel data and meet various work requirements at the present stage.
In order to achieve the above purposes, the technical scheme adopted by the invention is as follows:
in a first aspect, the present invention discloses a coding and decoding method, comprising the following steps:
establishing a plurality of independent channels, wherein each channel corresponds to a cache space;
each channel receives a data frame and caches the data frame to a corresponding cache space;
according to a preset scheduling strategy, completing the transmission and coding of data frames in each buffer space one buffer space at a time; wherein, the transmission and coding and decoding of the data frame comprises:
and reading a data frame in the cache space, transmitting the data frame to an RS codec, finishing the coding and decoding work of the data frame in the cache space, and obtaining a coded data frame.
On the basis of the technical scheme, the scheduling strategy comprises the following steps:
polling the number of the readable addresses in each cache space, positioning the channel with the maximum readable address and the length larger than 1 code word, and authorizing the corresponding channel to obtain the next read operation permission.
On the basis of the above technical solution, before each of the channels receives a data frame and buffers the data frame to a corresponding buffer space, the method further includes a data shaping process, and the data sorting process includes the following steps:
comparing the data length of the data frame with a preset standard data length;
when the data length of the data frame is consistent with the standard data length, the data frame is normally transmitted;
when the data length of the data frame is larger than the standard data length, only transmitting the part of the data frame conforming to the standard data length;
and when the data length of the data frame is smaller than the standard data length, adjusting the data length of the data frame to the standard data length according to a preset compensation rule, and transmitting the adjusted data frame.
On the basis of the technical scheme, when the data length of the data frame is greater than the standard data length, only the part of the data frame conforming to the standard data length is transmitted, a frame start indicating signal is detected, and when the frame start indicating signal appears, the data length of the next data frame is compared with the preset standard data length.
On the basis of the technical scheme, when the data length of the data frame is smaller than the standard data length, deleting the acquired frame start indication signal according to a preset compensation rule, adjusting the data length of the data frame to the standard data length, and transmitting the adjusted data frame.
On the basis of the technical scheme, the method further comprises the following steps:
and carrying out first time delay processing on the data frame in the buffer space.
On the basis of the technical scheme, before the coded data frames are correspondingly transmitted to the corresponding output channels, the method further comprises a data compensation process, and the data compensation process comprises the following steps:
acquiring a first delay value of the compiled code data frame during the first delay processing, and recording the first delay value as T1;
acquiring a transmission delay value of the data frame corresponding to the compiled code data frame, which is stored in the cache space at the beginning and is transmitted into the corresponding output channel by the compiled code data frame, and recording the transmission delay value as T2;
calculating an inherent delay value of the incoming channel corresponding to the compiled code data frame, and recording the inherent delay value as T3, wherein T3 is T2-T1;
and performing delay compensation according to the inherent delay value corresponding to the coding and decoding data frame.
In a second aspect, the present invention also discloses a coding and decoding system, which includes:
the channel configuration unit is used for establishing a plurality of independent channels, and each channel corresponds to a cache space;
the data receiving unit is used for controlling each channel to receive the data frame and buffer the data frame to the corresponding buffer space;
a data coding and decoding unit, configured to complete transmission and coding and decoding of data frames in each buffer space one buffer space at a time according to a preset scheduling policy, where the transmission and coding and decoding of the data frames include:
and reading a data frame in the cache space, transmitting the data frame to an RS codec, finishing the coding and decoding work of the data frame in the cache space, and obtaining a coded data frame.
On the basis of the technical scheme, the number of the readable addresses of each cache space is polled, the channel with the maximum readable address and the length larger than 1 code word is positioned, and the corresponding channel is authorized to obtain the next read operation permission.
On the basis of the above technical solution, the system further includes a data preprocessing unit, configured to perform data shaping on each data frame before the data receiving unit receives the data frame of the data receiving unit;
the data preprocessing unit is specifically configured to compare the data length of the data frame with a preset standard data length;
the data preprocessing unit is specifically configured to, when the data length of the data frame is consistent with the standard data length, normally transmit the data frame;
the data preprocessing unit is specifically configured to transmit only a portion of the data frame that conforms to the standard data length when the data length of the data frame is greater than the standard data length;
the data preprocessing unit is specifically configured to, when the data length of the data frame is smaller than the standard data length, adjust the data length of the data frame to the standard data length according to a preset compensation rule, and transmit the adjusted data frame.
Compared with the prior art, the invention has the advantages that:
(1) the invention respectively obtains the data frames from different sources by presetting the mutually independent channels, and codes and decodes the data frames in a plurality of channels in batches, thereby realizing the multi-channel coding and decoding work and meeting various work requirements.
(2) The invention keeps the output data envelope consistent with the input data envelope, has the same uniformity and avoids adverse impact on the buffer memory of a downstream module.
(3) The preset scheduling strategy of the invention completes the transmission and the coding and decoding of the data frames in each cache space one cache space at a time, avoids the bandwidth waste and effectively controls the occupancy rate of the cache space.
(5) In the invention, the delay conditions of data input and data output are controllable, so that the regulation and control of workers are facilitated, and various working requirements are met.
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FIG. 1 is a flowchart illustrating steps of a coding method according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating steps of a data sorting process in a coding/decoding method according to an embodiment of the present invention;
FIG. 3 is a flowchart illustrating steps of a data compensation process in a coding method according to an embodiment of the present invention;
FIG. 4 is a flowchart illustrating steps of RS (255,239) encoding and decoding for supporting 4-channel OTU4/OTU2 access in the encoding and decoding method according to an embodiment of the present invention;
FIG. 5 is a flowchart illustrating the internal processing of a 4-channel RS (255,239) code scheduler module in the encoding and decoding method according to an embodiment of the present invention;
FIG. 6 is a block diagram of a coding system according to a second embodiment of the present invention;
in the figure: 1. a channel configuration unit; 2. a data receiving unit; 3. a data coding and decoding unit; 4. a data preprocessing unit; 5. and a time delay compensation unit.
Detailed Description
Embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
The embodiment of the invention provides a coding and decoding method and system, which can carry out coding and decoding work on multi-channel data and meet various work requirements at the present stage.
In order to achieve the technical effects, the general idea of the application is as follows:
a method of coding, the method comprising the steps of:
s1, establishing a plurality of independent channels, wherein each channel corresponds to a cache space;
s2, each channel receives the data frame and buffers the data frame to the corresponding buffer space;
s3, according to the preset scheduling strategy, completing the transmission and coding of the data frames in each buffer space one buffer space at a time;
wherein, the transmission and coding and decoding of the data frame comprises:
and reading a data frame in a cache space, transmitting the data frame to an RS codec, finishing the coding and decoding of the data frame in the cache space, and obtaining a coded data frame.
Embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
Example 1
Referring to fig. 1 to 5, embodiment 1 of the present invention provides a coding and decoding method, including the following steps:
s1, establishing a plurality of independent channels, wherein each channel corresponds to a cache space;
s2, each channel receives the data frame and buffers the data frame to the corresponding buffer space;
s3, according to the preset scheduling strategy, completing the transmission and coding of the data frames in each buffer space one buffer space at a time;
wherein, the transmission and coding and decoding of the data frame comprises:
and reading a data frame in a cache space, transmitting the data frame to an RS codec, finishing the coding and decoding work of the data frame in the cache space, and obtaining a coded data frame.
In the embodiment of the invention, a plurality of mutually independent channels are established, each channel is respectively used for receiving data transmitted by different transmitting ends, and each channel is respectively provided with a cache space correspondingly, namely each channel is respectively provided with a dedicated cache space;
each channel receives the transmitted data frame and stores the received data frame into the corresponding buffer space;
and finally, starting to perform data coding and decoding work, and acquiring a data frame from a cache space for transmission and coding and decoding each time according to a preset scheduling strategy, wherein the transmission and coding and decoding of the data frame comprise:
and reading a data frame in a cache space, transmitting the data frame to an RS codec, finishing the coding and decoding work of the data frame in the cache space, and obtaining a coded data frame.
In addition, it should be noted that, the transmission and encoding and decoding of the data frames in each buffer space are completed one buffer space at a time, and since one data frame is obtained from one buffer space for transmission and encoding and decoding each time, the data frame obtained this time and the data frame obtained next time can be from the same buffer space or different buffer spaces, and the encoding and decoding work is finished when the data of each buffer space is completely read after multiple times of extraction and encoding and decoding.
According to the embodiment of the invention, the data frames are respectively obtained from different sources by presetting the mutually independent channels, and the data frames in the multiple channels are coded in batches, so that the coding and decoding work of multiple channels is realized, and various work requirements are met.
It should be noted that the encoding and decoding operation is mainly performed by the RS codec, and the processing bandwidth of the RS codec must be greater than the sum of the bandwidths of the channels, otherwise, if the bandwidth of each channel is greater than the processing bandwidth of the RS codec, data loss may be caused.
In another implementation manner in the embodiment of the present invention, the scheduling policy includes the following steps:
polling the number of the readable addresses in each cache space, positioning the channel with the maximum readable address and the length larger than 1 code word, and authorizing the corresponding channel to obtain the next read operation permission.
In a specific operation, one read operation can just continuously read the length of one RS code word from one channel, because the RS code is a block code and one code word is a related whole, if the coding and decoding are discontinuously processed, the temporary storage processing of the intermediate operation state is too complicated.
In addition, the scheduling method using the code word as the basic unit brings additional benefits: because one-time reading operation lasts for multiple beats, the operation of judging next authority distribution in the scheduling strategy can be completed in multiple beats, and high-speed realization of a digital circuit is facilitated;
the scheduling policy is specifically that, during one read operation, the number of readable addresses in the cache space of each channel is compared, the channel with the largest readable address and a length larger than one codeword obtains the permission of the next read operation, or all channels do not meet the authorization condition, and the channel enters an idle state.
The scheduling strategy in the embodiment of the invention brings the following advantages: 1. because the next scheduling authority is allocated to the channel with the largest number of readable addresses in the cache space in each channel, rather than allocating the authority according to the fixed rate of each channel, the balance of the waterlines of the cache spaces of each channel can be ensured, and the abnormal phenomenon that the waterlines of the cache spaces of the channels are burst or even overflow caused by the uniformity fluctuation of a certain channel data envelope can not occur; 2. since the right assignment of the next scheduling is already completed in the previous scheduling period, there may be no interval between the read operation of the previous scheduling and the read operation of the next scheduling, and bandwidth waste is not caused;
it should be noted that the pipeline is a metric for representing the total size of the data stored in the cache space.
In another implementation manner in the embodiment of the present invention, before each channel receives a data frame and buffers the data frame in a corresponding buffer space, the method further includes a data shaping process, where the data sorting process includes the following steps:
a1, comparing the data length of the data frame with a preset standard data length;
a2, when the data length of the data frame is consistent with the standard data length, the data frame is transmitted normally;
a3, when the data length of the data frame is larger than the standard data length, only transmitting the part of the data frame conforming to the standard data length;
and A4, when the data length of the data frame is smaller than the standard data length, adjusting the data length of the data frame to the standard data length according to a preset compensation rule, and transmitting the adjusted data frame.
Specifically, when the data length of a data frame is greater than the standard data length, only the part of the data frame conforming to the standard data length is transmitted, the part of the data frame exceeding the standard data length is not transmitted, a frame start indicating signal is detected, and when the frame start indicating signal appears, the data length of the next data frame is compared with the preset standard data length;
when the data length of the data frame is smaller than the standard data length, deleting the acquired frame start indication signal according to a preset compensation rule, adjusting the data length of the data frame to the standard data length, and transmitting the adjusted data frame;
the preset compensation rule may be that the length of the data frame is made to conform to the standard data length on the premise of not affecting the functional data in the data frame.
In a specific implementation, when performing a data shaping process, the specific operation method is as follows: a shaping state machine is defined, and the shaping state machine has 3 states: and normally, truncating and compensating, wherein the data frame in the normal state is output as it is, the data frame in the truncated state is not output, and the data frame in the compensated state is also output as it is.
The initialization state is a truncation state, the data frame is indicated to enter a normal state until a frame start indicating signal is received to be effective, if the received data beat number is continuously calculated in the normal state, and when the position of the frame start indicating signal theoretically should appear and actually also appears, the data frame is continuously kept in the normal state, otherwise, the data frame enters the truncation state, if the position of the frame start indicating signal theoretically should not appear and the frame start indicating signal actually appears in the normal state, namely the frame length of the received data frame is indicated to be smaller than a theoretical value, the frame start indicating effective signal is cleared firstly during output, then the data frame enters a compensation state, and when the frame length reaches the theoretical value, an effective signal is supplemented at the position where the frame start effective indication theoretically should appear;
the result of the data shaping process is that the output frame is always the frame with the standard interval, thereby avoiding the subsequent step from entering an abnormal state due to the abnormal frame.
In another implementation manner of the embodiment of the present invention, the method further includes the following steps:
carrying out first time delay processing on the data frame in the cache space;
specifically, the data frames in each buffer space are delayed according to the working requirement.
In specific implementation, the specific operation method of the first delay processing is as follows: the data effective indication signals are firstly beaten, the maximum beat number of the beating is the configurable maximum delay beat number, so that the optional output signals can be any one of the delay 1 beat number and the configurable maximum delay beat number, and the delay beat number corresponding to the actual configuration value is selected during actual output.
The minimum configuration value of the delay should be greater than the maximum time length required by the data frames of each channel from the receiving to the compiling to the outputting, otherwise, the function abnormity can be caused. By carrying out the first delay processing, the delay of each data frame passing through the multichannel multi-rate RS coder for coding and decoding in the embodiment of the invention is a fixed value, and in addition, the output data envelope and the input data envelope can be kept consistent and have the same uniformity, thereby avoiding adverse impact on the buffer memory of a downstream module.
In another implementation manner of the embodiment of the present invention, before correspondingly transmitting the encoded data frames to the corresponding output channels, the method further includes a data compensation process, where the data compensation process includes the following steps:
b1, acquiring a first delay value of the compiled code data frame in the first delay processing, and recording the first delay value as T1;
b2, acquiring a transmission delay value of a data frame corresponding to the compiled code data frame, which is stored in a buffer space at the beginning and the compiled code data frame is transmitted into a corresponding output channel, and recording the transmission delay value as T2;
b3, calculating the inherent delay value of the incoming channel corresponding to the coded data frame, and recording the inherent delay value as T3, wherein T3 is T2-T1;
and B4, performing delay compensation according to the inherent delay value corresponding to the coding data frame.
It should be noted that, in actual operation, a compensation buffer space is correspondingly allocated to each channel, and after the data frame of each channel is coded and decoded, a data compensation process is performed in the corresponding compensation buffer space.
In the embodiment of the invention, the compiled code data frames of each channel are written into the compensation cache space. The delay of the compiled data frame to reach the compensation buffer space is an indeterminate value due to the preceding operational steps. In order to make the delay of each data passing through the multi-channel multi-rate RS coder of the embodiment of the invention be a fixed value, a coded data frame needs to wait for a period of time in a compensation buffer space before being output so as to compensate the difference of the delay;
and then, after the data compensation process is finished, outputting the compiled code data frame processed by the data compensation process from the compensation cache space.
Here, a specific embodiment is given for the method mentioned in the embodiment of the present invention, and is explained by taking 4-channel RS (255,239) applied to the OTU2 and OTU4 as an example, but it should be noted that the present invention is also applicable to other situations where RS codes are used by FlexE, FlexO, and the like.
Fig. 4 is a flowchart of an RS (255,239) encoding and decoding process supporting 4-channel OTU4/OTU2 access according to an embodiment of the present invention, and includes 4 OTU frame shaping modules, 4 buffer space modules, 1 4-channel data valid indication signal delay module, 1 4-channel RS (255,239) code scheduling module, 1 RS (255,239) encoding and decoding module, 1 4-channel data distribution module, and 4 compensation FIFO modules. Wherein:
and the 4 OTU frame shaping modules are used for carrying out data arrangement flow on the 4 paths of OTU4/OTU2 services, so that the frame interval is always a standard value. Here, the 4-path access of the shaping module supports OTU2 service with 10G bandwidth and OTU4 service with 100G bandwidth;
the 4 cache space modules are used for caching 4 paths of OTU4/OTU2 data services;
the 4-channel data valid indication signal delay module is used for delaying a configurable fixed time length for the data valid indication signal;
the 4-channel RS (255,239) code scheduler module is used for reading the RS (255,239) code words from the buffer space and outputting the RS (255,239) code words to the RS (255,239) coding and decoding module;
a high-speed high-parallelism RS (255,239) codec module, where high speed refers to a high maximum operating clock frequency of a digital logic synthesis timing sequence, high parallelism refers to a parallelism of encoding or decoding, one clock beat requires processing of multiple RS symbols, for example, when a data bit width is 320 bits, one clock beat needs to process 320/8-40 RS (255,239) symbols, and the operating clock frequency and the parallelism jointly determine a maximum processing bandwidth of the codec;
the 4-channel data distribution module is used for distributing the data to each channel according to the data channel number synchronous with the data;
4 compensation buffer spaces, each channel corresponds to a compensation buffer space, which is used for compensating the difference between the time delay of the data from the inlet of the device to the compensation buffer space and the fixed time delay of the configured data from the inlet to the outlet of the device, the time delay of the compensated data from the inlet to the outlet of the device is a fixed value, and in addition, the read of the compensation buffer spaces enables the output of the time delay module of the data effective indication signal, so the compensation buffer spaces have the same envelope with the input data and have consistent uniformity.
Fig. 4 shows specific implementation steps of an RS (255,239) codec device supporting service access of an OTU4/OTU2 with 4 channels:
c1 and 4 OTU frame shapers respectively shape 4 paths of accessed OTU4/OTU2 services;
c2 and 4 cache spaces respectively cache the shaped 4 paths of OTU4/OTU2 service data;
the C3 and 4-channel data valid indication signal delay module delays the envelope of the 4-path OTU4/OTU2 service data;
the C4, 4-channel RS (255,239) code scheduler module reads out RS (255,239) code words from the buffer space and outputs the RS (255,239) code words to the RS (255,239) coding and decoding module;
c5, the high-speed high-parallelism RS (255,239) encoder or decoder module serially processes the service data from the 4 channels and carries out RS (255,239) encoding and decoding;
the C6 and 4 channel data distribution module distributes data to each parallel channel;
c7, writing the 4 channel data output in the step C6 into the corresponding compensation buffer space modules;
and C8, reading out the data from the 4 compensation buffer space modules by using the delayed envelope of each channel output in the step C3 as read enable, and outputting the data.
In the above step, the internal processing flow of the 4-channel RS (255,239) code scheduler module in step C4 is shown in fig. 5:
step D1, initializing, and scheduling to enter an idle state;
d2, polling each channel 0-3, when the number of readable addresses in a certain channel cache space is larger than the length of one RS (255,239) code word, obtaining scheduling authorization by the channel, and entering a scheduling state;
and D3, during the scheduling, judging the number of readable addresses in the buffer space of each channel No. 0-3, finding out the channel with the maximum length larger than one RS (255,239) code word, authorizing the channel to be an object of the next scheduling, and if no authorized object meets the condition, turning to the step D1.
In the frame structure of the OTU4/OTU2 in the embodiment of the present invention, OTUk frames all have the same frame structure, and are composed of 4 rows and 4080 columns, and the unit is 1 RS (255,239) symbol, that is, 8 bits,
each row consists of 16 interleaved RS (255,239) codewords, of which columns 1 to 3824 are information bits and columns 3825 to 4080 are check bits.
Based on the same inventive concept, the present application provides an embodiment of a coding system corresponding to the embodiment, which is detailed in the second embodiment
Example two
Referring to fig. 6, an embodiment of the present invention provides a coding and decoding system, where the coding and decoding system includes:
the channel configuration unit 1 is used for establishing a plurality of independent channels, and each channel corresponds to a cache space;
the data receiving unit 2 is used for controlling each channel to receive the data frame and buffer the data frame to the corresponding buffer space;
a data encoding and decoding unit 3, configured to complete transmission and encoding and decoding of data frames in each buffer space one buffer space at a time according to a preset scheduling policy, where the transmission and encoding and decoding of data frames include:
and reading a data frame in a cache space, transmitting the data frame to an RS codec, finishing the coding and decoding work of the data frame in the cache space, and obtaining a coded data frame.
In the embodiment of the invention, a plurality of mutually independent channels are established, each channel is respectively used for receiving data transmitted by different transmitting ends, and each channel is respectively provided with a cache space correspondingly, namely each channel is respectively provided with a dedicated cache space;
each channel receives the transmitted data frame and stores the received data frame into the corresponding buffer space;
and finally, starting to perform data coding and decoding work, and acquiring a data frame from a cache space for transmission and coding and decoding each time according to a preset scheduling strategy, wherein the transmission and coding and decoding of the data frame comprise:
and reading a data frame in a cache space, transmitting the data frame to an RS codec, finishing the coding and decoding work of the data frame in the cache space, and obtaining a coded data frame.
In addition, it should be noted that, transmission and compilation of data frames in each cache space are completed one cache space at a time, and since one data frame is acquired from one cache space each time for transmission and compilation, the data frame acquired this time and the data frame acquired next time may be from the same cache space or from different cache spaces, and the compilation operation is completed when data in each cache space is completely read after multiple times of extraction and compilation.
According to the embodiment of the invention, the data frames are respectively obtained from different sources by presetting the mutually independent channels, and the data frames in the multiple channels are compiled in batches, so that the multichannel coding and decoding work is realized, and various work requirements are met.
It should be noted that the encoding and decoding operation is mainly performed by the RS codec, and the processing bandwidth of the RS codec must be greater than the sum of the bandwidths of the channels, otherwise, if the bandwidth of each channel is greater than the processing bandwidth of the RS codec, data loss may be caused.
In another implementation manner of the embodiment of the present invention, the scheduling policy includes the following steps:
polling the number of the readable addresses in each cache space, positioning the channel with the maximum readable address and the length larger than 1 code word, and authorizing the corresponding channel to obtain the next read operation permission.
In a specific operation, one read operation can just continuously read the length of one RS code word from one channel, because the RS code is a block code and one code word is a related whole, if the coding and decoding are discontinuously processed, the temporary storage processing of the intermediate operation state is too complicated.
In addition, the scheduling method using the code word as the basic unit brings additional benefits: because one-time reading operation lasts for multiple beats, the operation of judging next authority distribution in the scheduling strategy can be completed in multiple beats, and high-speed realization of a digital circuit is facilitated;
the scheduling policy is specifically that, during one read operation, the number of readable addresses in the cache space of each channel is compared, the channel with the largest readable address and a length larger than one codeword obtains the permission of the next read operation, or all channels do not meet the authorization condition, and the channel enters an idle state.
In another implementation manner of the embodiment of the present invention, the system further includes a data preprocessing unit 4, configured to perform data shaping on each data frame before the data receiving unit receives the data frame of the data receiving unit;
the data preprocessing unit 4 is specifically configured to compare the data length of the data frame with a preset standard data length;
the data preprocessing unit 4 is specifically used for normally transmitting the data frame when the data length of the data frame is consistent with the standard data length;
the data preprocessing unit 4 is specifically configured to transmit a portion of the data frame that conforms to the standard data length and not transmit a portion of the data frame that exceeds the standard data length when the data length of the data frame is greater than the standard data length, and further compare the data length of the next data frame with a preset standard data length;
the data preprocessing unit 4 is specifically configured to, when the data length of the data frame is smaller than the standard data length, adjust the data length of the data frame to the standard data length according to a preset compensation rule, and transmit the adjusted data frame;
the preset compensation rule may be that the length of the data frame is made to conform to the standard data length on the premise of not affecting the functional data in the data frame.
In another implementation manner of the embodiment of the present invention, the system further includes a delay compensation unit 5, configured to perform a data compensation process;
the delay compensation unit 5 is configured to obtain a first delay value of the coded data frame during the first delay processing, and record the first delay value as T1;
the delay compensation unit 5 is further configured to obtain a transmission delay value when the data frame corresponding to the compiled code data frame starts to be stored in the buffer space and the compiled code data frame is transmitted into the corresponding output channel, and record the transmission delay value as T2;
the delay compensation unit 5 is further configured to calculate an inherent delay value of an incoming channel corresponding to the coded data frame, which is denoted as T3, where T3 is T2-T1;
the delay compensation unit 5 is further configured to perform delay compensation according to an inherent delay value corresponding to the coded data frame.
Based on the same inventive concept, the present application provides an embodiment of a storage medium corresponding to the embodiment described in the third embodiment
EXAMPLE III
A third embodiment of the invention provides a computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out all or part of the method steps of the first embodiment.
The present invention can implement all or part of the flow in the first embodiment, and can also be implemented by using a computer program to instruct related hardware, where the computer program can be stored in a computer-readable storage medium, and when the computer program is executed by a processor, the steps of the above-mentioned method embodiments can be implemented. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer readable medium may include: any entity or device capable of carrying computer program code, recording medium, U-disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-Only Memory (ROM), random-Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution media, and the like. It should be noted that the computer readable medium may contain other components which may be suitably increased or decreased as required by legislation and patent practice in jurisdictions, for example, in some jurisdictions, in accordance with legislation and patent practice, the computer readable medium does not include electrical carrier signals and telecommunications signals.
Based on the same inventive concept, the application provides an embodiment of a corresponding device, and the detailed description is given in the fourth embodiment
Example four
The fourth embodiment of the present invention further provides an apparatus, which includes a memory and a processor, wherein the memory stores a computer program running on the processor, and the processor executes the computer program to implement all or part of the method steps in the first embodiment.
The processor may be a Central Processing Unit (CP U), or may be other general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, discrete hardware component, or the like. The general purpose processor may be a microprocessor or the processor may be any conventional processor or the like, the processor being the control center of the computer device and the various interfaces and lines connecting the various parts of the overall computer device.
The memory may be used to store computer programs and/or modules, and the processor may implement various functions of the computer device by executing or executing the computer programs and/or modules stored in the memory, as well as by invoking data stored in the memory. The memory may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required by at least one function (such as a sound playing function, an image playing function, etc.), and the like; the storage data area may store data (such as audio data, video data, etc.) created according to the use of the cellular phone, etc. In addition, the memory may include high speed random access memory, and may also include non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), at least one magnetic disk storage device, a Flash memory device, or other volatile solid state storage device.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, server, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.
The present invention has been described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), servers and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A method of coding and decoding, the method comprising the steps of:
establishing a plurality of independent channels, wherein each channel corresponds to a cache space;
each channel receives a data frame and caches the data frame to a corresponding cache space;
according to a preset scheduling strategy, completing the transmission and coding of data frames in each buffer space one buffer space at a time; wherein, the transmission and coding and decoding of the data frame comprises:
and reading a data frame in the cache space, transmitting the data frame to an RS codec, finishing the coding and decoding work of the data frame in the cache space, and obtaining a coded data frame.
2. The method of claim 1, wherein the scheduling policy comprises the steps of:
polling the number of the readable addresses in each cache space, positioning the channel with the maximum readable address and the length larger than 1 code word, and authorizing the corresponding channel to obtain the next read operation permission.
3. The method of claim 1, wherein before each of the lanes receives the data frame and buffers it to the corresponding buffer space, the method further comprises a data shaping process, the data grooming process comprising the steps of:
comparing the data length of the data frame with a preset standard data length;
when the data length of the data frame is consistent with the standard data length, the data frame is normally transmitted;
when the data length of the data frame is larger than the standard data length, only transmitting the part of the data frame conforming to the standard data length;
and when the data length of the data frame is smaller than the standard data length, adjusting the data length of the data frame to the standard data length according to a preset compensation rule, and transmitting the adjusted data frame.
4. The method of claim 3, wherein:
and when the data length of the data frame is greater than the standard data length, only transmitting the part of the data frame conforming to the standard data length, detecting a frame start indicating signal, and when the frame start indicating signal appears, comparing the data length of the next data frame with the preset standard data length.
5. The method of claim 3, wherein:
and when the data length of the data frame is smaller than the standard data length, deleting the acquired frame start indication signal according to a preset compensation rule, adjusting the data length of the data frame to the standard data length, and transmitting the adjusted data frame.
6. The method of claim 1, further comprising the steps of:
and carrying out first time delay processing on the data frame in the buffer space.
7. The method of claim 6, wherein prior to transmitting said compiled code data frames to a corresponding output channel, said method further comprises a data compensation process, said data compensation process comprising the steps of:
acquiring a first delay value of the compiled code data frame during the first delay processing, and recording the first delay value as T1;
acquiring a transmission delay value of the data frame corresponding to the compiled code data frame, which is stored in the cache space at the beginning and is transmitted into the corresponding output channel by the compiled code data frame, and recording the transmission delay value as T2;
calculating an inherent delay value of the incoming channel corresponding to the compiled code data frame, and recording the inherent delay value as T3, wherein T3 is T2-T1;
and performing delay compensation according to the inherent delay value corresponding to the coding and decoding data frame.
8. A coding system, the system comprising:
the channel configuration unit is used for establishing a plurality of independent channels, and each channel corresponds to a cache space;
the data receiving unit is used for controlling each channel to receive the data frame and buffer the data frame to the corresponding buffer space;
a data coding and decoding unit, configured to complete transmission and coding and decoding of data frames in each buffer space one buffer space at a time according to a preset scheduling policy, where the transmission and coding and decoding of the data frames include:
and reading a data frame in the cache space, transmitting the data frame to an RS codec, finishing the coding and decoding work of the data frame in the cache space, and obtaining a coded data frame.
9. The system of claim 8, wherein the scheduling policy comprises the steps of:
polling the number of the readable addresses in each cache space, positioning the channel with the maximum readable address and the length larger than 1 code word, and authorizing the corresponding channel to obtain the next read operation permission.
10. The system of claim 8, further comprising a data pre-processing unit for data shaping each data frame prior to the data receiving unit receiving the data frame;
the data preprocessing unit is specifically configured to compare the data length of the data frame with a preset standard data length;
the data preprocessing unit is specifically configured to, when the data length of the data frame is consistent with the standard data length, normally transmit the data frame;
the data preprocessing unit is specifically configured to transmit only a portion of the data frame that conforms to the standard data length when the data length of the data frame is greater than the standard data length;
the data preprocessing unit is specifically configured to, when the data length of the data frame is smaller than the standard data length, adjust the data length of the data frame to the standard data length according to a preset compensation rule, and transmit the adjusted data frame.
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