CN111403411B - Three-dimensional memory and forming method thereof - Google Patents
Three-dimensional memory and forming method thereof Download PDFInfo
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- CN111403411B CN111403411B CN202010228715.8A CN202010228715A CN111403411B CN 111403411 B CN111403411 B CN 111403411B CN 202010228715 A CN202010228715 A CN 202010228715A CN 111403411 B CN111403411 B CN 111403411B
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- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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Abstract
The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a three-dimensional memory and a method for forming the same. The method for forming the three-dimensional memory comprises the following steps: providing a substrate, wherein the substrate comprises a substrate, a stacking structure, a channel hole, an epitaxial layer and a charge storage layer; forming a first treatment layer on the side wall surface of the charge storage layer and forming a second treatment layer on the bottom wall surface of the charge storage layer, wherein the first treatment layer has etching selectivity relative to the second treatment layer and the charge storage layer; removing the second treatment layer to expose the charge storage layer; and removing the charge storage layer at the bottom of the channel hole to expose the epitaxial layer. The invention avoids damage to the charge storage layer on the side wall of the channel hole and improves the electrical performance of the three-dimensional memory core region.
Description
Technical Field
The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a three-dimensional memory and a method for forming the same.
Background
With the development of planar flash memories, the production process of semiconductors has made tremendous progress. But in recent years, the development of planar flash memory has met with various challenges: physical limits, current development technology limits, stored electron density limits, and the like. In this context, to address the difficulties encountered with planar flash memories and the pursuit of lower unit cell production costs, various three-dimensional (3D) flash memory structures have been developed, such as 3D NOR flash and 3D NAND flash.
The 3D NAND memory uses the small volume and large capacity as starting points, uses the high integration of stacking the storage units layer by layer in a three-dimensional mode as a design concept, produces the memory with high storage density per unit area and high performance of the storage units, and has become the mainstream technology of the design and production of the emerging memory.
In the current manufacturing process of the 3D NAND memory, a sidewall penetration phenomenon often occurs in the memory function layer formed in the channel hole, thereby affecting the electrical performance of the core area of the three-dimensional memory, and even resulting in the rejection of the whole three-dimensional memory when serious.
Therefore, how to improve the electrical performance of the core area of the three-dimensional memory and ensure the integrity of the morphology of the memory functional layer is a technical problem to be solved currently.
Disclosure of Invention
The invention provides a three-dimensional memory and a forming method thereof, which are used for solving the problem of poor performance of the existing three-dimensional memory.
In order to solve the above problems, the present invention provides a method for forming a three-dimensional memory, comprising the steps of:
providing a substrate, wherein the substrate comprises a substrate, a stacking structure positioned on the surface of the substrate, a channel hole penetrating through the stacking structure, an epitaxial layer positioned on the surface of the substrate and exposed at the bottom of the channel hole, and a charge storage layer covering the inner wall of the channel hole and the surface of the epitaxial layer;
forming a first treatment layer on the side wall surface of the charge storage layer and forming a second treatment layer on the bottom wall surface of the charge storage layer, wherein the first treatment layer has etching selectivity relative to the second treatment layer and the charge storage layer;
selectively removing the second treatment layer by adopting a wet etching process to expose the charge storage layer;
and removing the charge storage layer at the bottom of the channel hole by adopting a wet etching process, and exposing the epitaxial layer.
Optionally, the specific steps of forming a first treatment layer on the sidewall surface of the charge storage layer and forming a second treatment layer on the bottom wall surface of the charge storage layer include:
forming a protective layer on the surfaces of the side wall and the bottom wall of the charge storage layer;
modifying the protective layer located on the side wall of the charge storage layer and/or the bottom wall of the charge storage layer to form the first treatment layer and the second treatment layer.
Optionally, the protective layer has a single-layer structure; or alternatively, the process may be performed,
the protective layer is a multi-layer structure sequentially stacked along the radial direction of the channel hole.
Optionally, the specific step of forming a protective layer on the side wall and bottom wall surfaces of the charge storage layer includes:
forming a first sub-layer on the side wall and bottom wall surfaces of the charge storage layer;
forming a second sub-layer covering the surface of the first sub-layer, wherein the second sub-layer has etching selectivity relative to the first sub-layer;
and forming a third sub-layer covering the surface of the second sub-layer, wherein the third sub-layer has etching selectivity relative to the second sub-layer, and the protective layer comprising the first sub-layer, the second sub-layer and the third sub-layer is formed.
Optionally, the specific step of modifying the protective layer located on the side wall of the charge storage layer and/or the bottom wall of the charge storage layer comprises:
modifying the third sub-layer located on the side wall of the second sub-layer and/or the bottom wall of the second sub-layer to form the first treated layer located on the side wall of the second sub-layer and the second treated layer located on the bottom wall of the second sub-layer.
Optionally, the specific steps of forming the first treatment layer on the sidewall of the second sub-layer and the second treatment layer on the bottom wall of the second sub-layer include:
implanting a doping element into the third sub-layer located on the bottom wall of the second sub-layer to form the second processing layer;
oxidizing the third sub-layer on the sidewall of the second sub-layer to form the first treated layer.
Optionally, the material of the third sub-layer is polysilicon;
the doping element is nitrogen.
Optionally, the specific step of exposing the charge storage layer includes:
and selectively removing the second treatment layer, the second sub-layer positioned on the bottom wall of the charge storage layer and the first sub-layer positioned on the bottom wall of the charge storage layer by adopting a wet etching process to expose the charge storage layer.
Optionally, the charge storage layer includes a blocking layer covering the sidewall of the channel hole and the surface of the epitaxial layer, a charge trapping layer covering the surface of the blocking layer, and a tunneling layer covering the surface of the charge trapping layer; the first treatment layer and the tunneling layer are made of the same material; the specific step of removing the charge storage layer at the bottom of the channel hole further comprises the following steps:
and simultaneously removing the first treatment layer and the tunneling layer positioned on the bottom wall of the channel hole by adopting a wet etching process, and exposing the charge trapping layer and the second sub-layer positioned on the side wall of the charge storage layer.
Optionally, the second sub-layer is the same material as the charge trapping layer; the specific step of removing the charge storage layer at the bottom of the channel hole further comprises the following steps:
and simultaneously removing the second sub-layer and the charge trapping layer positioned on the bottom wall of the channel hole by adopting a wet etching process, and exposing the blocking layer and the first sub-layer positioned on the side wall of the charge storage layer.
Optionally, the barrier layer has an etch selectivity with respect to the first sub-layer; the specific step of removing the charge storage layer at the bottom of the channel hole further comprises the following steps:
removing the blocking layer on the bottom wall of the channel hole by adopting a wet etching process to expose the epitaxial layer;
and removing the first sub-layer by adopting a wet etching process.
In order to solve the above problems, the present invention also provides a three-dimensional memory including:
the substrate comprises a substrate, a stacking structure positioned on the surface of the substrate, a channel hole penetrating through the stacking structure, and an epitaxial layer positioned on the surface of the substrate and exposed at the bottom of the channel hole;
the charge storage layer is covered on the inner wall of the channel hole, an opening exposing the epitaxial layer is formed in the bottom of the charge storage layer, the opening is formed by removing the second processing layer and the charge storage layer at the bottom of the channel hole after the side wall of the charge storage layer covers the first processing layer and the bottom wall of the charge storage layer covers the second processing layer, and the first processing layer has etching selectivity relative to the second processing layer and the charge storage layer.
Optionally, the material of the second treatment layer is a polysilicon material doped with nitrogen element, and the material of the first treatment layer is an oxide material.
Optionally, the first treatment layer is a single-layer structure or a multi-layer structure sequentially stacked along the radial direction of the channel hole;
the second treatment layer is of a single-layer structure or a multi-layer structure which is sequentially overlapped along the radial direction of the channel hole.
Optionally, a first sub-layer and a second sub-layer are disposed between the charge storage layer and the first processing layer and between the charge storage layer and the second processing layer, the second sub-layer is located on a side of the first sub-layer facing away from the charge storage layer, and the second sub-layer has etching selectivity with respect to the first sub-layer.
Optionally, the charge storage layer includes a blocking layer, a charge trapping layer, and a tunneling layer sequentially stacked along a radial direction of the channel hole;
the material of the first treatment layer is the same as that of the tunneling layer, so that the tunneling layer and the first treatment layer can be removed simultaneously in the process of forming the opening.
Optionally, the second sub-layer is of the same material as the charge-trapping layer, such that the charge-trapping layer and the second sub-layer can be removed simultaneously during formation of the opening.
Optionally, the barrier layer has an etch selectivity with respect to the first sub-layer.
Optionally, the material of the first sub-layer is a polysilicon material.
According to the three-dimensional memory and the forming method thereof, the first treatment layer and the second treatment layer are respectively formed on the side wall surface and the surface of the charge storage layer in the channel hole, and the first treatment layer and the second treatment layer are controlled to have etching selectivity relative to each other and also have etching selectivity relative to the charge storage layer, so that the second treatment layer and the charge storage layer at the bottom of the channel hole can be selectively removed through a process in the subsequent process, damage to the charge storage layer on the side wall of the channel hole is avoided, the integrity of the side wall morphology of the charge storage layer is ensured, the electrical performance of a core area of the three-dimensional memory is improved, and the yield of the three-dimensional memory is improved.
Drawings
FIG. 1 is a flow chart of a method for forming a three-dimensional memory in an embodiment of the invention;
figures 2A-2H are schematic cross-sectional views of the main process of forming a three-dimensional memory according to embodiments of the present invention.
Detailed Description
The following describes in detail embodiments of a three-dimensional memory and a method for forming the same provided by the present invention with reference to the accompanying drawings.
After a channel hole is etched in a core area of the 3D NAND memory, an epitaxial layer is formed at the bottom of the channel hole, a charge storage layer is formed on the inner wall of the channel hole, the bottom of the charge storage layer is opened through a dry etching process, the epitaxial layer is exposed, and finally the channel layer is formed on the surfaces of the charge storage layer and the epitaxial layer, so that the channel layer is electrically connected with the epitaxial layer. The channel layer and the charge storage layer together serve as a channel function layer. However, during the process of opening the bottom of the charge storage layer by using the dry etching process, the plasma bombards the charge storage layer on the sidewall of the channel hole, which is very easy to cause breakdown of the charge storage layer, so that the electrical performance of the core area is reduced, and even the memory is scrapped. This phenomenon is more pronounced in three-dimensional memories having a dual stack channel hole structure, where there is a problem of misalignment of the alignment marks.
In order to reduce the risk of breakdown of the charge storage layer on the sidewall of the channel hole, the present embodiment provides a method for forming a three-dimensional memory, fig. 1 is a flowchart of a method for forming a three-dimensional memory according to an embodiment of the present invention, and fig. 2A-2H are schematic cross-sectional views of main processes of the embodiment of the present invention in the process of forming the three-dimensional memory. The three-dimensional memory described in this embodiment may be, but is not limited to, a 3D NAND memory, such as a 3D NAND memory having a dual stack channel hole structure. As shown in fig. 1 and fig. 2A to fig. 2H, the method for forming a three-dimensional memory according to the present embodiment includes the following steps:
in step S11, a base is provided, where the base includes a substrate 20, a stacked structure 21 located on a surface of the substrate 20, a channel hole 25 penetrating through the stacked structure 21, an epitaxial layer 30 located on a surface of the substrate 20 and exposed at a bottom of the channel hole 25, and a charge storage layer covering an inner wall of the channel hole 25 and a surface of the epitaxial layer 25, as shown in fig. 2A.
In particular, the material of the substrate 20 may be, but is not limited to, silicon. The stacked structure 21 includes interlayer insulating layers 211 and sacrificial layers 212 alternately stacked on the surface of the substrate 20 in a direction perpendicular to the substrate 20. The material of the interlayer insulating layer 211 may be an oxide material (e.g., silicon dioxide), and the material of the sacrificial layer 212 may be a nitride material (e.g., silicon nitride). The number of stacked layers of the stacked structure 21 can be set by those skilled in the art according to actual needs, and may be 32 layers, 64 layers or 128 layers, for example. In this embodiment, a buffer oxide layer 22 and a dielectric layer 23 may also be disposed between the substrate 20 and the stacked structure 21. After the stacked structure 21 is formed, a channel hole 25 penetrating the stacked structure 21 is formed by an etching process, and the epitaxial layer 30 is grown at the bottom of the channel hole 25. A person skilled in the art may also form an auxiliary layer 24 on the surface of the epitaxial layer 30 to avoid damage to the epitaxial layer 30 during the subsequent etching process. The material of the auxiliary layer 24 may be an oxide material. Thereafter, the charge storage layer is deposited on the inner wall of the channel hole 25, and covers the surface of the auxiliary layer 24.
In step S12, a first process layer 29 is formed on the sidewall surface of the charge storage layer, and a second process layer 28 is formed on the bottom wall surface of the charge storage layer, wherein the first process layer 29 has etching selectivity with respect to both the second process layer 28 and the charge storage layer, as shown in fig. 2C.
Specifically, the first process layer 29 and the second process layer 28 are formed on the side wall and bottom wall surfaces of the charge storage layer, respectively, and the first process layer 29 is controlled to have etching selectivity with respect to the second process layer 28, so that the second process layer 28 can be selectively removed by a wet etching process, without damaging the first process layer 29, thereby protecting the charge storage layer on the side wall of the channel hole 25. The specific method for forming the first treatment layer 29 on the sidewall surface of the charge storage layer and forming the second treatment layer 28 on the bottom wall surface of the charge storage layer may be selected by those skilled in the art according to actual needs, and this embodiment is not limited as long as the first treatment layer 29 and the second treatment layer 28 having etching selectivity with respect to each other can be formed on the sidewall and the bottom wall of the charge storage layer.
Optionally, the specific steps of forming the first treatment layer 29 on the sidewall surface of the charge storage layer and forming the second treatment layer 28 on the bottom wall surface of the charge storage layer include:
forming a protective layer on the surfaces of the side wall and the bottom wall of the charge storage layer;
the modification treatment is performed on the protective layer located on the side wall of the charge storage layer and/or on the bottom wall of the charge storage layer, forming the first treatment layer 29 and the second treatment layer 28.
Specifically, in order to simplify the process steps, the first process layer 29 and the second process layer 28 may be formed by forming the protective layer over the entire surface of the charge storage layer, and then subjecting the protective layer on the side wall of the charge storage layer to a modification treatment, subjecting the protective layer on the bottom wall of the charge storage layer to a modification treatment, or subjecting the charge storage layers on the side wall and the bottom wall of the charge storage layer to a modification treatment, respectively. The specific manner of the modification treatment can be selected by those skilled in the art according to actual needs, such as oxidation, ion implantation, and the like.
Optionally, the protective layer has a single-layer structure; or alternatively, the process may be performed,
the protective layer is a multi-layer structure sequentially stacked along the radial direction of the channel hole.
Optionally, the specific step of forming a protective layer on the side wall and bottom wall surfaces of the charge storage layer includes:
forming a first sub-layer 271 on the side and bottom wall surfaces of the charge storage layer;
forming a second sub-layer 272 covering the surface of the first sub-layer 271, wherein the second sub-layer 272 has etching selectivity relative to the first sub-layer 271;
a third sub-layer 273 is formed to cover the surface of the second sub-layer 272, the third sub-layer 273 has etching selectivity with respect to the second sub-layer 272, and the protective layer including the first sub-layer 271, the second sub-layer 272 and the third sub-layer 273 is formed as shown in fig. 2A.
Optionally, the specific step of modifying the protective layer located on the side wall of the charge storage layer and/or the bottom wall of the charge storage layer comprises:
modifying the third sub-layer 273 located on the side wall of the second sub-layer 272 and/or the bottom wall of the second sub-layer 272 forms the first treated layer 29 located on the side wall of the second sub-layer 272 and the second treated layer 28 located on the bottom wall of the second sub-layer 272.
Optionally, the specific steps of forming the first treatment layer 29 on the sidewall of the second sub-layer 272 and the second treatment layer 28 on the bottom wall of the second sub-layer 272 include:
implanting doping elements into the third sub-layer 273 located on the bottom wall of the second sub-layer 272, forming the second process layer 28, as shown in fig. 2B;
the third sub-layer 273 on the sidewall of the second sub-layer 272 is oxidized to form the first handle layer 29, as shown in fig. 2C.
Optionally, the material of the third sub-layer 273 is polysilicon;
the doping element is nitrogen.
Hereinafter, the material of the first sub-layer 271 is a polysilicon material, the material of the second sub-layer 272 is a nitride material, and the material of the third sub-layer 273 is a polysilicon material. After the charge storage layer is formed, the first sub-layer 271 is deposited over the entire surface of the charge storage layer, the second sub-layer 272 is deposited over the entire surface of the first sub-layer 271, and the third sub-layer 273 is deposited over the entire surface of the second sub-layer 272, i.e., the first sub-layer 271, the second sub-layer 272, and the third sub-layer 273 are sequentially stacked in the radial direction of the channel hole 25, as shown in fig. 2A. Then, nitrogen is injected into the third sub-layer 273 on the bottom wall of the channel hole 25 in the direction perpendicular to the substrate 20, and the material at the bottom of the third sub-layer 273 is modified into polysilicon material doped with nitrogen, so that the second process layer 28 is formed, as shown in fig. 2B. Then, an oxidizing gas such as oxygen is transferred into the trench 25, and the third sub-layer 273 on the sidewall of the trench 25 is oxidized to form the first treatment layer 29 made of silicon oxide, as shown in fig. 2C. In the oxidation process, on one hand, the second treatment layer 28 is not easily oxidized due to the doping of nitrogen element; on the other hand, the first sub-layer 271, which is made of polysilicon, is not oxidized due to the blocking effect of the second sub-layer 272. The first process layer 29 of silicon oxide and the second process layer 28 of polysilicon doped with nitrogen have an etch selectivity therebetween.
In step S13, the second processing layer 28 is removed, exposing the charge storage layer, as shown in fig. 2D.
In order to avoid the damage to the first handle layer 29 caused by the plasma bombardment during the dry etching process, thereby ensuring that the first handle layer 29 can protect the charge storage layer located on the sidewall of the channel hole 25 during the removal of the second handle layer 28, a wet etching process is optionally used to selectively remove the second handle layer 28.
Optionally, the specific step of exposing the charge storage layer includes:
the second handle layer 28, the second sub-layer 272 on the bottom wall of the charge storage layer, and the first sub-layer 271 on the bottom wall of the charge storage layer are selectively removed using a wet etch process, exposing the charge storage layer.
For example, due to the etch selectivity between the first handle layer 29 and the second handle layer 28, the second handle layer 28 may be removed by a wet etch process by selecting an appropriate etching reagent, exposing the second sub-layer 272, and retaining the first handle layer 29. Then, since the material of the first processing layer 29 is silicon oxide and the material of the second sub-layer 272 is silicon nitride, the second sub-layer 272 on the bottom wall of the channel hole 25 may be selectively removed by a wet etching process, and the first processing layer 29 remains. The material of the first sub-layer 271 is polysilicon, so that the first sub-layer 271 on the bottom wall of the channel hole 25 can be selectively removed by wet etching, and the first processing layer 29 will remain, so as to obtain the structure shown in fig. 2D. In the process of exposing the charge storage layer, a wet etching process is adopted, so that the bombardment of plasmas on the film layer on the side wall of the channel hole 25 in the dry etching process is avoided, and the integrity of the shape of the side wall of the charge storage layer is ensured.
In step S14, the charge storage layer at the bottom of the channel hole 25 is removed, exposing the epitaxial layer 30, as shown in fig. 2G.
In order to avoid the damage to the film layer on the sidewall of the channel hole 25 caused by the plasma bombardment during the dry etching, a wet etching process is optionally used to remove the charge storage layer at the bottom of the channel hole 25, so as to expose the epitaxial layer 30.
Optionally, the charge storage layer includes a blocking layer 261 covering the sidewall of the channel hole 25 and the surface of the epitaxial layer 30, a charge trapping layer 262 covering the surface of the blocking layer 261, and a tunneling layer 263 covering the surface of the charge trapping layer 262; the first handle layer 29 is the same material as the tunneling layer 263; the specific step of removing the charge storage layer at the bottom of the channel hole 25 further includes:
the first process layer 29 and the tunneling layer 263 on the bottom wall of the channel hole 25 are simultaneously removed using a wet etching process, exposing the charge trapping layer 262 and the second sub-layer 272 on the side wall of the charge storage layer, as shown in fig. 2E.
For example, the materials of the first processing layer 29 and the tunneling layer 263 are both silicon oxide, the first processing layer 29 has etching selectivity with respect to the second sub-layer 272 made of silicon nitride, the tunneling layer 263 also has etching selectivity with respect to the charge trapping layer 262 made of nitride, and by selecting a suitable etching reagent, the second sub-layer 272 and the charge trapping layer 262 can be used as etching stop layers, and the first processing layer 29 and the tunneling layer 263 can be removed simultaneously by a one-step wet etching process, so as to form the structure shown in fig. 2E.
Optionally, the second sub-layer 272 is the same material as the charge-trapping layer 262; the specific step of removing the charge storage layer at the bottom of the channel hole 25 further includes:
the second sub-layer 272 and the charge trapping layer 262 on the bottom wall of the channel hole 25 are removed simultaneously using a wet etching process, exposing the blocking layer 261 and the first sub-layer 271 on the side wall of the charge storage layer, as shown in fig. 2F.
For example, the materials of the second sub-layer 272 and the charge-trapping layer 262 are both silicon nitride, the second sub-layer 272 has etching selectivity with respect to the first sub-layer 271 made of polysilicon, the charge-trapping layer 262 has etching selectivity with respect to the blocking layer 261 made of oxide, and by selecting a suitable etching reagent, the first sub-layer 271 and the blocking layer 261 can be used as etching stop layers, and the second sub-layer 272 and the charge-trapping layer 262 can be removed simultaneously by a one-step etching process, so as to form the structure shown in fig. 2F.
Optionally, the barrier layer 261 has an etching selectivity with respect to the first sub-layer 271; the specific step of removing the charge storage layer at the bottom of the channel hole 25 further includes:
removing the blocking layer 261 on the bottom wall of the channel hole 25 by a wet etching process, and exposing the epitaxial layer 30, as shown in fig. 2G;
the first sub-layer 271 is removed using a wet etch process, as shown in fig. 2H.
For example, the barrier layer 261 made of silicon oxide has etching selectivity with respect to the first sub-layer 271 made of polysilicon, and when the material of the auxiliary layer 24 is also silicon oxide, the barrier layer 261 and the auxiliary layer 24 located on the bottom of the channel hole 25 may be removed by a wet etching process by selecting an appropriate etching agent, so as to form an opening 31 exposing the epitaxial layer 30, as shown in fig. 2G. During the etching process of this step, the charge storage layer on the sidewall of the channel hole 25 is not etched due to the protection of the first sub-layer 271, and is not damaged by the plasma bombardment. Finally, an appropriate etching reagent is selected, and the first sub-layer 271 is removed by a wet etching process, so as to obtain the structure shown in fig. 2H. Thereafter, a polysilicon material may also be deposited on the charge storage layer surface and the epitaxial layer 30 surface to form a channel layer.
Furthermore, the present embodiment also provides a three-dimensional memory. The three-dimensional memory provided in this embodiment may be formed by using the method for forming a three-dimensional memory described in any one of the above. The specific structure of the three-dimensional memory can be seen in fig. 2A-2H. As shown in fig. 2A to 2H, the three-dimensional memory provided in this embodiment includes:
a base including a substrate 20, a stacked structure 21 located on the surface of the substrate, a channel hole 25 penetrating through the stacked structure 21, and an epitaxial layer 30 located on the surface of the substrate 20 and exposed at the bottom of the channel hole 25;
the charge storage layer covers the inner wall of the channel hole 25, and the bottom of the charge storage layer has an opening 31 exposing the epitaxial layer 30, the opening 31 is formed by removing the second processing layer 28 and the charge storage layer at the bottom of the channel hole 25 after the sidewall of the charge storage layer covers the first processing layer 29 and the bottom wall of the charge storage layer covers the second processing layer 28, and the first processing layer 29 has etching selectivity relative to the second processing layer 28 and the charge storage layer.
In particular, the material of the substrate 20 may be, but is not limited to, silicon. The stacked structure 21 includes interlayer insulating layers 211 and sacrificial layers 212 alternately stacked on the surface of the substrate 20 in a direction perpendicular to the substrate 20. The material of the interlayer insulating layer 211 may be an oxide material (e.g., silicon dioxide), and the material of the sacrificial layer 212 may be a nitride material (e.g., silicon nitride). The first process layer 29 is controlled to have etching selectivity with respect to the second process layer 28, so that the second process layer 28 can be selectively removed by a subsequent wet etching process without damaging the first process layer 29, thereby protecting the charge storage layer located on the sidewall of the channel hole 25, so that the charge storage layer after the opening 31 is formed has a flat surface. Optionally, the etching selectivity between the first processing layer 29 and the second processing layer 28 is greater than 3, and the etching selectivity between the first processing layer 29 and the charge storage layer is also greater than 3. The first handle layer 29 and the second handle layer 28 may be formed using a deposition process in combination with ion implantation and/or oxidation processes.
Optionally, the three-dimensional memory further comprises an auxiliary layer 24, and the opening 31 penetrates the auxiliary layer 24 in a direction perpendicular to the substrate 20. The auxiliary layer 24 is used to avoid damage to the epitaxial layer 30 during the subsequent etching process to form the opening 31. The material of the auxiliary layer 24 may be, but is not limited to, an oxide material.
Optionally, the material of the second treatment layer 28 is a polysilicon material doped with nitrogen element, and the material of the first treatment layer 29 is an oxide material.
Alternatively, the first treatment layer 29 may have a single-layer structure or a multi-layer structure sequentially stacked in the radial direction of the channel hole 25;
the second process layer 28 is a single-layer structure or a multi-layer structure sequentially stacked in the radial direction of the channel hole 25.
Optionally, a first sub-layer 271 and a second sub-layer 272 are provided between the charge storage layer and the first processing layer 29 and between the charge storage layer and the second processing layer 28, the second sub-layer 272 is located on a side of the first sub-layer 271 facing away from the charge storage layer, and the second sub-layer 272 has etching selectivity with respect to the first sub-layer 271.
Specifically, the first sub-layer 271 continuously covers the entire surface of the charge storage layer, the second sub-layer 272 continuously covers the entire surface of the first sub-layer 271 facing away from the charge storage layer, that is, the first sub-layer 271 and the second sub-layer 272 are sequentially stacked in the radial direction of the channel hole 25, the first treated layer 29 covers the sidewall surface of the second sub-layer 272, and the second treated layer 28 covers the sidewall surface of the first sub-layer 271.
Optionally, the charge storage layer includes a blocking layer 261, a charge trapping layer 262, and a tunneling layer 263 sequentially stacked in a radial direction of the channel hole 25;
the material of the first treatment layer 29 is the same as that of the tunneling layer 263, so that the tunneling layer 263 and the first treatment layer 29 can be removed simultaneously in the process of forming the opening 31.
For example, the materials of the first processing layer 29 and the tunneling layer 263 are both silicon oxide, the first processing layer 29 has etching selectivity with respect to the second sub-layer 272 made of silicon nitride, the tunneling layer 263 also has etching selectivity with respect to the charge trapping layer 262 made of nitride, and by selecting a suitable etching reagent, the second sub-layer 272 and the charge trapping layer 262 can be used as etching stop layers, and the first processing layer 29 and the tunneling layer 263 can be removed simultaneously by a one-step wet etching process.
Optionally, the second sub-layer 272 is the same material as the charge-trapping layer, such that the charge-trapping layer 262 and the second sub-layer 272 can be removed simultaneously during formation of the opening 31.
For example, the materials of the second sub-layer 272 and the charge-trapping layer 262 are both silicon nitride, the second sub-layer 272 has etching selectivity with respect to the first sub-layer 271 made of polysilicon, the charge-trapping layer 262 has etching selectivity with respect to the blocking layer 261 made of oxide, and by selecting a suitable etching reagent, the first sub-layer 271 and the blocking layer 261 can be used as etching stop layers, and the second sub-layer 272 and the charge-trapping layer 262 can be removed simultaneously by a one-step etching process.
Optionally, the barrier layer 261 has an etch selectivity with respect to the first sub-layer 271.
Optionally, the material of the first sub-layer 271 is a polysilicon material.
Specifically, the material of the blocking layer 261 is an oxide material, which has a high etching selectivity with respect to the polysilicon material, so that the first sub-layer 271 can protect the charge storage layer of the sidewall of the channel hole 25. Thereafter, an appropriate etching reagent is selected, and the first sub-layer 271 is removed by a wet etching process.
The three-dimensional memory further includes a channel layer overlying the charge storage layer surface and the epitaxial layer 30 surface.
According to the three-dimensional memory and the forming method thereof, the first treatment layer and the second treatment layer are respectively formed on the side wall surface and the surface of the charge storage layer in the channel hole, and the first treatment layer and the second treatment layer are controlled to have etching selectivity relative to each other and also have etching selectivity relative to the charge storage layer, so that the second treatment layer and the charge storage layer at the bottom of the channel hole can be selectively removed through an etching process in the subsequent process, damage to the charge storage layer on the side wall of the channel hole is avoided, the integrity of the side wall morphology of the charge storage layer is ensured, the electrical performance of a core area of the three-dimensional memory is improved, and the yield of the three-dimensional memory is improved.
The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.
Claims (14)
1. A method for forming a three-dimensional memory, comprising the steps of:
providing a substrate, wherein the substrate comprises a substrate, a stacking structure positioned on the surface of the substrate, a channel hole penetrating through the stacking structure, an epitaxial layer positioned on the surface of the substrate and exposed at the bottom of the channel hole, and a charge storage layer covering the inner wall of the channel hole and the surface of the epitaxial layer;
forming a first sub-layer on the side wall and bottom wall surfaces of the charge storage layer;
forming a second sub-layer covering the surface of the first sub-layer, wherein the second sub-layer has etching selectivity relative to the first sub-layer;
forming a third sub-layer covering the surface of the second sub-layer, wherein the third sub-layer has etching selectivity relative to the second sub-layer, and forming a protective layer comprising the first sub-layer, the second sub-layer and the third sub-layer;
modifying the third sub-layer positioned on the side wall of the second sub-layer and/or the bottom wall of the second sub-layer to form a first treatment layer positioned on the side wall of the second sub-layer and a second treatment layer positioned on the bottom wall of the second sub-layer, wherein the first treatment layer has etching selectivity relative to the second treatment layer and the charge storage layer;
removing the second treatment layer to expose the charge storage layer;
and removing the charge storage layer at the bottom of the channel hole to expose the epitaxial layer.
2. The method of forming a three-dimensional memory according to claim 1, wherein the specific steps of forming the first processed layer on the sidewall of the second sub-layer and the second processed layer on the bottom wall of the second sub-layer include:
implanting a doping element into the third sub-layer located on the bottom wall of the second sub-layer to form the second processing layer;
oxidizing the third sub-layer on the sidewall of the second sub-layer to form the first treated layer.
3. The method of claim 2, wherein the material of the third sub-layer is polysilicon;
the doping element is nitrogen.
4. The method of claim 2, wherein exposing the charge storage layer comprises:
and selectively removing the second treatment layer, the second sub-layer positioned on the bottom wall of the charge storage layer and the first sub-layer positioned on the bottom wall of the charge storage layer by adopting a wet etching process to expose the charge storage layer.
5. The method of claim 4, wherein the charge storage layer comprises a blocking layer covering the sidewall of the channel hole and the surface of the epitaxial layer, a charge trapping layer covering the surface of the blocking layer, and a tunneling layer covering the surface of the charge trapping layer; the first treatment layer and the tunneling layer are made of the same material; the specific step of removing the charge storage layer at the bottom of the channel hole further comprises the following steps:
and simultaneously removing the first treatment layer and the tunneling layer positioned on the bottom wall of the channel hole by adopting a wet etching process, and exposing the charge trapping layer and the second sub-layer positioned on the side wall of the charge storage layer.
6. The method of claim 5, wherein the second sub-layer is the same material as the charge trapping layer; the specific step of removing the charge storage layer at the bottom of the channel hole further comprises the following steps:
and simultaneously removing the second sub-layer and the charge trapping layer positioned on the bottom wall of the channel hole by adopting a wet etching process, and exposing the blocking layer and the first sub-layer positioned on the side wall of the charge storage layer.
7. The method of claim 6, wherein the barrier layer is etch selective with respect to the first sub-layer; the specific step of removing the charge storage layer at the bottom of the channel hole further comprises the following steps:
removing the blocking layer on the bottom wall of the channel hole by adopting a wet etching process to expose the epitaxial layer;
and removing the first sub-layer by adopting a wet etching process.
8. A three-dimensional memory, comprising:
the substrate comprises a substrate, a stacking structure positioned on the surface of the substrate, a channel hole penetrating through the stacking structure, and an epitaxial layer positioned on the surface of the substrate and exposed at the bottom of the channel hole; the charge storage layer covers the inner wall of the channel hole, an opening exposing the epitaxial layer is formed in the bottom of the charge storage layer, after the side wall of the charge storage layer covers the first processing layer and the bottom wall of the charge storage layer covers the second processing layer, the second processing layer and the charge storage layer at the bottom of the channel hole are removed to form the charge storage layer, the first processing layer has etching selectivity relative to the second processing layer and the charge storage layer, a first sub-layer and a second sub-layer are arranged between the charge storage layer and the first processing layer and between the charge storage layer and the second processing layer, the second sub-layer is located on one side, away from the charge storage layer, of the first sub-layer, and the second sub-layer has etching selectivity relative to the first sub-layer.
9. The three-dimensional memory according to claim 8, wherein the material of the second processing layer is a polysilicon material doped with nitrogen element and the material of the first processing layer is an oxide material.
10. The three-dimensional memory according to claim 8, wherein the first processing layer is a single-layer structure or a multi-layer structure stacked in order along a radial direction of the channel hole;
the second treatment layer is of a single-layer structure or a multi-layer structure which is sequentially overlapped along the radial direction of the channel hole.
11. The three-dimensional memory according to claim 8, wherein the charge storage layer comprises a blocking layer, a charge trapping layer, and a tunneling layer stacked in this order in a radial direction of the channel hole;
the material of the first treatment layer is the same as that of the tunneling layer, so that the tunneling layer and the first treatment layer can be removed simultaneously in the process of forming the opening.
12. The three-dimensional memory of claim 11, wherein the second sub-layer is of the same material as the charge-trapping layer such that the charge-trapping layer and the second sub-layer can be removed simultaneously during formation of the opening.
13. The three-dimensional memory of claim 11, wherein the barrier layer is etch selective with respect to the first sub-layer.
14. The three-dimensional memory of claim 13, wherein the material of the first sub-layer is a polysilicon material.
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