CN111400995A - Layout optimization method and layout optimization system - Google Patents
Layout optimization method and layout optimization system Download PDFInfo
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- CN111400995A CN111400995A CN201911321133.8A CN201911321133A CN111400995A CN 111400995 A CN111400995 A CN 111400995A CN 201911321133 A CN201911321133 A CN 201911321133A CN 111400995 A CN111400995 A CN 111400995A
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Abstract
The invention provides a layout optimization method which comprises the steps of carrying out time sequence analysis on a circuit, extracting time sequence key devices from the time sequence devices, sorting the time sequence key devices according to time sequence margins, selecting one time sequence key device, calculating a deviation value, judging that the deviation value is greater than a deviation threshold value, carrying out position optimization processing, and sequentially selecting the time sequence key devices according to the sorting until the position optimization processing of all the time sequence key devices is completed. And the deviation value is greater than a deviation threshold value, and the time sequence key devices are sequentially selected according to the sequence for position optimization processing, so that the positions of all the time sequence key devices are optimized, the mutual influence among the time sequence key devices is avoided, the time delay of the time sequence key devices is reduced, and the time sequence optimization effect is improved. The invention also provides a layout optimization system for realizing the layout optimization method.
Description
Technical Field
The present invention relates to the field of integrated circuit technologies, and in particular, to a layout optimization method and a layout optimization system.
Background
The global layout method of the time sequence drive of the integrated circuit usually adopts indirect methods such as net weighting and the like to optimize the chip time sequence quality of the layout, so that the chip time sequence still has a considerable optimization space after the global layout.
U.S. patent application publication No. US07072815B1 discloses a component relocation method after layout optimization, wherein the layout optimization method only considers the old and new positions of devices on a single timing critical path, and does not consider the influence of the new position of the device on other timing critical paths passing through the device, so that when selecting the new position of the device, timing analysis is required to detect whether the new position of the device will cause timing deterioration of other timing critical paths, thereby increasing the workload of timing analysis and reducing the operating efficiency, and in addition, when selecting the optimized position of the device, the selection error of the optimized position will also influence the effect achieved by the overall timing optimization.
Therefore, there is a need to provide a new layout optimization method to solve the above problems in the prior art.
Disclosure of Invention
The invention aims to provide a layout optimization method and a layout optimization system, which avoid the influence of position optimization on other time sequence key devices and improve the time sequence optimization effect.
To achieve the above object, the layout optimization method of the present invention includes the following steps:
s1: performing time sequence analysis on the circuit;
s2: extracting n time sequence key devices from m time sequence devices, and sequencing the time sequence key devices according to a time sequence margin, wherein m is a natural number greater than 1, and n is a natural number greater than 1;
s3: selecting one time sequence key device from n time sequence key devices, and calculating an offset value of the time sequence key device based on a path where the time sequence key device is located;
s4: when the deviation value is judged to be larger than a deviation threshold value, position optimization processing is carried out on the time sequence key device;
s5: and repeating the step S3 and the step S4, and sequentially selecting the time sequence key devices according to the sequence until the position optimization processing of all the time sequence key devices is completed.
The invention has the beneficial effects that: calculating the deviation value of the time sequence key devices, wherein the deviation value is larger than a deviation threshold value, and sequentially selecting the time sequence key devices according to the sequence to perform position optimization processing, so that the positions of all the time sequence key devices are optimized, the mutual influence among the time sequence key devices is avoided, the time delay of the time sequence key devices is reduced, and the time sequence optimization effect is improved.
Further preferably, in the step S4, when the deviation value is less than or equal to the deviation threshold value, the step S3 is executed to select the next timing critical device, which has the following advantages: and only the time sequence key device needing position optimization is optimized, so that the optimization efficiency is improved.
Preferably, m sequential devices are sorted according to the sequential margin, the first n sequential devices are taken as the sequential key devices, and n accounts for 0.5-1.5% of m.
Preferably, the deviation threshold is ten times the average length of all the sequential devices.
Preferably, the location optimization process includes:
s21: extracting a fan-in set of the time sequence key device, and calculating a minimum actual arrival time arc of the time sequence key device;
s22: extracting a fan-out set of the time sequence key device, and calculating a maximum required arrival time arc of the time sequence key device;
s23: calculating a time sequence optimal region and a frame of the time sequence optimal region of the time sequence key device according to the minimum actual arrival time arc and the maximum required arrival time arc;
s24: traversing in the frame, and selecting the optimal layout position of the time sequence key device;
s25: calculating the timing allowance of the timing critical device at the optimal layout position and the timing allowance of the original position;
s26: comparing the time sequence allowance of the optimal layout position with the time sequence allowance of the original position, and judging whether to restore the position of the time sequence key device, wherein the method has the advantages that: and calculating a time sequence optimal region of the time sequence key device and a frame of the time sequence optimal region according to the minimum actual arrival time arc and the maximum required arrival time arc, and selecting the optimal layout position of the time sequence key device in the frame without influencing other time sequence key devices and paths, so that the possibility of time sequence reduction is avoided, and the quality of time sequence optimization is improved.
Further preferably, in step S26, when the timing margin of the optimal layout position is smaller than the timing margin of the original position, the timing critical device is fixed at the optimal layout position.
Further preferably, in step S26, when the timing margin of the optimal layout position is greater than or equal to the timing margin of the original position, the timing critical device is restored to the original position.
Further preferably, the minimum actual arrival time arc is a set of first locations, the first locations being locations of the timing critical devices that minimize actual arrival time.
Further preferably, the maximum required arrival time arc is a set of second locations, the second locations being locations of the timing critical devices that maximize required arrival time.
Further preferably, the timing optimization region is a set of third locations, the third locations being locations of the timing critical devices that maximize the timing margin.
The invention also provides a layout optimization system for implementing the layout optimization method, the layout optimization system comprises a time sequence analysis module, a sorting module, a selection module, a calculation module, a judgment module and a processing module, wherein the time sequence analysis module is used for carrying out time sequence analysis on a circuit, the sorting module is used for sorting the time sequence key devices, the selection module is used for extracting a set of the time sequence key devices and the time sequence key devices, the calculation module is used for calculating the time sequence margin and the deviation, the judgment module is used for comparing the deviation with the deviation threshold value, and the processing module is used for carrying out the position optimization processing on the devices to be critical.
The layout optimization system has the beneficial effects that: the calculation module is used for calculating the time sequence allowance, the sequencing module is used for sequencing the time sequence key devices, the selection module is used for sequentially selecting the time sequence key devices, the calculation module is used for calculating the deviation value of the time sequence key devices, the judgment module is used for judging to perform position optimization processing on the time sequence key devices, the processing module is used for performing position optimization processing on the time sequence key devices, time sequence optimization can be performed on all the time sequence key devices, the position optimization is performed sequentially after sequencing, the mutual influence of the time sequence key devices is reduced, and the time sequence optimization quality is improved.
Drawings
FIG. 1 is a flow chart of a layout optimization method of the present invention;
FIG. 2 is a block diagram of the layout optimization system of the present invention;
FIG. 3 is a diagram of a minimum actual arrival time of some embodiments of the present invention;
FIG. 4a is a schematic diagram of a location of the time-optimized region according to some embodiments of the present invention;
FIG. 4b is another location diagram of the time-optimized region according to some embodiments of the present invention;
FIG. 5a is a schematic illustration of a position of a Manhattan arc in accordance with some embodiments of the present invention;
FIG. 5b is a schematic view of another position of a Manhattan arc in accordance with certain embodiments of the invention;
FIG. 5c is a schematic illustration of another position of a Manhattan arc in accordance with some embodiments of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and similar words are intended to mean that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.
To solve the problems in the prior art, an embodiment of the present invention provides a layout optimization method, and with reference to fig. 1, the layout optimization method includes:
s1: performing time sequence analysis on the circuit;
s2: extracting n time sequence key devices from m time sequence devices, and sequencing the time sequence key devices according to a time sequence margin, wherein m is a natural number greater than 1, and n is a natural number greater than 1;
s3: selecting one time sequence key device from n time sequence key devices, and calculating an offset value of the time sequence key device based on a path where the time sequence key device is located;
s4: when the deviation value is judged to be larger than a deviation threshold value, position optimization processing is carried out on the time sequence key device;
s5: and repeating the step S3 and the step S4, and sequentially selecting the time sequence key devices according to the sequence until the position optimization processing of all the time sequence key devices is completed.
In some preferred embodiments of the present invention, in step S2, n timing critical devices are extracted from m timing devices, and the timing critical devices are sorted from small to large according to a timing margin, where m is a natural number greater than 1, and n is a natural number greater than 1.
In some preferred embodiments of the present invention, in the step S5, the step S3 and the step S4 are repeatedly executed, and the timing critical devices are sequentially selected according to the sequence of the timing margins from small to large until the position optimization processing of all the timing critical devices is completed.
In some embodiments of the present invention, in the step S4, when the deviation value is less than or equal to the deviation threshold, the step S3 is executed to select the next timing critical device.
In some embodiments of the present invention, m of the sequential devices are sorted according to the timing margin, the first n of the sequential devices are the critical sequential devices, and n accounts for 0.5% to 1.5% of m. Preferably, m time sequence devices are sorted from small to large according to the time sequence margin, the first n time sequence devices are taken as the time sequence key devices, and n accounts for 1% of m.
In some embodiments of the invention, there are m of the sequential devices in the circuit.
In some embodiments of the invention, the deviation threshold is ten times the average length of all the sequential devices.
In some embodiments of the invention, the location optimization process comprises:
s21: extracting a fan-in set of the time sequence key device, and calculating a minimum actual arrival time arc of the time sequence key device;
s22: extracting a fan-out set of the time sequence key device, and calculating a maximum required arrival time arc of the time sequence key device;
s23: calculating a time sequence optimal region and a frame of the time sequence optimal region of the time sequence key device according to the minimum actual arrival time arc and the maximum required arrival time arc;
s24: traversing in the frame, and selecting the optimal layout position of the time sequence key device;
s25: calculating the timing allowance of the timing critical device at the optimal layout position and the timing allowance of the original position;
s26: and comparing the time sequence allowance of the optimal layout position with the time sequence allowance of the original position, and judging whether to restore the position of the time sequence key device.
In some embodiments of the invention, in step S26, when the timing margin of the optimal layout position is smaller than the timing margin of the original position, the timing critical device is fixed at the optimal layout position.
In some embodiments of the invention, in step S26, when the timing margin of the optimal layout position is greater than or equal to the timing margin of the original position, the timing critical device is restored to the original position.
In some embodiments of the invention, the minimum actual arrival time arc is a set of first locations that are the locations of the timing critical devices that minimize actual arrival time.
In some embodiments of the invention, the maximum required arrival time arc is a set of second locations that are locations of the timing critical devices that maximize required arrival time.
In some embodiments of the invention, the timing optimal region is a set of third locations, the third locations being locations of the timing critical devices that maximize the timing margin.
FIG. 2 is a block diagram of the layout optimization system according to some embodiments of the invention. Referring to fig. 2, the layout optimization system includes a timing analysis module 1, a sorting module 2, a selection module 3, a calculation module 4, a judgment module 5, and a processing module 6, where the timing analysis module 1 is configured to perform timing analysis on a circuit, the sorting module 2 is configured to sort the timing critical devices, the selection module 3 is configured to extract a set of the timing critical devices and the timing critical devices, the calculation module 4 is configured to calculate the timing margin and the deviation, the judgment module 5 is configured to compare the deviation with a deviation threshold, and the processing module 6 is configured to perform the position optimization on the device to be critical.
In some embodiments of the present invention, in the circuit, the device that transmits the signal to the timing critical device is a fan-in device of the timing critical device, and the device that receives the signal transmitted by the timing critical device is a fan-out device of the timing critical device.
In some embodiments of the invention, the offset value is a distance between a location of the timing critical device and a fan-in device and a fan-out device connection of the timing critical device on the path.
In some embodiments of the present invention, the calculating the deviation value comprises the following specific steps: sequentially calculating a Manhattan distance between a fan-in device of the time sequence key device and the time sequence key device, a Manhattan distance between the time sequence key device and a fan-out device of the time sequence key device, and a Manhattan distance between the fan-in device of the time sequence key device and the fan-out device of the time sequence key device; and obtaining the deviation value according to the Manhattan distance between the fan-in device of the time sequence key device and the time sequence key device, the Manhattan distance between the time sequence key device and the fan-out device of the time sequence key device, and the Manhattan distance between the fan-in device of the time sequence key device and the fan-out device of the time sequence key device.
In some embodiments of the invention, a manhattan distance between a fan-in device of the timing critical device and the timing critical device plus a manhattan distance between the timing critical device and a fan-out device of the timing critical device yields a first result; the first result is subtracted from a Manhattan distance between a fan-in device of the timing critical device and a fan-out device of the timing critical device to obtain the offset value.
In some embodiments of the invention, the formula for calculating the bias value is dev (s, v) + dist (v, t) -dist (s, t), where v is the timing critical device, s is the fan-in device of v, t is the fan-out device of v, dev (v) is the bias value of v, dist (s, v) is the manhattan distance between s and v, dist (v, t) is the manhattan distance between v and t, and dist (s, t) is the manhattan distance between s and t.
In some embodiments of the present invention, the specific step of calculating the actual arrival time of the timing critical device is: calculating the actual arrival time of a single fan-in node of the timing key device; calculating the Manhattan distance between the single fan-in node and the time sequence key device; revising the Manhattan distance between the single fan-in node and the time sequence key device to obtain a revised Manhattan distance; obtaining the actual arrival time of a single fan-in node according to the actual arrival time of the single fan-in node of the time sequence key device and the revised Manhattan distance; sequentially obtaining the actual arrival time of all the single fan-in nodes of the time sequence key device; and taking the maximum value of the actual arrival time of all the single fan-in nodes as the actual arrival time of the timing critical device.
In some embodiments of the invention, the minimum actual arrival time arc is defined as k (F), where F is a set of all fan-in nodes of the timing critical device, and F is defined as FiF, since the minimum actual arrival time arc is the set of first positionsiRepresenting the physical meaning of said first location, said minimum actual arc of arrival time being represented by a function k (f).
In some embodiments of the invention, the formula for calculating the actual arrival time of the timing critical device is AAT (v) max (AAT (F)i)+delay(FiV) }, in which Fi∈ F, when the layout result is analyzed in time sequence, a linear time delay model is adopted for the connection line, so the time delay of the signal passing through the time sequence key device is ignored, and the signal passing through the time sequence key is ignoredAssuming that the delay of the device is constant and does not affect the calculation and correlation analysis of the minimum actual arrival time arc, the formula AAT (v) max (AAT (F) } max is obtainedi)+τ×dist(Fi,v)},Fi∈ F, where v is the timing critical device, τ is a constant, FiIs a fan-in node of said v, said AAT (v) is the actual arrival time of said v, said AAT (F)i) For the fan-in time of v, the dist (F)iV) is said FiAnd the manhattan distance between said v.
Fig. 3 is a diagram of a minimum actual arrival time of some embodiments of the present invention. Referring to fig. 3, the timing critical device has two fan-in nodes, the two fan-in nodes are divided into a first fan-in node 31 and a second fan-in node 32, and the first fan-in node 31 is defined as F1The second fan-in node 32 is F2The signal reaches said F1Is AAT (F)1)，AAT(F1) 1, the signal reaches said F2Is AAT (F)2)，AAT(F2) 3, the connection delay corresponding to the distance between the first fan-in node 31 and the second fan-in node 32 is 6, the minimum actual arrival time arc is a line segment 33 forming 45 degrees with the horizontal line, the connection delay time of the signal from the first fan-in node 31 to the line segment 33 is 4, the connection delay time of the signal from the second fan-in node 32 to the line segment 33 is 2, and when the timing key device is at a certain position on the minimum actual arrival time arc, aat (v) is 5, and 5 is the minimum value.
In some embodiments of the invention, the step of calculating the new minimum actual arrival time arc is: sequentially traversing all fan-in nodes of the time sequence key device, and updating the minimum actual arrival time arc of the time sequence key device and the actual arrival time of the minimum actual arrival time arc of the time sequence key device when the signal arrives; initializing a first fan-in node of all the fan-in nodes, wherein the minimum actual arrival time arc is equal to the first fan-in node; the first fan-in node is excluded from all the fan-in nodes to obtain the remaining fan-in nodes; selecting a single residual fan-in node, calculating the distance between the single residual fan-in node and the minimum actual arrival time arc, and obtaining a first distance from the minimum actual arrival time arc to the new minimum actual arrival time arc and a second distance from the single residual fan-in node to the new minimum actual arrival time arc according to the revised distance, the revised actual arrival time and the revised actual arrival time of the single residual fan-in node; constructing a range graph according to the minimum actual arrival time arc and the single node to obtain a single minimum actual arrival time arc; and obtaining the single minimum actual arrival time arc obtained according to all the single residual nodes, and processing the single minimum actual arrival time arc to obtain the new minimum actual arrival time arc.
In some embodiments of the present invention, the specific step of calculating the new minimum actual arrival time arc is: sequentially traversing the set of all fan-in nodes, and updating the minimum actual arrival time arc and the actual arrival time of the signal reaching the position in the minimum actual arrival time arc, wherein the actual arrival time is AAT (K (F)); initializing the first node row in the set of all fan-in nodes, wherein the first node is F1Obtaining K (F) ═ F1Therefore, AAT (K (F)) ═ AAT (F)1) (ii) a Removing the first node from the set of all the fan-in nodes to obtain a residual fan-in node set, wherein the residual fan-in node set is FaAnd calculating the distance between the residual fan-in node set and the minimum actual arrival time arc, wherein the distance is d.
τ is a constant, when the product of τ and d is greater than the absolute value of the actual arrival time of the minimum actual arrival time arc minus the actual arrival time of the remaining fan-in node set, the actual arrival time of the minimum actual arrival time arc minus the actual arrival time of the remaining fan-in node set to obtain a third result, the product of τ and d is a fourth result, the third result is added with the fourth result to obtain a fifth result, the product of 2 and τ is a sixth result, the fifth result is divided by the sixth result to obtain a first distance, and the d subtracts the first distance to obtain a second distance;
when the product of τ and d is smaller than the absolute value of the actual arrival time of the minimum actual arrival time arc minus the actual arrival time of the remaining fan-in node set, and the actual arrival time of the minimum actual arrival time arc is greater than the actual arrival time of the remaining fan-in node set, the first distance is 0, the actual arrival time of the minimum actual arrival time arc minus the actual arrival time of the remaining fan-in node set obtains a seventh result, and the seventh result is divided by τ to obtain the second distance;
when the product of τ and d is smaller than the absolute value of the actual arrival time of the minimum actual arrival time arc minus the actual arrival time of the remaining fan-in node set, and the actual arrival time of the minimum actual arrival time arc is smaller than the actual arrival time of the remaining fan-in node set, the second distance is 0, the actual arrival time of the remaining fan-in node set minus the actual arrival time of the minimum actual arrival time arc obtains an eighth result, and the eighth result is divided by τ to obtain the first distance;
the first distance is d1The second distance is d2(ii) a Constructing a line segment on a line by taking the minimum actual arrival time arc as a center point of the opposite side, wherein the distance from the minimum actual arrival time arc is d1A first square inclined at an angle of 45 degrees to the horizontal, constructed with the set of remaining fan-in nodes as a center point, an angle at a distance d from the center point2And a second square at a 45 degree angle to the horizontal, wherein the overlapping portion of the first square and the second square is a manhattan arc, and the manhattan arc is the new minimum actual arrival time arc.
Fig. 5a is a schematic illustration of a position of a manhattan arc in accordance with some embodiments of the present invention. In the figure, the first square 51 and the second square 52 form an angle of 45 degrees with a horizontal line 59, a line segment 53 forms an angle of 45 degrees with the horizontal line, partial sides of the first square 51 and the second square 52 are overlapped, the line segment 53 in the first square 51 is the minimum actual arrival time arc, the right end point 54 of the minimum actual arrival time arc and the first square 52The first right corner 55 of the square 51 has a distance d1The black dot 56 in the second square is the remaining fan-in node set, and the distance between the black dot 56 and the second right end corner 57 of the second square 52 is d2The overlapping portion of the first square 51 and the second square 52 is the manhattan arc 58.
Fig. 5b is another schematic illustration of the position of the manhattan arc in accordance with some embodiments of the invention. In the figure, the second square 52 is at an angle of 45 degrees with the horizontal line 59, the line segment 53 is at an angle of 45 degrees with the horizontal line 59, the black point 56 in the second square 52 is the remaining fan-in node set, the line segment 53 cross-connected with the upper right of the second square 52 is the minimum actual arrival time arc, and the portion overlapping with the line segment 53 inside the second square 52 is the manhattan arc 58.
Fig. 5c is a schematic illustration of another position of the manhattan arc in accordance with some embodiments of the present invention. The first square 51 is shown at a 45 degree angle to the horizontal 59, the line segment 53 inside the first square 51 is the smallest actual arc of arrival time, the black point 56 inside the first square 51 is the set of remaining fan-in nodes, and the manhattan arc (not shown) coincides with the black point 54.
In some embodiments of the invention, the maximum required arrival time arc is defined as k (S), S ═ Si, the S being the set of all fan-out nodes of the timing critical device, the S being the set of the second locations because the maximum required arrival time arc is the set of the second locations, the SiRepresenting the physical meaning of said second location, said maximum required time of arrival arc being represented by a function k (f).
In some embodiments of the invention, the maximum required arrival time arc is physically shaped identically to the minimum actual arrival time arc.
In some embodiments of the invention, the step of calculating the required arrival time of the timing critical device is the same as the step of calculating the actual arrival time of the timing critical device, except that calculating the required arrival time is based on the set of fan-out nodes and taking the minimum value out of the results, calculating the actual arrival time of the timing critical device is based on the set of fan-in nodes and taking the maximum value out of the results.
In some embodiments of the invention, the formula for calculating the required arrival time of the timing critical device is RAT (v) min (RAT (S) { RAT (S) }i)+τ×dist(v,Si) Where v is the timing critical device, τ is a constant, and FiIs a fan-in node of said v, said SiIs one fan-out node of the v, the RAT (v) is the required arrival time of the v, the RAT (S)i) For the fan-out time of v, the dist (v, S)i) Is said v and said SiManhattan distance between.
In some embodiments of the invention, calculating a new maximum required arrival time arc is the same as calculating a new minimum actual arrival time arc except that the new minimum actual arrival time arc is calculated based on the set of fan-in nodes of the timing critical device and the new maximum required arrival time arc is calculated based on the set of fan-out nodes of the timing critical device.
In some embodiments of the present invention, the specific step of calculating the new maximum required arrival time arc is: sequentially traversing the set of all fan-out nodes, updating the maximum required arrival time arc and the required arrival time of a signal arriving at a position in the maximum required arrival time arc, wherein the required arrival time is RAT (K (S)); initializing a first node row in the set of all fan-out nodes, wherein the first node is S1RAT (k (S)) is RAT (S1) because k (S) is S1; removing the first node from the set of all fan-out nodes to obtain a residual fan-out node set, wherein the residual fan-out node set is SaCalculating the distance between the remaining fan-out node set and the maximum required arrival time arc, wherein the distance is e;
τ is a constant, and when the product of τ and e is greater than the required arrival time of the maximum required arrival time arc minus SaWhen the requirements ofIn absolute value of, the required arrival time of the maximum required arrival time arc minus SaObtaining a third result by the required time, wherein the product of tau and e is a fourth result, the third result is added with the fourth result to obtain a fifth result, the product of 2 and tau is a sixth result, the fifth result is divided by the sixth result to obtain a third distance, and the fourth distance is obtained by subtracting the third distance from e;
when the product of τ and e is smaller than the absolute value of the required reaching time of the maximum required reaching time arc minus the required reaching time of the remaining node set, and the required reaching time of the maximum required reaching time arc is greater than the required reaching time of the remaining node set, a third distance is 0, the required reaching time of the maximum required reaching time arc minus the required reaching time of the remaining node set to obtain a seventh result, and the seventh result is divided by τ to obtain the fourth distance;
when the product of τ and e is less than the absolute value of the required arrival time of the maximum required arrival time arc minus the required arrival time of the remaining node set, and the required arrival time of the maximum required arrival time arc is less than the required arrival time of the remaining node set, the fourth distance is 0, the required arrival time of the remaining node set minus the required arrival time of the maximum required arrival time arc to obtain an eighth result, and the eighth result is divided by τ to obtain the third distance;
the third distance is e1The fourth distance is e2(ii) a Constructing a time-of-arrival curve with the maximum required time of arrival as a centerline and a distance e from the centerline1Constructing a first square inclined at an angle of 45 degrees by taking the remaining fan-out node set as a central point and taking the distance from the central point as e2And a second square inclined at an angle of 45 degrees, wherein the overlapping part of the first square and the second square is a Manhattan arc, and the Manhattan arc is the new maximum required arrival time arc.
In some embodiments of the present invention, the specific step of calculating the timing margin is: calculating the required reaching time of the time sequence key device; calculating an actual arrival time of the timing critical device; and subtracting the actual arrival time of the time sequence key device from the required arrival time of the time sequence key device to obtain the time sequence margin.
In some embodiments of the invention, the timing optimum region of the timing critical device is defined as Z, the timing optimum region is a set of locations that maximizes a timing margin of the timing critical device, a timing margin calculation formula of the timing critical device is slack (v) -rat (v) -aat (v), the v is the timing critical device, the slack (v) is a timing margin of the v, the rat (v) is a required arrival time of the v, and the aat (v) is an actual arrival time of the v.
In some embodiments of the invention, when the timing critical device is located within the timing optimization region encompassed by the minimum actual arrival time arc and the maximum required arrival time arc, the sum of the manhattan distance between the timing critical device and the minimum actual arrival time arc plus the manhattan distance between the timing critical device and the maximum required arrival time arc is the smallest, while the timing margin is the largest.
Fig. 4a is a location diagram of the time optimal region according to some embodiments of the present invention. Referring to fig. 4a, the minimum actual arrival time arc 41 and the maximum required arrival time arc 42 are parallel to each other, the area enclosed by the minimum actual arrival time arc 41 and the maximum required arrival time arc 42 is the optimal timing area 43, and the dashed rectangle is the frame 44 of the optimal timing area.
Fig. 4b is another location diagram of the time optimal region according to some embodiments of the present invention. Referring to fig. 4b, the minimum actual arrival time arc 41 and the maximum required arrival time arc 42 are perpendicular to each other, the area enclosed by the minimum actual arrival time arc and the maximum required arrival time arc is the time sequence optimal area 43, and the dashed rectangle is the frame 44 of the time sequence optimal area.
In some embodiments of the present invention, the specific step of calculating the frame of the time sequence optimal region based on the minimum actual arrival time arc and the maximum required arrival time arc is: calculating a minimum distance between the minimum actual arrival time arc and the maximum required arrival time arc; removing a portion of the minimum required arrival time arc having a distance to the maximum required arrival time arc that is greater than the minimum distance, and removing a portion of the maximum required arrival time arc having a distance to the minimum required arrival time arc that is greater than the minimum distance; and calculating a frame surrounding the minimum actual arrival time arc and a frame surrounding the maximum required arrival time arc, namely the frame of the time sequence optimal area.
In some embodiments of the present invention, the specific step of selecting the new layout position of the timing critical device is: after the frame of the time sequence optimal area is calculated, traversing all positions in the frame of the time sequence optimal area; selecting a position which is not occupied by a device in a frame of the time sequence optimal area; selecting a position with the minimum sum of the distances between the minimum actual arrival time arc and the maximum required arrival time arc from the positions which are not occupied by the device; and selecting a position with the minimum distance from the position with the minimum distance to a frame formed by two starting and ending points of a path where the time sequence key device is located, wherein the position with the minimum distance is an optimal position, and the optimal position is used as a new layout position of the time sequence key device.
Although the embodiments of the present invention have been described in detail hereinabove, it is apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention as described herein is capable of other embodiments and of being practiced or of being carried out in various ways.
Claims (10)
1. A layout optimization method, comprising the steps of:
s1: performing time sequence analysis on the circuit;
s2: extracting n time sequence key devices from m time sequence devices, and sequencing the time sequence key devices according to a time sequence margin, wherein m is a natural number greater than 1, and n is a natural number greater than 1;
s3: selecting one time sequence key device from n time sequence key devices, and calculating an offset value of the time sequence key device based on a path where the time sequence key device is located;
s4: when the deviation value is judged to be larger than a deviation threshold value, position optimization processing is carried out on the time sequence key device;
s5: and repeating the step S3 and the step S4, and sequentially selecting the time sequence key devices according to the sequence until the position optimization processing of all the time sequence key devices is completed.
2. The layout optimization method of claim 1, wherein in step S4, when the deviation value is less than or equal to the deviation threshold, the step S3 is performed to select the next timing critical device.
3. The layout optimization method according to claim 1, wherein m sequential devices are sorted according to the sequential margin, the first n sequential devices are the sequential critical devices, and n accounts for 0.5% to 1.5% of m.
4. The layout optimization method according to claim 1, wherein the location optimization process includes:
s21: extracting a fan-in set of the time sequence key device, and calculating a minimum actual arrival time arc of the time sequence key device;
s22: extracting a fan-out set of the time sequence key device, and calculating a maximum required arrival time arc of the time sequence key device;
s23: calculating a time sequence optimal region and a frame of the time sequence optimal region of the time sequence key device according to the minimum actual arrival time arc and the maximum required arrival time arc;
s24: traversing in the frame, and selecting the optimal layout position of the time sequence key device;
s25: calculating the timing allowance of the timing critical device at the optimal layout position and the timing allowance of the original position;
s26: and comparing the time sequence allowance of the optimal layout position with the time sequence allowance of the original position, and judging whether to restore the position of the time sequence key device.
5. The layout optimization method of claim 4, wherein in step S26, when the timing margin of the optimal layout position is smaller than the timing margin of the original position, the timing critical device is fixed at the optimal layout position.
6. The layout optimization method according to claim 4, wherein in step S26, when the timing margin of the optimal layout position is greater than or equal to the timing margin of the original position, the timing critical device is restored to the original position.
7. The layout optimization method of claim 4, wherein the minimum actual arrival time arc is a set of first locations that are locations of the timing critical devices that minimize actual arrival time.
8. The layout optimization method of claim 4, wherein the maximum required arrival time arc is a set of second locations that are locations of the timing critical devices that maximize required arrival times.
9. The layout optimization method of claim 4, wherein the timing-optimal region is a set of third locations, the third locations being locations of the timing critical devices that maximize the timing margin.
10. A layout optimization system, configured to implement the layout optimization method according to any one of claims 1 to 9, where the layout optimization system includes a timing analysis module, a sorting module, a selection module, a calculation module, a judgment module, and a processing module, where the timing analysis module is configured to perform timing analysis on a circuit, the sorting module is configured to sort the timing critical devices, the selection module is configured to extract a set of the timing critical devices and the timing critical devices, the calculation module is configured to calculate the timing margin and the deviation, the judgment module is configured to compare the deviation with the deviation threshold, and the processing module is configured to perform the position optimization on the device to be critical.
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