CN111400079B - Isolator, and software resetting method, device and storage medium applicable to isolator - Google Patents
Isolator, and software resetting method, device and storage medium applicable to isolator Download PDFInfo
- Publication number
- CN111400079B CN111400079B CN202010181152.1A CN202010181152A CN111400079B CN 111400079 B CN111400079 B CN 111400079B CN 202010181152 A CN202010181152 A CN 202010181152A CN 111400079 B CN111400079 B CN 111400079B
- Authority
- CN
- China
- Prior art keywords
- module
- reset
- bus
- transmission
- instruction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 20
- 230000005540 biological transmission Effects 0.000 claims abstract description 140
- 238000001514 detection method Methods 0.000 claims description 21
- 238000005192 partition Methods 0.000 claims description 6
- 238000004590 computer program Methods 0.000 claims description 4
- 238000000638 solvent extraction Methods 0.000 claims description 2
- 238000004891 communication Methods 0.000 abstract description 7
- 238000010586 diagram Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 2
- 239000013307 optical fiber Substances 0.000 description 2
- 230000000644 propagated effect Effects 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The embodiment of the invention discloses an isolator, and a software resetting method, a device and a storage medium applicable to the isolator, wherein the isolator comprises the following components: the system comprises a gate control management module, a bus state judging module and a reset logic executing module; the bus state judging module is respectively connected with the gate control management module and the reset logic executing module; according to the technical scheme provided by the embodiment of the invention, when the reset logic executing module acquires the software reset instruction sent by the register, the bus state judging module detects the working state of the transmission bus, and when the transmission bus is idle, the gate control management module cuts off the data and/or command transmission of the transmission bus, so that the software reset logic is executed, the execution of the software reset instruction does not influence the transmission function of the transmission bus, the loss of the transmission data and/or command and the hanging death of each functional module in the chip are prevented, the communication fault of the chip caused by the hanging death of the functional module is avoided, and the system safety during the software reset is improved.
Description
Technical Field
Embodiments of the present invention relate to chip and bus technologies, and in particular, to an isolator, and a method, an apparatus, and a storage medium for resetting software thereof.
Background
With the continuous progress of technology, chip technology has been rapidly developed, and in order to ensure the normal operation of each functional module in a chip, a software reset function needs to be provided for each functional module, so as to ensure that each functional module can be reset when a fault or a communication error occurs.
In the existing software reset technology, a software reset signal is provided to a target module through a register, after the target module receives the reset signal, a reset operation is performed, but when each functional module in a chip performs software reset, the bus state of the module cannot be completely perceived, for example, as shown in fig. 1A, when the target module just receives a control instruction sent by a main module and does not complete corresponding instruction operation, the target module receives the software reset signal and performs the reset operation, although the reset of the target module is successful, the control instruction sent by the main module is lost, so that the instruction of the main module cannot be responded, the main module is suspended, and even the communication of the whole chip fails.
Disclosure of Invention
The embodiment of the invention provides an isolator, a software resetting method and device suitable for the isolator and a storage medium, and realizes the software resetting of a functional module in a chip.
In a first aspect, an embodiment of the present invention provides an isolator, including: the system comprises a gate control management module, a bus state judging module and a reset logic executing module; the bus state judging module is respectively connected with the gate control management module and the reset logic executing module;
the gate control management module is respectively connected with the target working module and the data sending module through a transmission bus and is used for cutting off data transmission and/or command transmission of the transmission bus when a control instruction sent by the bus state judging module is acquired; the data sending module transmits data and/or commands to the target working module through the transmission bus;
the bus state judging module is used for detecting the working state of the transmission bus, sending the control instruction to the gate control management module and sending a reset execution instruction to the reset logic execution module according to the working state of the transmission bus;
the reset logic executing module is connected with the register matched with the target working module and is used for acquiring a software reset instruction sent by the register, and executing the software reset instruction when acquiring the reset execution instruction sent by the bus state judging module so as to enable the target working module to execute software reset.
In a second aspect, an embodiment of the present invention provides a software reset method, including:
when a reset logic executing module acquires a software reset instruction sent by a register, a detection request is sent to a bus state judging module, so that the bus state judging module detects the working state of a transmission bus;
when the bus state judging module detects that the working state of the transmission bus is idle, a control instruction is sent to a gating management module, and a reset execution instruction is sent to the reset logic execution module;
the gate control management module cuts off data transmission and/or command transmission of the transmission bus according to the control instruction;
and the reset logic execution module executes the software reset instruction according to the reset execution instruction so as to enable the target working module matched with the register to execute software reset.
In a third aspect, an embodiment of the present invention provides a software reset apparatus, including:
the detection request sending module is integrated in the reset logic executing module and is used for sending a detection request to the bus state judging module when a software reset instruction sent by the register is acquired, so that the bus state judging module detects the working state of the transmission bus;
the working state detection module is integrated in the bus state judgment module and is used for sending a control instruction to the gating management module and sending a reset execution instruction to the reset logic execution module when the working state of the transmission bus is detected to be idle;
the transmission data partition module is integrated in the gate control management module and is used for partitioning data transmission and/or command transmission of the transmission bus according to the control instruction;
and the first software reset execution module is integrated in the reset logic execution module and is used for executing the software reset instruction according to the reset execution instruction so as to enable the target working module matched with the register to execute software reset.
In a fourth aspect, an embodiment of the present invention further provides a computer readable storage medium, where a computer program is stored, where the program when executed by a processor implements the software reset method according to any embodiment of the present invention.
According to the technical scheme provided by the embodiment of the invention, when the reset logic execution module acquires the software reset instruction sent by the register, the bus state judgment module detects the working state of the transmission bus, and when the transmission bus is idle, the gate control management module cuts off the data transmission of the transmission bus, and then the reset logic execution module executes the software reset logic, so that the execution of the software reset instruction does not influence the data and/or command transmission of the transmission bus, the loss of the transmission data and/or the transmission command is prevented, each functional module in the chip is hung up, the occurrence of chip communication faults caused by the hanging up of the functional module is avoided, the system stability of software reset is improved, meanwhile, the original software reset program in the chip is not influenced, no software program modification is needed, and the forward compatibility is high.
Drawings
FIG. 1A is a logic flow diagram of a software reset provided in the background of the invention;
FIG. 1B is a block diagram of an isolator according to a first embodiment of the present invention;
FIG. 1C is a logic flow diagram of a software reset according to a first embodiment of the present invention;
FIG. 1D is a logic flow diagram of a software reset and a hardware reset according to a first embodiment of the present invention;
FIG. 1E is a logic flow diagram of a software reset and a hardware reset according to a first embodiment of the present invention;
fig. 2 is a flowchart of a software reset method according to a second embodiment of the present invention;
fig. 3 is a block diagram of a software reset device according to a third embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
Example 1
Fig. 1B is a block diagram of an isolator according to a first embodiment of the present invention, where the isolator includes: the system comprises a gating management module 101, a bus state judging module 102 and a reset logic executing module 103; the bus state judging module 102 is respectively connected with the gating management module 101 and the reset logic executing module 103;
specifically, as shown in fig. 1C, the gate management module 101 is connected to the target working module and the data sending module through a transmission bus respectively, and is configured to block data transmission and/or command transmission of the transmission bus when a control instruction sent by the bus state judging module 102 is obtained; the data sending module transmits data and/or commands to the target working module through the transmission bus, and the target working module feeds back responses to the data sending module through the transmission bus according to the data and/or commands. The gating management module 101 is inserted into a transmission bus between the target working module and the data transmission module, and in a normal working state, the gating management module 101 is in a conducting state, so that normal data transmission and/or command transmission between the target working module and the data transmission module is ensured, and when the gating management module 101 acquires a control instruction sent by the bus state judgment module 102, the data transmission and/or command transmission of the transmission bus is blocked. In the embodiment of the invention, the types and functions of the target working module and the data sending module are not particularly limited, and the data type of the data transmitted between the data sending module and the target working module and the command type of the transmission command are not particularly limited.
Optionally, in an embodiment of the present invention, the transmission bus includes an AXI bus; AXI (Advanced eXtensible Interface) bus an on-chip bus with high performance, high bandwidth and low delay characteristics supports misaligned data transmission, and in burst transmission, only a first address is needed, so that timing convergence is easy to realize.
The bus state judging module 102 is configured to detect a working state of the transmission bus, and send the control instruction to the gating management module 101 and send a reset execution instruction to the reset logic executing module 103 according to the working state of the transmission bus. Specifically, when the reset logic executing module 103 obtains a software reset instruction sent by a register, a detection request is sent to the bus state judging module, and when the bus state judging module 102 receives the detection request, the working state of the transmission bus is detected; the bus state judging module 102 may detect the working state of the transmission bus through the gating management module 101, for example, when the gating management module 101 detects that a transmission command passes, the command counter is subjected to 1-increasing processing, and when it detects that a feedback response passes, the command counter is subjected to 1-decreasing processing; accordingly, when the command counter is 0, the working state of the transmission bus is idle, and when the command counter is not 0, the working state of the transmission bus is busy. When the bus state judging module 102 detects that the transmission bus is in a busy state, the bus state judging module 102 is in a waiting state until detecting that the transmission bus is in an idle state, the bus state judging module 102 sends a reset execution instruction to the reset logic executing module 103 to inform the reset logic executing module 103 that the transmission bus is in the idle state.
The reset logic executing module 103 is connected to a register matched with the target working module, and is configured to obtain a software reset instruction sent by the register, and execute the software reset instruction when obtaining a reset execution instruction sent by the bus state judging module 102, so that the target working module executes software reset.
Optionally, in this embodiment of the present invention, the reset logic executing module 103 is further configured to control the bus state judging module 102, the gating management module 101, and the reset logic executing module 103 to execute software reset when a reset execution instruction sent by the bus state judging module 102 is obtained. In order to ensure that the target working module is reset and simultaneously release the partition of the transmission bus, namely, ensure the data transmission between the data sending module and the target working module, the isolator is required to be reset, namely, the gate control management module 101, the bus state judging module 102 and the reset logic executing module 103 are required to be reset.
Optionally, in an embodiment of the present invention, the reset logic executing module 103 is connected to the target working module or is connected to the target working module through an or gate circuit. As shown in fig. 1C, if only a software reset function is provided in the chip, the reset logic execution module is directly connected to the target work module; as shown in fig. 1D, if a hardware reset function is provided in the chip, for example, the power management unit (Power Management Unit, PMU) provides a hardware reset instruction for resetting at power-up, then the software reset instruction and the hardware reset instruction are typically connected through an or gate circuit, that is, when any reset instruction is received, and the target working module performs a reset operation, then at this time, the reset logic executing module 103 is connected to the or gate circuit, so as to perform a reset operation on the target working module together with the PMU.
Optionally, the reset logic executing module 103 is further configured to send a detection request to the bus state judging module 102 when a software reset instruction sent by the register is obtained; correspondingly, the bus state judging module 102 is specifically configured to detect the working state of the transmission bus when the detection request sent by the reset logic executing module 103 is obtained.
Optionally, in an embodiment of the present invention, the transmission bus includes a command queue; the bus state judging module 102 is connected to the command queue of the transmission bus, and is specifically configured to detect a working state of the command queue of the transmission bus, send a control instruction to the gating management module 101 and send a reset execution instruction to the reset logic executing module 103 according to the working state of the command queue of the transmission bus. As shown in fig. 1E, the command queue of the transmission bus includes one or more instructions to be executed in the transmission bus, indicating that the transmission bus is in an idle state when the command queue is empty.
In particular, if the target working module is connected to a plurality of data sending modules, the isolator in the embodiment of the present invention may include a plurality of gating management modules 101, a bus state judging module 102, and a reset logic executing module 103; the number of the gating management modules 101 is the same as that of the data sending modules, and when the bus state judging module 102 detects that all the gating management modules 101 have no data transmission or all the command queues have no instructions to be executed, it is determined that all the transmission buses are in an idle state, and a reset execution instruction can be sent to the reset logic executing module 103, so that the target working module performs a reset operation.
According to the technical scheme provided by the embodiment of the invention, when the reset logic execution module acquires the software reset instruction sent by the register, the bus state judgment module detects the working state of the transmission bus, and when the transmission bus is idle, the gate control management module cuts off the data transmission of the transmission bus, and then the reset logic execution module executes the software reset logic, so that the execution of the software reset instruction does not influence the data and/or command transmission of the transmission bus, the loss of the transmission data and/or the transmission command is prevented, each functional module in the chip is hung up, the occurrence of chip communication faults caused by the hanging up of the functional module is avoided, the system stability of software reset is improved, meanwhile, the original software reset program in the chip is not influenced, no software program modification is needed, and the forward compatibility is high.
Example two
Fig. 2 is a flowchart of a software reset method provided in a second embodiment of the present invention, where the present embodiment is applicable to a case of performing software reset on a functional module in a chip, the method may be performed by an isolator in the embodiment of the present invention, and the isolator may be implemented by software and/or hardware and integrated in the chip, and the method in the embodiment of the present invention specifically includes the following steps:
and S210, when the reset logic executing module acquires a software reset instruction sent by the register, sending a detection request to the bus state judging module so that the bus state judging module detects the working state of the transmission bus.
And S220, when the bus state judging module detects that the working state of the transmission bus is idle, a control instruction is sent to the gating management module, and a reset execution instruction is sent to the reset logic execution module.
And S230, the gate control management module cuts off the data transmission of the transmission bus according to the control instruction.
S240, the reset logic execution module executes the software reset instruction according to the reset execution instruction so as to enable the target working module matched with the register to execute software reset.
Optionally, in an embodiment of the present invention, after the reset logic executing module executes the software reset instruction according to the reset executing instruction, so that the target working module matched with the register executes software reset, the method further includes: and the reset logic executing module controls the bus state judging module, the gate control management module and the reset logic executing module to execute software reset after delaying for a preset time according to the reset executing instruction. In order to ensure that the target working module is reset and simultaneously release the partition of the transmission bus, the preset time can be set to 0, namely, the isolator is reset while the target working module is reset; the preset time may be set to a time other than 0 (for example, 0.01 seconds), so that the partition of the transmission bus is released after the reset of the target working module is completed, and the situation that the reset of the target working module is slower and the partition of the transmission bus is released is avoided.
According to the technical scheme provided by the embodiment of the invention, when the reset logic execution module acquires the software reset instruction sent by the register, the bus state judgment module detects the working state of the transmission bus, and when the transmission bus is idle, the gate control management module cuts off the data transmission of the transmission bus, and then the reset logic execution module executes the software reset logic, so that the execution of the software reset instruction does not influence the data and/or command transmission of the transmission bus, the loss of the transmission data and/or the transmission command is prevented, each functional module in the chip is hung up, the occurrence of chip communication faults caused by the hanging up of the functional module is avoided, the system stability of software reset is improved, meanwhile, the original software reset program in the chip is not influenced, no software program modification is needed, and the forward compatibility is high.
Example III
Fig. 3 is a block diagram of a software reset device according to a third embodiment of the present invention, where the device specifically includes: the device comprises a detection request sending module 310, a working state detection module 320, a transmission data blocking module 330 and a first software reset execution module 340.
The detection request sending module 310 is integrated in the reset logic executing module, and is configured to send a detection request to the bus state judging module when a software reset instruction sent by the register is acquired, so that the bus state judging module detects the working state of the transmission bus;
the working state detection module 320 is integrated in the bus state judging module, and is configured to send a control instruction to the gating management module and send a reset execution instruction to the reset logic execution module when detecting that the working state of the transmission bus is idle;
a transmission data blocking module 330, integrated in the gate control management module, configured to block data transmission and/or command transmission of the transmission bus according to the control instruction;
the first software reset execution module 340 is integrated in the reset logic execution module, and is configured to execute the software reset instruction according to the reset execution instruction, so that the target working module matched with the register executes software reset.
According to the technical scheme provided by the embodiment of the invention, when the reset logic execution module acquires the software reset instruction sent by the register, the bus state judgment module detects the working state of the transmission bus, and when the transmission bus is idle, the gate control management module cuts off the data transmission of the transmission bus, and then the reset logic execution module executes the software reset logic, so that the execution of the software reset instruction does not influence the data and/or command transmission of the transmission bus, the loss of the transmission data and/or the transmission command is prevented, each functional module in the chip is hung up, the occurrence of chip communication faults caused by the hanging up of the functional module is avoided, the system stability of software reset is improved, meanwhile, the original software reset program in the chip is not influenced, no software program modification is needed, and the forward compatibility is high.
Optionally, based on the above technical solution, the software reset device further includes:
and the second software reset execution module is integrated in the reset logic execution module and is used for controlling the bus state judgment module, the gate control management module and the reset logic execution module to execute software reset after delaying for a preset time according to the reset execution instruction.
The device can execute the software resetting method provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method. Technical details not described in detail in this embodiment may be found in the method provided by any embodiment of the present invention.
Example IV
A fourth embodiment of the present invention further provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements a software reset method according to any embodiment of the present invention, the method comprising:
when a reset logic executing module acquires a software reset instruction sent by a register, a detection request is sent to a bus state judging module, so that the bus state judging module detects the working state of a transmission bus;
when the bus state judging module detects that the working state of the transmission bus is idle, a control instruction is sent to a gating management module, and a reset execution instruction is sent to the reset logic execution module;
the gate control management module cuts off data transmission and/or command transmission of the transmission bus according to the control instruction;
and the reset logic execution module executes the software reset instruction according to the reset execution instruction so as to enable the target working module matched with the register to execute software reset.
The computer storage media of embodiments of the invention may take the form of any combination of one or more computer-readable media. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
The computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, either in baseband or as part of a carrier wave. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
Computer program code for carrying out operations of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, smalltalk, C ++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider).
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (10)
1. An isolator, comprising: the system comprises a gate control management module, a bus state judging module and a reset logic executing module; the bus state judging module is respectively connected with the gate control management module and the reset logic executing module;
the gate control management module is respectively connected with the target working module and the data sending module through a transmission bus and is used for cutting off data transmission and/or command transmission of the transmission bus when a control instruction sent by the bus state judging module is acquired; the data sending module transmits data and/or commands to the target working module through the transmission bus;
the bus state judging module is used for detecting the working state of the transmission bus, and sending the control instruction to the gate control management module and sending a reset execution instruction to the reset logic execution module when the working state of the transmission bus is idle;
the reset logic executing module is connected with the register matched with the target working module and is used for acquiring a software reset instruction sent by the register, and executing the software reset instruction when acquiring the reset execution instruction sent by the bus state judging module so as to enable the target working module to execute software reset.
2. The isolator of claim 1, wherein the reset logic execution module is further configured to control the bus state determination module, the gating management module, and the reset logic execution module to perform a software reset when a reset execution instruction sent by the bus state determination module is obtained.
3. The isolator of claim 1, wherein the transmission bus comprises a command queue; the bus state judging module is connected with the command queue of the transmission bus, and is specifically used for detecting the working state of the command queue of the transmission bus, and sending a control instruction to the gating management module and a reset execution instruction to the reset logic execution module when the working state of the command queue of the transmission bus is idle.
4. The isolator of claim 1, wherein the reset logic execution module is connected to the target working module or is connected to the target working module through an or gate.
5. The isolator of claim 1, wherein the reset logic execution module is further configured to send a detection request to the bus state determination module when a software reset instruction sent by the register is obtained;
correspondingly, the bus state judging module is specifically configured to detect the working state of the transmission bus when the detection request sent by the reset logic executing module is obtained.
6. The isolator of claim 1, wherein the transmission bus comprises an AXI bus.
7. A method for resetting software, comprising:
when a reset logic executing module acquires a software reset instruction sent by a register, a detection request is sent to a bus state judging module, so that the bus state judging module detects the working state of a transmission bus;
when the bus state judging module detects that the working state of the transmission bus is idle, a control instruction is sent to a gating management module, and a reset execution instruction is sent to the reset logic execution module;
the gate control management module cuts off data transmission and/or command transmission of the transmission bus according to the control instruction;
and the reset logic execution module executes the software reset instruction according to the reset execution instruction so as to enable the target working module matched with the register to execute software reset.
8. The method of claim 7, wherein after the reset logic execution module executes the software reset instruction according to the reset execution instruction to cause the target working module matched with the register to perform a software reset, comprising:
and the reset logic executing module controls the bus state judging module, the gate control management module and the reset logic executing module to execute software reset after delaying for a preset time according to the reset executing instruction.
9. A software reset device, comprising:
the detection request sending module is integrated in the reset logic executing module and is used for sending a detection request to the bus state judging module when a software reset instruction sent by the register is acquired, so that the bus state judging module detects the working state of the transmission bus;
the working state detection module is integrated in the bus state judgment module and is used for sending a control instruction to the gating management module and sending a reset execution instruction to the reset logic execution module when the working state of the transmission bus is detected to be idle;
the transmission data partition module is integrated in the gate control management module and is used for partitioning data transmission and/or command transmission of the transmission bus according to the control instruction;
and the first software reset execution module is integrated in the reset logic execution module and is used for executing the software reset instruction according to the reset execution instruction so as to enable the target working module matched with the register to execute software reset.
10. A computer readable storage medium, on which a computer program is stored, characterized in that the program, when being executed by a processor, implements a software reset method according to claim 7 or 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010181152.1A CN111400079B (en) | 2020-03-16 | 2020-03-16 | Isolator, and software resetting method, device and storage medium applicable to isolator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010181152.1A CN111400079B (en) | 2020-03-16 | 2020-03-16 | Isolator, and software resetting method, device and storage medium applicable to isolator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111400079A CN111400079A (en) | 2020-07-10 |
| CN111400079B true CN111400079B (en) | 2024-03-01 |
Family
ID=71430931
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010181152.1A Active CN111400079B (en) | 2020-03-16 | 2020-03-16 | Isolator, and software resetting method, device and storage medium applicable to isolator |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111400079B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003233634A (en) * | 2002-02-07 | 2003-08-22 | Sanyo Electric Co Ltd | Circuit function verification method and program |
| CN1549081A (en) * | 2003-05-21 | 2004-11-24 | 华为技术有限公司 | Resettnig method of bridging chip and apparatus thereof |
| CN1740998A (en) * | 2005-09-13 | 2006-03-01 | 中兴通讯股份有限公司 | Method for realizing to reset main device in 12C bus and resetting apparatus and equipment thereof |
| CN102662452A (en) * | 2012-03-30 | 2012-09-12 | 中兴通讯股份有限公司 | Method, device and system for controlling inter-integrated circuit (I2C) master device to reset |
| CN103064774A (en) * | 2013-01-16 | 2013-04-24 | 北京君正集成电路股份有限公司 | Bus monitoring method and device applied to embedded system |
| CN104461985A (en) * | 2014-12-31 | 2015-03-25 | 哈尔滨工业大学 | Master-slave synchronous serial communication bus based on node cascading and implementation method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6996750B2 (en) * | 2001-05-31 | 2006-02-07 | Stratus Technologies Bermuda Ltd. | Methods and apparatus for computer bus error termination |
-
2020
- 2020-03-16 CN CN202010181152.1A patent/CN111400079B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003233634A (en) * | 2002-02-07 | 2003-08-22 | Sanyo Electric Co Ltd | Circuit function verification method and program |
| CN1549081A (en) * | 2003-05-21 | 2004-11-24 | 华为技术有限公司 | Resettnig method of bridging chip and apparatus thereof |
| CN1740998A (en) * | 2005-09-13 | 2006-03-01 | 中兴通讯股份有限公司 | Method for realizing to reset main device in 12C bus and resetting apparatus and equipment thereof |
| CN102662452A (en) * | 2012-03-30 | 2012-09-12 | 中兴通讯股份有限公司 | Method, device and system for controlling inter-integrated circuit (I2C) master device to reset |
| CN103064774A (en) * | 2013-01-16 | 2013-04-24 | 北京君正集成电路股份有限公司 | Bus monitoring method and device applied to embedded system |
| CN104461985A (en) * | 2014-12-31 | 2015-03-25 | 哈尔滨工业大学 | Master-slave synchronous serial communication bus based on node cascading and implementation method thereof |
Non-Patent Citations (1)
| Title |
|---|
| 基于FPGA的简易MCU设计;雒雄;曹建;;现代电子技术(16);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111400079A (en) | 2020-07-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP2829986B1 (en) | Computer system, access method and apparatus for peripheral component interconnect express endpoint devices | |
| US9692846B2 (en) | System, device and method for providing push service using feedback message | |
| EP4152719A1 (en) | Scene pushing method, scene executing method, scene pushing device, scene executing device, terminal, server, and system | |
| WO2016107270A1 (en) | Device managing method, device and device managing controller | |
| CN112769652B (en) | Node service monitoring method, device, equipment and medium | |
| WO2020238747A1 (en) | Serial port output path switching method, system and apparatus, and switch | |
| US10970148B2 (en) | Method, device and computer program product for managing input/output stack | |
| KR20150001146A (en) | Storage system and Operating method thereof | |
| CN110881224B (en) | Network long connection method, device, equipment and storage medium | |
| CN111400079B (en) | Isolator, and software resetting method, device and storage medium applicable to isolator | |
| CN113382056A (en) | Data reporting method, device, equipment, storage medium and system | |
| US11431782B2 (en) | Method, apparatus, and device for transmitting file based on BMC, and medium | |
| CN108804152B (en) | Method and device for adjusting configuration parameters | |
| CN116192534A (en) | Train control data communication transmission method, device, equipment and storage medium | |
| US11314670B2 (en) | Method, apparatus, and device for transmitting file based on BMC, and medium | |
| US20150347347A1 (en) | Dynamic Data Collection Communication Between Adapter Functions | |
| US8370839B2 (en) | Monitoring message queues in message queuing information systems and initiating batch jobs to perform functions on the message queues | |
| US20160037285A1 (en) | Accessing serial console port of a wireless access point | |
| CN108090347B (en) | Data processing method and system | |
| CN114928540B (en) | Preemption method and device, electronic equipment and storage medium | |
| CN114567536B (en) | Abnormal data processing method, device, electronic equipment and storage medium | |
| CN116737445B (en) | Control method for realizing resource isolation by using pseudo container | |
| WO2021160043A1 (en) | Method and system for selecting reference signal for rlm, medium, and electronic device | |
| CN108334359B (en) | Server control method, system, equipment and computer storage medium | |
| US20130173814A1 (en) | Session establishing device, session establishing method, and recording medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Country or region after: China Address after: Room 802a, building 5, 3000 Longdong Avenue, Pudong New Area Free Trade Zone, Shanghai, 201203 Applicant after: Shanghai Jinzhuo Technology Co.,Ltd. Address before: Room 802a, building 5, 3000 Longdong Avenue, Pudong New Area Free Trade Zone, Shanghai, 201203 Applicant before: SHANGHAI KINDROID NETWORK TECHNOLOGY CO.,LTD. Country or region before: China |
|
| CB02 | Change of applicant information | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |