CN111384976A - Storage method and reading method of sparse check matrix - Google Patents
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Abstract
The embodiment of the invention is suitable for the technical field of coding and decoding, and provides a storage method and a reading method of a sparse check matrix, wherein the storage method comprises the following steps: acquiring a sparse check matrix used in the encoding and decoding process of the multi-system LDPC code; determining non-0 elements in the sparse check matrix, wherein any non-0 element has corresponding position information in the sparse check matrix, and the position information comprises a row sequence number and a column sequence number; for each row of the sparse check matrix, storing non-0 elements in each row, column sequence numbers of the non-0 elements, and row separators of each row line by line; storing, column by column, for each column of the sparse check matrix, a non-0 element in the each column, a row sequence number of the non-0 element, and a column separator of the each column. According to the embodiment, the indexing efficiency and the access speed of the sparse check matrix can be obviously improved on the premise of not obviously increasing the storage space.
Description
Technical Field
The invention belongs to the technical field of coding and decoding, and particularly relates to a storage method of a sparse check matrix, a storage device of the sparse check matrix, a reading method of the sparse check matrix, a reading device of the sparse check matrix, a decoder and a computer readable storage medium.
Background
Binary Low-Density-Parity-Check (B-LDPC) code is a packet error correcting code with sparse Check matrix, is suitable for almost all channels, can quickly approach the channel capacity of Shannon theory in the form of code length index, and is a research hotspot in recent years in the coding field. However, when the code length is relatively short, the performance of the B-LDPC code may be degraded to some extent. Therefore, researchers have proposed a multilevel LDPC (Non-binary low-Density-Parity-Check, NB-LDPC for short) code based on the B-LDPC code. Compared with the B-LDPC code, the NB-LDPC code has theoretically more excellent performance particularly when the code length is shorter, and at present, the NB-LDPC code is also gradually adopted as the coding standard by related industries. Such as the beidou satellite navigation system (BDS).
However, the application of NB-LDPC codes also brings with it more complex decoding algorithms. In general, the NB-LDPC decoding algorithm is an iterative algorithm based on belief propagation, and commonly includes a basic belief propagation algorithm (BP), a belief propagation algorithm based on fast fourier transform (FFT-BP), and an Extended Minimum Sum algorithm (EMS), among others.
Fig. 1 is a schematic flow chart of NB-LDPC iterative decoding algorithm in the prior art. The process comprises the following steps:
(1.1) initialization: initializing symbol confidence, setting maximum iteration times and the like;
(1.2) variable node update (also called horizontal update or backward update): updating the confidence coefficient of the current variable node by using the information of other variable nodes belonging to the same check node;
(1.3) updating the check nodes (also called vertical updating or forward updating), and updating the confidence coefficient of the current check node by using the information of other check nodes belonging to the same variable node;
(1.4) symbol decision: selecting the symbol with the maximum confidence coefficient to output;
(1.5) check calculation: and (4) checking the output symbol, if the output symbol passes the checking, decoding is successful, otherwise, repeating the steps (1.2) and (1.3), and continuing iteration until the iteration number exceeds the set maximum iteration number.
For NB-LDPC iterative decoding algorithms, variable node updates and check node updates require frequent access to the entire row and column of the sparse check matrix. The variable node updating needs to calculate the sparse check matrix column by column, and the check node updating needs to calculate the sparse check matrix row by row. In practice, however, for the sparse check matrix, in order to save its storage space, its non-0 elements and corresponding row and column serial numbers are generally stored in the order of rows or columns by using its sparse characteristic. As shown in fig. 2, the method is a schematic diagram of storing a sparse check matrix commonly used in the prior art, and the storage method is not at all favorable for fast indexing non-0 elements row by row and column by column of the sparse check matrix by the NB-LDPC iterative decoding algorithm. Therefore, in order to reduce the complexity of the NB-LDPC iterative decoding algorithm, it is necessary to optimize the storage and reading manner of the sparse check matrix.
Disclosure of Invention
In view of this, embodiments of the present invention provide a storage method and a reading method for a sparse check matrix, so as to solve the problem that a storage and reading method for the sparse check matrix is too complex when an NB-LDPC iterative decoding algorithm is used for encoding and decoding in the prior art.
A first aspect of an embodiment of the present invention provides a method for storing a sparse check matrix, including:
acquiring a sparse check matrix used in the encoding and decoding process of the multi-system LDPC code;
determining non-0 elements in the sparse check matrix, wherein any non-0 element has corresponding position information in the sparse check matrix, and the position information comprises a row sequence number and a column sequence number;
for each row of the sparse check matrix, storing non-0 elements in each row, column sequence numbers of the non-0 elements, and row separators of each row line by line;
storing, column by column, for each column of the sparse check matrix, a non-0 element in the each column, a row sequence number of the non-0 element, and a column separator of the each column.
A second aspect of the embodiments of the present invention provides a method for reading a sparse check matrix, including:
acquiring a sparse check matrix to be read;
reading non-0 elements in the sparse check matrix to be read row by row or column by column;
the sparse check matrix to be read is obtained by storing in the following way:
for each row of an original sparse check matrix, storing non-0 elements in each row, column sequence numbers of the non-0 elements and row separators of each row line by line;
storing, column by column, for each column of the original sparse check matrix, a non-0 element in the each column, a row sequence number of the non-0 element, and a column separator of the each column.
A third aspect of the embodiments of the present invention provides a storage apparatus for a sparse check matrix, including:
the acquisition module is used for acquiring a sparse check matrix used in the encoding and decoding process of the multi-system LDPC code;
a determining module, configured to determine non-0 elements in the sparse check matrix, where any non-0 element has corresponding location information in the sparse check matrix, and the location information includes a row sequence number and a column sequence number;
a row-by-row storage module, configured to store, for each row of the sparse check matrix, a non-0 element in each row, a column number of the non-0 element, and a row separator of each row, row by row;
a column-by-column storage module, configured to store, for each column of the sparse check matrix, a non-0 element in each column, a row sequence number of the non-0 element, and a column separator of each column, column by column.
A fourth aspect of the embodiments of the present invention provides a device for reading a sparse check matrix, including:
the acquisition module is used for acquiring a sparse check matrix to be read;
the reading module is used for reading non-0 elements in the sparse check matrix to be read row by row or column by column;
the sparse check matrix to be read is obtained by calling the following modules for storage:
a row-by-row storage module, configured to store, for each row of an original sparse check matrix, a non-0 element in each row, a column number of the non-0 element, and a row separator of each row, row by row;
a column-by-column storage module, configured to store, for each column of the original sparse check matrix, a non-0 element in each column, a row sequence number of the non-0 element, and a column separator of each column, column by column.
A fifth aspect of the embodiments of the present invention provides a decoder, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor implements the steps of the above method for storing a sparse check matrix when executing the computer program.
A sixth aspect of the embodiments of the present invention provides a decoder, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor implements the steps of the above method for reading a sparse check matrix when executing the computer program.
A seventh aspect of the embodiments of the present invention provides a computer-readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the steps of the above-mentioned storage method for a sparse check matrix are implemented.
An eighth aspect of the embodiments of the present invention provides a computer-readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the steps of the method for reading a sparse check matrix described above are implemented.
Compared with the background art, the embodiment of the invention has the following advantages:
according to the characteristic that the NB-LDPC iterative decoding algorithm accesses the sparse check matrix row by row or column by column, the sparse elements can be stored in a row and column mode at the same time, wherein the column serial number and the row separator of each row are stored in the row storage process, and the row serial number and the column separator of each column are stored in the column storage process.
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In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the embodiments or the description of the prior art will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
FIG. 1 is a schematic flow diagram of a prior art NB-LDPC iterative decoding algorithm;
FIG. 2 is a schematic diagram of a sparse check matrix storage as is common in the prior art;
FIG. 3 is a flowchart illustrating steps of a method for storing a sparse check matrix according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a sparse check matrix storage according to an embodiment of the present invention;
FIG. 5 is a flowchart illustrating steps of a method for reading a sparse check matrix according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a row-by-row reading process of a sparse check matrix according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a column-by-column read process of a sparse check matrix according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a sparse check matrix storage device according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of a sparse check matrix reading apparatus according to an embodiment of the present invention;
fig. 10 is a schematic diagram of a decoder according to an embodiment of the present invention.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
The technical solution of the present invention will be described below by way of specific examples.
Referring to fig. 3, a schematic flow chart illustrating steps of a method for storing a sparse check matrix according to an embodiment of the present invention is shown, which may specifically include the following steps:
s301, acquiring a sparse check matrix used in the encoding and decoding process of the multi-system LDPC code;
it should be noted that the method can be applied to the decoding process of the multilevel LDPC (NB-LDPC) code.
In a matrix, if the number of elements with a value of 0 is much larger than the number of elements other than 0, and the distribution of the elements other than 0 is irregular, the matrix is called a sparse matrix.
For example, if there are 20000 elements in a 200 × 100 matrix, most of the elements in the matrix are 0 elements, and only 400 non-0 elements, the matrix can be called sparse.
In the encoding and decoding process of the multi-system LDPC code, a check matrix is needed to verify the correctness of the received code word and correct the wrong received code word to a certain extent. In order to reduce the computational complexity of the checking process, the check matrix is typically designed to be sparse, i.e., a sparse check matrix.
In general, the sparse check matrix is known in advance and is invariant in the iterative process, which needs to be used repeatedly.
S302, determining non-0 elements in the sparse check matrix, wherein any non-0 element has corresponding position information in the sparse check matrix, and the position information comprises row sequence numbers and column sequence numbers;
in general, to save memory space, only the non-0 elements of the sparse matrix may be stored. If the storage is performed in this way, not only the value of the non-0 element, but also the row number and the column number corresponding to the element, that is, the position information of the non-0 element in the matrix, are stored.
Since the sparse check matrix is given in advance, the value of the non-0 element in the matrix, the row number, and the column number may also be determined in advance.
S303, storing non-0 elements in each row, column sequence numbers of the non-0 elements and row separators of each row line by line aiming at each row of the sparse check matrix;
in the embodiment of the present invention, each non-0 element in the sparse check matrix may be stored in a row-by-row and column-by-column manner. During storage, according to the difference between row storage and column storage, it is further necessary to store the column sequence number or row sequence number of each non-0 element, and the row separator of each row or column separator of each column, respectively.
In a specific implementation, for each row of the sparse check matrix, the non-0 elements in each row, the column numbers of the non-0 elements, and the row separators of each row may be sequentially stored in order. The line separator of each line may be the number of non-0 elements of each line, or the starting position or the ending position of the non-0 elements of each line.
S304, storing the non-0 element in each column, the row sequence number of the non-0 element and the column separator of each column by columns aiming at each column of the sparse check matrix.
Similarly, for each column of the sparse check matrix, the non-0 element in each column, the row sequence number of the non-0 element, and the column separator of each column may also be sequentially stored in order. The column separator of each column may be the number of non-0 elements of each column, or the starting position or the ending position of the non-0 elements of each column.
For example, for a simple matrix H of 3x3, if H is expressed as follows,
H＝[
2,0,3
0,1,0
1,0,3
]
then the column storage order may be represented as D ═ 2(1),1(3),1(2),3(1),3(3) ], where the number in the parenthesis is the row number corresponding to the non-0 element, and the column separator may be represented as S ═ 2,1,2], i.e., the number of non-0 elements per column.
Fig. 4 is a schematic diagram of a sparse check matrix storage according to an embodiment of the present invention. In fig. 4, non-0 elements of each row and their corresponding column numbers, and row separators of each row are stored in rows, respectively; and storing non-0 elements of each column, corresponding row serial numbers thereof and column separators of each column according to the columns.
In the embodiment of the invention, according to the characteristic that the NB-LDPC iterative decoding algorithm accesses the sparse check matrix row by row or column by column, the sparse elements can be stored in a row and column mode at the same time, wherein the column serial number and the row separator of each row are stored in the row storage process, and the row serial number and the column separator of each column are stored in the column storage process, so that the indexing efficiency and the access speed of the sparse check matrix can be obviously improved when the NB-LDPC iterative decoding algorithm is adopted on the premise of not obviously increasing the storage space.
Referring to fig. 5, a schematic flow chart illustrating steps of a method for reading a sparse check matrix according to an embodiment of the present invention is shown, which may specifically include the following steps:
s501, acquiring a sparse check matrix to be read;
in the embodiment of the present invention, the sparse check matrix to be read may be a stored sparse check matrix used to verify the correctness of the received codeword and correct the erroneous received codeword to a certain extent when an NB-LDPC iterative decoding algorithm is adopted.
The sparse check matrix to be read can be obtained by storing in the following way:
for each row of an original sparse check matrix, storing non-0 elements in each row, column sequence numbers of the non-0 elements and row separators of each row line by line;
storing, column by column, for each column of the original sparse check matrix, a non-0 element in the each column, a row sequence number of the non-0 element, and a column separator of the each column.
Since the storage manner of the non-0 element in the sparse check matrix in this embodiment is similar to that in the above embodiment, the relevant details may refer to the description of steps S301 to S304 in the above embodiment, and this embodiment is not described again.
S502, reading non-0 elements in the sparse check matrix to be read row by row or column by column;
in the embodiment of the present invention, the non-0 elements in the stored sparse check matrix may be read in a row-by-row or column-by-column manner.
In a specific implementation, for each row of the sparse check matrix to be read, the non-0 elements and the column sequence numbers of the non-0 elements in each row may be sequentially read, and when a row separator is read, the current row sequence number is incremented and shifted to the next row for reading.
Fig. 6 is a schematic diagram of a row-by-row reading process of a sparse check matrix according to an embodiment of the present invention. Referring to the reading mode shown in fig. 6, reading can be performed according to the following steps:
(1) sequentially reading the elements and the corresponding column sequence numbers;
(2) if the line separator is met, adding 1 to the line sequence number, and switching to the next line for reading;
(3) reading line by line until the last line is finished.
Of course, it is also possible to sequentially read the non-0 element and the row sequence number of the non-0 element in each column for each column of the sparse check matrix to be read, and when the column separator is read, increment the current column sequence number and shift to the next column for reading.
Fig. 7 is a schematic diagram of a column-by-column reading process of a sparse check matrix according to an embodiment of the present invention. Referring to the reading mode shown in fig. 7, the reading can be performed as follows:
(1) sequentially reading the elements and the corresponding line sequence numbers;
(2) if the column separator is met, adding 1 to the column serial number, and switching to the next column for reading;
(3) this is done column by column until the end of the last column.
In the embodiment of the invention, aiming at the condition that the sparse check matrix is rapidly indexed row by row and column by column, particularly the multi-system LDPC iterative decoding algorithm, the sparse check matrix is respectively stored according to the rows and the columns and is read according to the rows or the columns, so that the indexing efficiency and the access speed of the sparse check matrix can be obviously improved on the premise of not obviously increasing the storage space.
It should be noted that, the sequence numbers of the steps in the foregoing embodiments do not mean the execution sequence, and the execution sequence of each process should be determined by the function and the internal logic of the process, and should not constitute any limitation on the implementation process of the embodiments of the present invention.
Referring to fig. 8, a schematic diagram of a storage apparatus of a sparse check matrix according to an embodiment of the present invention is shown, which may specifically include the following modules:
an obtaining module 801, configured to obtain a sparse check matrix used in an encoding and decoding process of a multilevel LDPC code;
a determining module 802, configured to determine non-0 elements in the sparse check matrix, where any non-0 element has corresponding location information in the sparse check matrix, where the location information includes a row sequence number and a column sequence number;
a row-by-row storage module 803, configured to store, for each row of the sparse check matrix, a non-0 element in each row, a column number of the non-0 element, and a row separator of each row, row by row;
a column-by-column storage module 804, configured to store, for each column of the sparse check matrix, a non-0 element in each column, a row sequence number of the non-0 element, and a column separator of each column, column by column.
In the embodiment of the present invention, the row separator of each row may be the number of non-0 elements of each row, and the column separator of each column may be the number of non-0 elements of each column; alternatively, the row separator of each row may be a start position or an end position of the non-0 element of each row, and the column separator of each column may be a start position or an end position of the non-0 element of each column.
Referring to fig. 9, a schematic diagram of a reading apparatus for a sparse check matrix according to an embodiment of the present invention is shown, which may specifically include the following modules:
an obtaining module 901, configured to obtain a sparse check matrix to be read;
a reading module 902, configured to read, row by row or column by column, a non-0 element in the sparse check matrix to be read;
the sparse check matrix to be read is obtained by calling the following modules for storage:
a row-by-row storage module, configured to store, for each row of an original sparse check matrix, a non-0 element in each row, a column number of the non-0 element, and a row separator of each row, row by row;
a column-by-column storage module, configured to store, for each column of the original sparse check matrix, a non-0 element in each column, a row sequence number of the non-0 element, and a column separator of each column, column by column.
In this embodiment of the present invention, the reading module 902 may specifically include the following sub-modules:
a row-by-row reading module, configured to sequentially read, for each row of the to-be-read sparse check matrix, a non-0 element in each row and a column number of the non-0 element; when the line separator is read, the current line sequence number is incremented and the next line is shifted to read.
In this embodiment of the present invention, the reading module 902 may further include the following sub-modules:
a column-by-column reading module, configured to sequentially read, for each column of the to-be-read sparse check matrix, a non-0 element and a row sequence number of the non-0 element in each column; when a column separator is read, the current column sequence number is incremented and shifted to the next column for reading.
For the apparatus embodiment, since it is substantially similar to the method embodiment, it is described relatively simply, and reference may be made to the description of the method embodiment section for relevant points.
Referring to fig. 10, a schematic diagram of a decoder according to an embodiment of the present invention is shown. As shown in fig. 10, the decoder 1000 of the present embodiment includes: a processor 1010, a memory 1020, and a computer program 1021 stored in the memory 1020 and operable on the processor 1010. The processor 1010 implements the steps in the various embodiments of the storage method of the sparse check matrix or the reading method of the sparse check matrix when executing the computer program 1021, such as steps S301 to S304 shown in fig. 3 and steps S501 to S502 shown in fig. 5. Alternatively, the processor 1010, when executing the computer program 1021, implements the functions of the modules/units in the above-mentioned device embodiments, such as the functions of the modules 801 to 804 shown in fig. 8 and the functions of the modules 901 to 902 shown in fig. 9.
Illustratively, the computer program 1021 may be partitioned into one or more modules/units that are stored in the memory 1020 and executed by the processor 1010 to implement the present invention. The one or more modules/units may be a series of computer program instruction segments capable of performing specific functions, which may be used to describe the execution of the computer program 1021 in the decoder 1000. For example, the computer program 1021 may be divided into an acquisition module, a determination module, a row-by-row storage module, and a column-by-column storage module, and the specific functions of each module are as follows:
the acquisition module is used for acquiring a sparse check matrix used in the encoding and decoding process of the multi-system LDPC code;
a determining module, configured to determine non-0 elements in the sparse check matrix, where any non-0 element has corresponding location information in the sparse check matrix, and the location information includes a row sequence number and a column sequence number;
a row-by-row storage module, configured to store, for each row of the sparse check matrix, a non-0 element in each row, a column number of the non-0 element, and a row separator of each row, row by row;
a column-by-column storage module, configured to store, for each column of the sparse check matrix, a non-0 element in each column, a row sequence number of the non-0 element, and a column separator of each column, column by column.
Alternatively, the computer program 1021 may be divided into an acquisition module and a reading module, and the specific functions of each module are as follows:
the acquisition module is used for acquiring a sparse check matrix to be read;
the reading module is used for reading non-0 elements in the sparse check matrix to be read row by row or column by column;
the sparse check matrix to be read is obtained by calling the following modules for storage:
a row-by-row storage module, configured to store, for each row of an original sparse check matrix, a non-0 element in each row, a column number of the non-0 element, and a row separator of each row, row by row;
a column-by-column storage module, configured to store, for each column of the original sparse check matrix, a non-0 element in each column, a row sequence number of the non-0 element, and a column separator of each column, column by column.
The decoder 1000 may be a computing device such as a desktop computer, a notebook, a palm computer, a cloud server, a navigation module, a time service module, and the like. The decoder 1000 may include, but is not limited to, a processor 1010, a memory 1020. Those skilled in the art will appreciate that fig. 10 is merely an example of the decoder 1000, and does not constitute a limitation on the decoder 1000, and may include more or less components than those shown, or combine certain components, or different components, e.g., the decoder 1000 may also include input-output devices, network access devices, buses, etc.
The Processor 1010 may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, discrete hardware component, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The memory 1020 may be an internal storage unit of the decoder 1000, such as a hard disk or a memory of the decoder 1000. The memory 1020 may also be an external storage device of the decoder 1000, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and so on, provided on the decoder 1000. Further, the memory 1020 may also include both an internal storage unit and an external storage device of the decoder 1000. The memory 1020 is used for storing the computer program 1021 and other programs and data required by the decoder 1000. The memory 1020 may also be used to temporarily store data that has been output or is to be output.
It will be apparent to those skilled in the art that the foregoing division of the functional units and modules is merely illustrative for the convenience and simplicity of description. In practical applications, the above function allocation may be performed by different functional units or modules as needed, that is, the internal structure of the apparatus/terminal device is divided into different functional units or modules, so as to perform all or part of the above described functions. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present invention. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus/terminal device and method may be implemented in other ways. For example, the above-described embodiments of the apparatus/terminal device are merely illustrative, and for example, the division of the modules or units is only one logical division, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. On the other hand, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated modules/units, if implemented in the form of software functional units and sold or used as separate products, may be stored in a computer readable storage medium. Based on such understanding, all or part of the flow in the method according to the above embodiments may be implemented by a computer program, which may be stored in a computer readable storage medium and used by a processor to implement the steps of the above embodiments of the method. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer-readable storage medium may include: any entity or device capable of carrying the computer program code, recording medium, usb disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution medium, and the like. It should be noted that the computer readable storage medium may contain content that is subject to appropriate increase or decrease as required by legislation and patent practice in jurisdictions, for example, in some jurisdictions, computer readable storage media that does not include electrical carrier signals and telecommunications signals in accordance with legislation and patent practice.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same. Although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.
Claims (10)
1. A method for storing a sparse check matrix is characterized by comprising the following steps:
acquiring a sparse check matrix used in the encoding and decoding process of the multi-system LDPC code;
determining non-0 elements in the sparse check matrix, wherein any non-0 element has corresponding position information in the sparse check matrix, and the position information comprises a row sequence number and a column sequence number;
for each row of the sparse check matrix, storing non-0 elements in each row, column sequence numbers of the non-0 elements, and row separators of each row line by line;
storing, column by column, for each column of the sparse check matrix, a non-0 element in the each column, a row sequence number of the non-0 element, and a column separator of the each column.
2. The method of claim 1, wherein the row separator of each row is a number of the non-0 elements of each row, and the column separator of each column is a number of the non-0 elements of each column; alternatively, the first and second electrodes may be,
the row separator of each row is the starting position or the ending position of each row of non-0 elements, and the column separator of each column is the starting position or the ending position of each column of non-0 elements.
3. A method for reading a sparse check matrix is characterized by comprising the following steps:
acquiring a sparse check matrix to be read;
reading non-0 elements in the sparse check matrix to be read row by row or column by column;
the sparse check matrix to be read is obtained by storing in the following way:
for each row of an original sparse check matrix, storing non-0 elements in each row, column sequence numbers of the non-0 elements and row separators of each row line by line;
storing, column by column, for each column of the original sparse check matrix, a non-0 element in the each column, a row sequence number of the non-0 element, and a column separator of the each column.
4. The method according to claim 3, wherein the step of reading non-0 elements in the sparse check matrix to be read row by row or column by column comprises:
sequentially reading non-0 elements in each row and the column sequence numbers of the non-0 elements for each row of the sparse check matrix to be read;
when the line separator is read, the current line sequence number is incremented and the next line is shifted to read.
5. The method according to claim 3, wherein the step of reading non-0 elements in the sparse check matrix to be read row by row or column by column comprises:
sequentially reading non-0 elements and row sequence numbers of the non-0 elements in each column aiming at each column of the sparse check matrix to be read;
when a column separator is read, the current column sequence number is incremented and shifted to the next column for reading.
6. A sparse check matrix reading apparatus, comprising:
the acquisition module is used for acquiring a sparse check matrix to be read;
the reading module is used for reading non-0 elements in the sparse check matrix to be read row by row or column by column;
the sparse check matrix to be read is obtained by calling the following modules for storage:
a row-by-row storage module, configured to store, for each row of an original sparse check matrix, a non-0 element in each row, a column number of the non-0 element, and a row separator of each row, row by row;
a column-by-column storage module, configured to store, for each column of the original sparse check matrix, a non-0 element in each column, a row sequence number of the non-0 element, and a column separator of each column, column by column.
7. A decoder comprising a memory, a processor and a computer program stored in said memory and executable on said processor, characterized in that said processor, when executing said computer program, implements the steps of the method of storing a sparse check matrix according to any one of claims 1 to 2.
8. Decoder comprising a memory, a processor and a computer program stored in said memory and executable on said processor, characterized in that said processor, when executing said computer program, implements the steps of the method for reading a sparse check matrix according to any of claims 3 to 5.
9. A computer-readable storage medium, in which a computer program is stored, which, when being executed by a processor, carries out the steps of the method for storing a sparse check matrix according to any one of claims 1 to 2.
10. A computer-readable storage medium, in which a computer program is stored, which, when being executed by a processor, carries out the steps of the method for reading a sparse check matrix according to any one of claims 3 to 5.
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