CN111382327B - Character string matching device and method - Google Patents
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Abstract
The invention discloses a character string matching device and a method, which are realized by mutual cooperation of hardware and software, wherein the compiling and the configuration of a character string matching automaton are completed by a CPU of a system, and a core character string matching task of the system is completed by a hardware engine on an FPGA (field programmable gate array), so that the requirements of both state convergence and matching performance are met. The FPGA module comprises a matching engine unit, a storage block unit and a storage module controller unit; the user uploaded character string rules are compiled into an active state transition table and a sub-active state transition table through an AC algorithm and are respectively stored in a storage block unit of the FPGA module and an external storage module, and different state transition tables are inquired according to different active states of characters to realize quick matching of the character strings.
Description
Technical Field
The invention relates to the technical field of network message detection, in particular to a character string matching device and a character string matching method.
Background
The deep packet inspection technology is an important technology in high-speed network monitoring technology, is also a core technology of feature identification, and is widely applied to the fields of flow charging, application layer protocol identification, intrusion detection systems, network monitoring systems, computer evidence obtaining systems and the like. With the development and application of the internet, the current network also relies on the deep packet inspection technology to identify and inspect the key characters of the payload part of the packet.
The deep packet inspection technology mainly adopts the traditional high-efficiency character string matching algorithm such as AC algorithm, WM algorithm and SBOM algorithm. In deep packet inspection, a character string is first compiled into a finite state automaton FSM, and a state table of the FSM is configured in a memory. The matching process is driven based on accessing the automaton state table, and at least one table lookup is needed for each character of the processed message to obtain the state address to be accessed next time.
Two challenges are mainly faced in the current deep packet inspection technology development process: the first is the problem of complexity of matching time, along with the development of network application, the number of features to be detected is more and more, the complexity of the features is more and more, and the matching process is more and more complicated; the second challenge is the performance requirement, which has high requirements on the processing bandwidth capability and the wire speed processing capability of the message detection system with the explosive increase of the internet traffic. For the first challenge, the invention adopts an AC algorithm, and the AC algorithm has the advantages that the character matching is skillfully converted into state transition; the matching of the long character strings only needs to be traversed once, namely, the character strings can be matched only by running once in the AC algorithm automaton; in addition, the invention optimizes the AC algorithm state transition matrix, and separately stores and queries the active state table entry and the sub-active state table entry, thereby greatly improving the matching efficiency. For the second challenge, which depends on memory access performance, for a certain number of accesses, it is critical to increase the speed of each access. Because the hardware has high-speed parallel processing capability, the character string matching based on the hardware becomes a research hotspot of the network deep message detection technology in recent years. The most advantage of character matching based on hardware implementation is that high throughput matching performance can still be obtained under a large-scale state set, thereby greatly improving the performance of the overall matching process, and when software is implemented, the performance of the character matching is rapidly decreased along with the increase of the state set.
Disclosure of Invention
To achieve the above object: the device and the method have simple structure and can quickly realize character string matching.
The technical scheme adopted by the invention is as follows: a character string matching device and method are realized by mutual cooperation of hardware and software, the compiling and the configuration of a character string matching automaton are completed by a CPU of a system, and a core character string matching task of the system is completed by a hardware engine on an FPGA.
A character string matching apparatus characterized in that: the FPGA module comprises a matching engine unit, a storage block unit and a storage module controller unit;
the CPU module is used for realizing software functions, processing uploading and compiling of a character string rule and issuing of a state transition table and a key character position table, wherein the state transition table comprises an active state transition table and a secondary active state transition table;
the FPGA module is used for realizing a hardware function, the storage block unit is used for storing the active state transition table and the key character position table, the matching engine unit is used for processing a character string matching calculation process, and the storage module controller unit is used for reading and writing data of the storage module;
the matching engine units comprise message cache regions and result cache regions;
the storage module is used for storing the secondary active state transition table.
Further the FPGA module comprises 1 or more of the matching engine units.
Further, the memory module is a DDR, and the memory block unit is a RAM.
A character string matching method is characterized by comprising the following steps:
firstly, a CPU module compiles a character string rule uploaded by a user according to an AC algorithm to generate a state transition matrix and a state transition table;
secondly, defining the next state of state transition by the state transition table, calculating a state transition probability table according to the state transition table, extracting k states with the maximum access probability values as active state transition tables to be written into a storage block unit of the FPGA module, writing the rest state transition tables as secondary active state transition tables into the storage module, and simultaneously writing a key character position table of a character string rule into the storage block unit of the FPGA module;
thirdly, in the character string matching calculation process, the matching engine unit extracts the payload after the message is input and outputs the payload to a message cache region, and the payload is distributed after extraction; when distributing message payloads, numbering each message payload, and then outputting the message payloads to a matching module; the matching module enters a matching starting state when receiving a message starting signal in an initial state, searches a table for character-by-character matching, inquires the active state transfer table in a storage block unit of the FPGA module in an active state, inquires the sub-active state transfer table in the storage block module in a sub-active state, processes and outputs a matching result; and outputting the matching results to a result cache region after outputting the matching results, and sequentially outputting the matching results according to the numbers printed when the message payload is distributed.
The first step further includes performing a calculation of matrix multiplication on the state transition matrix for a plurality of times, and optimizing the state transition matrix and the state transition table.
The third step further comprises the step of defining a hit identifier, a rule type and a rule ID by the state transition table; after the result of inquiring the state transition table is returned, whether key characters are hit is indicated according to the hit identification, if the key characters are hit, the rule belongs to a fixed key character rule or a floating key character rule according to the rule type indication, and if the key characters are not hit, the processing is carried out and the matching is continued; if the fixed key character rule belongs to, inquiring the key character position table according to the rule ID, if the actual hit position is consistent with the key character position table, outputting a matching result, and if the actual hit position is inconsistent with the key character position table, continuing to match; if the matching result belongs to the floating key character rule, processing and outputting the matching result; and finishing the payload of the message, processing and outputting a matching result.
And in the matching starting state, judging whether the current state is an active state or not according to the current state ID, inquiring the active state transfer table if the current state is the active state, jumping back to the initial state if the current state is the secondary active state, outputting an address to a storage module controller unit, queuing and inquiring the secondary active state transfer table, suspending the operation of message payloads in the current sequence, storing the inquired character position pointer to the original position of a message payload RAM (random access memory), and starting the matching operation of the next sequence of message payloads.
And the third step further comprises the steps of preferentially processing and outputting a matching result after the result of inquiring the secondary active state transition table is returned, and then jumping to the starting matching state.
Further, the memory module is DDR, and the memory block unit is RAM
Has the advantages that:
1. the state transition matrix of the automaton is optimized, and the requirements of state set convergence and matching performance are met.
2. And based on an FPGA (field programmable gate array) architecture, independently storing the active state query table and the secondary active state query table in the AC algorithm automaton, wherein the active state is stored in an RAM (random access memory) inside the FPGA, and the secondary active state is stored in an external DDR (double data rate). The automaton features ensure that most of the query actions are completed inside the FPGA.
3. The FPGA parallel processing structure is utilized, and a plurality of hardware matching engines are matched and processed in parallel; in addition, the time difference between the DDR and the RAM is inquired in a single matching module, parallel processing of a plurality of messages is realized, and the flow processing is fully performed, so that efficient matching is achieved, and the matching performance is greatly improved.
Drawings
FIG. 1 is a structural diagram of a character string matching apparatus of the present invention;
FIG. 2 is a diagram of a string hardware matching engine of the present invention;
FIG. 3 is a flow chart of the message payload distribution process of the present invention;
FIG. 4 is a block diagram of a string matching module of the present invention;
FIG. 5 is a flow chart of string matching of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "comprises," "comprising," and any other variation thereof, in the description and claims of this invention, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The structure of the character string matching device is shown in figure 1, and the character string matching device comprises a CPU module, an FPGA module and a DDR, wherein the FPGA module comprises a matching engine unit, a storage block unit and a DDR controller unit.
And the CPU module is used for realizing the compiling and the configuration of the automaton, the issuing of the state transition table and the key character position table and the like. The method mainly compiles a character string rule input by a user into a state tree through an AC algorithm matched with multiple modes, generates a state transition table, and writes the result into an RAM and a DDR inside an FPGA module.
The matching engine unit is used for processing a character string matching calculation process, the storage block unit is an RAM in the FPGA module and is used for storing an active state transfer table and a key character position table in the state transfer table, and the DDR controller unit is used for controlling data reading and writing of DDR.
The DDR is used to store a secondary active state transition table in the state transition table.
The character string matching device adopts n hardware matching engines for parallel processing so as to improve the processing bandwidth capacity of the equipment and open up an independent message buffer zone and an independent result buffer zone for each engine. The character string matching is realized by looking up a table and matching characters one by one, the active state is realized by looking up an internal RAM of the FPGA module, and the secondary active state is realized by looking up an external DDR.
The character string matching method is realized by the following steps:
firstly, compiling a character string rule input by a user into a state tree through an AC algorithm matched with multiple modes, and obtaining a state transition table at the moment and storing the state transition table in a matrix mode. And further carrying out matrix multiplication calculation on the state transition matrix for multiple times, and optimizing the state transition matrix and the state transition table so as to reduce the access times and the size of the content space occupied by the state transition table.
And a second step of calculating a state transition probability table according to the state transition table after the steps are carried out. And extracting k states with the maximum access probability value, writing the k states into an internal RAM of the FPGA module, and simultaneously writing the rest state transition tables into the DDR. Each table entry definition of the state transition table comprises a next state, a hit identifier, a rule type and a rule ID, wherein the next state refers to a state of next jump of the state, the hit identifier indicates that the current hit state is hit or miss, the rule type indicates whether the corresponding rule is a fixed key character rule or a floating key character rule, and the rule ID refers to a number of the rule corresponding to the current state. The fixed key character rule refers to that a character string rule input by a user designates a specific position of a key character in a message payload, the floating key character rule does not designate the position of the key character in the message payload, and the CPU module extracts a key character hit position from the character string rule input by the user and writes the key character hit position into a position table in the FPGA to form a key character position table.
And thirdly, in the character string matching calculation process, when the matching engine unit receives a starting signal in the initial state, starting a matching state, searching a table for byte-by-byte matching, inquiring an active state transfer table in an internal RAM of the FPGA module in the active state, and inquiring a secondary active state transfer table in the DDR in the secondary active state. If the state ID is smaller than k, the current state is indicated to be an active state, the RAM access address is calculated according to the state ID and the characters, and the next automaton state is read from the corresponding RAM to serve as the current state. And if the state ID is larger than k, the current state is stored in the DDR, the DDR access address is calculated according to the current state ID and the characters, and the next state is read from the DDR to serve as the current state.
The first step and the second step are realized based on a CPU module, the third step is realized based on an FPGA module, the structure diagram of a character string matching engine unit is shown in figure 2, and the flow of character string matching calculation mainly comprises the steps of message payload extraction, message payload distribution, matching and matching result processing.
The matching process is described below using a single hardware matching engine as an example.
And extracting the payload after the message is input, outputting the payload to a message cache region, and distributing the extracted payload. In order to ensure the order preservation of the matching result, the payload distribution module marks the serial number for each message payload, wherein the serial number ranges from 0 to 127. The process flow of distributing message payload is shown in fig. 3, after the message payload is input, the payload distribution operation is started, whether a complete message payload exists in the FIFO, whether a usable serial number exists, whether a branch RAM has a free bank and whether a branch RAM address to be sent has been calculated are detected, if the conditions are met, the message payload is taken out, repackaged, a serial number and a pointer label are marked on each beat of the message payload, and according to the calculated branch RAM address, the message payload is output to the matching module and written into the message payload RAM storing the message payload. The payload distribution module has the main functions of marking a numbered label on the message payload, repackaging and uniformly distributing the message payload to the m matching modules according to the storage condition of the message payload RAM of the m subsequent matching modules. The message payload number calculation is to calculate the released available number according to the RAM read pointer of the matching module, determine the number of the current message payload, wherein the number is num, and the value range is 0-127; and the branch RAM address calculation is that according to the use condition of the message payload RAM storage space of the m matching branches, the RAM branch with the least use amount is used as an output branch, the initial address of a free RAM block is calculated, and when all RAM spaces are fully written, a busy identifier is given to wait for the RAM space to be released.
The structure of the matching module is shown in fig. 4, when the matching module has main functions, an active state transfer table in the RAM of the FPGA module is inquired, and character string matching is performed on message payloads by combining inquiry of a secondary active state transfer table in the DDR module. The matching module is provided with a message payload RAM for storing message payloads, an active state transfer table and a key character position table. Each message payload RAM is logically divided into 8 banks, the number of each bank is 0-7, the depth of each bank is 128, the next maximum message payload can be loaded, the distribution module stores the message payloads into the banks of the message payload RAMs, only one bank stores one message payload, the storage state of the message payload RAMs is recorded by using a state register, and the state register of the message payload RAMs is updated when the message payload RAMs store or release one message payload. And the state of the message payload RAM is immediately output to the distribution module for calculation by the distribution module.
When the matching operation is executed, the message payload in the sequence 1, namely the message payload stored in the bank firstly, is taken out from the message payload RAM, each character of the message payload is matched with the current state, the state ID value is judged firstly, if the state ID value is smaller than k, the state ID and the character are used as the address to inquire an active state transfer table in the FPGA module, if the state ID is larger than or equal to k, the state ID and the character are used as the address to be output to the DDR controller unit to be queued for DDR, if the state ID is larger than or equal to k, the state ID and the character are output to the DDR controller unit to be queued for DDR, and if the state ID is larger than or equal to k, the state ID and the character are output to the DDR controller unit to be queued for DDR, the operation of the bank message payload in the sequence 1 is paused, the inquired character position pointer is stored back to the original position of the message payload in the RAM, then the message, and storing the inquired character position pointer back to the original position of the message payload RAM, and performing the next sequential message payload operation, and so on. And when the DDR query result of the message payload is returned, suspending the current operation, performing sequential message matching processing corresponding to the DDR query result, and preferentially processing the message payload stored first.
The specific matching flow of the message payload is shown in fig. 5, which mainly describes the matching process of querying the active state table inside the FPGA. When a message payload starting signal is received in an initial state, matching is started; and in the matching process, each input character is inquired and matched one by one. Firstly, detecting whether a result of inquiring a secondary active state transfer table in the DDR corresponding to the bank currently is returned or not in an initial state; if the message returns, assigning the corresponding message payload and the address of the state of the corresponding bank, outputting a matching result, jumping to a matching starting state, and starting the matching of the next character; and if not, jumping to the next sequential message payload matching operation, and entering a matching starting state.
In the matching starting state, whether the current state is an active state is judged according to the current state ID, if the current state is the active state, an active state transfer table in the FPGA is inquired, if the current state is the secondary active state, the current state is jumped back to the initial state, the address is output to the DDR controller unit to be queued for inquiring the DDR, the message payload operation of the current sequence is suspended, the inquired character position pointer is stored back to the original position of the message payload RAM, and the next sequence of message payload matching operation is started. If the query result is that the key character is not hit and the next state is active state, jumping to the matching continuous state, ending the message payload or jumping back to the initial state if the key character is not hit and the next state is sub-active state.
In a matching starting state or a matching continuing state, whether key characters, rule types and rule IDs are hit or not can be known according to a query result, whether the key characters are hit or not is indicated according to a hit identifier, if the key characters are hit, the rule types indicate that the key characters belong to a fixed key character rule or a floating key character rule, if the fixed key character rules are hit, a hit position is calculated, a key character hit position table is queried through the rule IDs, whether the rule hit position is consistent with an actual hit position or not is compared, if the rule hit position is consistent with the actual hit position, namely the key character position is hit, the fixed key characters are hit, message payloads are released, an initial state is jumped back, if the rule hit position is inconsistent, the key character positions are not hit, the message payloads are not finished, the next state is an active state, the matching continuing state is jumped back, and if the; if the floating key character rule is hit, releasing the message payload and jumping back to the initial state; when the message payload is finished, outputting a matching result and jumping back to the initial state; when the missing key character message payload is not finished and the next state is an active state, entering a matching continuation state or staying in the matching continuation state to continue matching, and returning to the initial state if the message payload of the current beat is finished; and when the key character is missed and the next matching state is the secondary active state, jumping back to the initial state and outputting the state ID and the next character together as an address to the DDR controller unit to queue and inquire the DDR. In any state, when the message payload inquiry DDR result returns, the current matching operation is suspended, the initial state is returned, the sequential message matching result processing corresponding to the DDR inquiry result is continuously carried out, and the message payload stored firstly is processed preferentially. The matching process for querying the secondary active state table is similar to the matching process for querying the active state table, and will not be described repeatedly here.
And after the matching is finished, outputting the matching result to a result cache region, outputting the matching result of the message payloads according to the serial number sequence of the message payloads in a matching result processing module, and releasing the serial number of the message payloads after the result is output.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (7)
1. A character string matching method is realized by a character string matching device, and is characterized in that: the character string matching device comprises a CPU module, an FPGA module and a storage module, wherein the FPGA module comprises a matching engine unit, a storage block unit and a storage module controller unit;
the CPU module is used for realizing software functions, processing uploading and compiling of a character string rule and issuing of a state transition table and a key character position table, wherein the state transition table comprises an active state transition table and a secondary active state transition table;
the FPGA module is used for realizing a hardware function, the storage block unit is used for storing the active state transition table and the key character position table, the matching engine unit is used for processing a character string matching calculation process, and the storage module controller unit is used for controlling data reading and writing of the storage module;
the matching engine unit comprises a message cache region and a result cache region;
the storage module is used for storing the secondary active state transition table;
the character string matching method comprises the following steps:
firstly, a CPU module compiles a character string rule uploaded by a user according to an AC algorithm to generate a state transition matrix and a state transition table;
secondly, defining the next state of state transition by the state transition table, calculating a state transition probability table according to the state transition table, extracting k states with the maximum access probability values as active state transition tables to be written into a storage block unit of an FPGA module, writing the rest state transition tables as secondary active state transition tables into the storage module, and simultaneously writing a key character position table of a character string rule into the storage block unit of the FPGA module;
thirdly, in the character string matching calculation process, the matching engine unit extracts the payload after the message is input and outputs the payload to a message cache region, and the payload is distributed after extraction; when distributing message payloads, numbering each message payload, and then outputting the message payloads to a matching module; the matching module enters a matching starting state when receiving a message starting signal in an initial state, searches a table for character-by-character matching, inquires the active state transfer table in a storage block unit of the FPGA module in an active state, inquires the sub-active state transfer table in the storage block module in a sub-active state, processes and outputs a matching result; outputting the matching results to a result cache region after outputting the matching results, and sequentially outputting the matching results according to the numbers printed when the message payload is distributed;
the third step also includes that in the matching starting state, whether the current state is an active state is judged according to the current state ID, if the current state is the active state, the active state transfer table is inquired, if the current state is a secondary active state, the current state jumps back to the initial state, the address is output to the storage module controller unit to be queued for inquiring the secondary active state transfer table, the message payload operation of the current sequence is suspended, the inquired character position pointer is stored back to the original position of the message payload RAM, and the next sequence of message payload matching operation is started;
the message payload distribution processing flow comprises the following steps: after the message payload is input, payload distribution operation is started, whether a complete message payload exists in FIFO is detected, whether an available serial number exists in the FIFO, whether a branch RAM has an idle bank and whether a branch RAM address to be sent is calculated, if the conditions are met, the message payload is taken out and packaged again, serial numbers and pointer labels are marked on the message payload of each beat according to the calculated branch RAM address, and the message payload is output to a matching module and written into a message payload RAM for storing the message payload according to the calculated branch RAM address.
2. The character string matching method according to claim 1, wherein: the message payload number calculation is to calculate the released available number according to the RAM read pointer of the matching module, determine the number of the current message payload, the number is num, and the value range is 0-127; and the branch RAM address calculation is that according to the use condition of the message payload RAM storage space of the m matching branches, the RAM branch with the least use amount is used as an output branch, the initial address of a free RAM block is calculated, and when all RAM spaces are fully written, a busy identifier is given to wait for the RAM space to be released.
3. The character string matching method according to claim 1, wherein: the FPGA module comprises 1 or more matching engine units.
4. A character string matching method according to any one of claims 1 to 3, characterized in that: the memory module is a DDR, and the memory block unit is a RAM.
5. The character string matching method according to claim 1, wherein: the first step further includes performing a plurality of matrix multiplication calculations on the state transition matrix to optimize the state transition matrix and the state transition table.
6. The character string matching method according to claim 1, wherein: the third step further comprises the state transition table definition hit identifier, rule type and rule ID; after the result of inquiring the state transition table is returned, whether key characters are hit is indicated according to the hit identification, if the key characters are hit, the rule belongs to a fixed key character rule or a floating key character rule according to the rule type indication, and if the key characters are not hit, matching is continued; if the fixed key character rule belongs to, inquiring the key character position table according to the rule ID, if the actual hit position is consistent with the key character position table, processing and outputting a matching result, and if the actual hit position is inconsistent with the key character position table, continuing to match; if the matching result belongs to the floating key character rule, processing and outputting the matching result; and finishing the payload of the message, processing and outputting a matching result.
7. The character string matching method according to claim 6, wherein: and the third step also comprises the steps of preferentially processing and outputting a matching result after the result of inquiring the secondary active state transition table is returned, and then jumping to the starting matching state.
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| CN112784127B (en) * | 2021-03-12 | 2023-12-05 | 清华大学 | Multi-string pattern matching method, device, computer equipment and storage medium |
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| CN117493622B (en) * | 2023-12-28 | 2024-03-29 | 苏州元脑智能科技有限公司 | Method and device for inquiring character strings based on field programmable array device |
| CN117675417B (en) * | 2024-02-02 | 2024-04-16 | 中国电子信息产业集团有限公司第六研究所 | Quick text scanning method and device, electronic equipment and storage medium |
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