CN111370338A

CN111370338A - Packaging method

Info

Publication number: CN111370338A
Application number: CN201811605547.9A
Authority: CN
Inventors: 秦晓珊
Original assignee: China Core Integrated Circuit Ningbo Co Ltd
Current assignee: China Core Integrated Circuit Ningbo Co Ltd
Priority date: 2018-12-26
Filing date: 2018-12-26
Publication date: 2020-07-03
Anticipated expiration: 2038-12-26
Also published as: CN111370338B

Abstract

The invention provides a packaging method, which comprises the following steps: providing a plurality of chips, wherein an electric connection structure is formed in each chip, the front surface of each chip is exposed out of the surface of the electric connection structure, a plastic package layer is formed between every two adjacent chips, and the front surface of each chip and the surface of the plastic package layer are provided with a plurality of solder ball areas and passivation areas between every two adjacent solder ball areas; forming a rewiring layer electrically connected with the electric connection structure on the front surface of each chip, wherein each rewiring layer spans the solder ball area and a passivation area adjacent to the solder ball area; forming a solder ball electrically connected with the rewiring layer on the rewiring layer of the solder ball area; and carrying out selective spraying treatment, spraying slurry to the rewiring layer, the front surface of the chip and the surface of the plastic packaging layer in the passivation area, and carrying out curing treatment on the slurry in the passivation area to form a passivation layer in the passivation area. The passivation layer is formed by utilizing selective spraying treatment, so that damage caused by a passivation layer forming process is reduced, and the reliability of the formed packaging structure is improved.

Description

Packaging method

Technical Field

The invention relates to the technical field of semiconductor packaging, in particular to a packaging method.

Background

With the trend of very large scale integrated circuits, the feature size of the integrated circuits is continuously decreasing, and the requirements of people on the packaging technology of the integrated circuits are also increasing correspondingly. Conventional packaging technologies include Ball Grid Array (BGA), Chip Scale Package (CSP), Wafer Level Package (WLP), three-dimensional Package (3D), System In Package (SiP), and the like.

The formation of solder balls is one of the key techniques in the packaging process. The solder balls are electrically connected with the electric connection structure in the chip, and the positions and the number of the input/output pins of the packaging structure are rearranged by utilizing the solder balls, so that the packaging structure is conveniently and electrically connected with an external circuit or other devices.

The performance of the package structure formed by the prior art packaging method still needs to be improved.

Disclosure of Invention

The invention provides a packaging method, which improves the packaging effect and improves the reliability of the formed packaging structure.

To solve the above problems, the present invention provides a packaging method, comprising: providing a plurality of chips, wherein each chip is provided with a front surface and a back surface opposite to the front surface, an electric connection structure is formed in each chip, the front surface of each chip is exposed out of the surface of the electric connection structure, a plastic package layer is formed between every two adjacent chips, and the front surface of each chip and the surface of the plastic package layer are provided with a plurality of welding ball areas and passivation areas between every two adjacent welding ball areas; forming a rewiring layer electrically connected with the electric connection structure on the front surface of each chip, wherein each rewiring layer spans the solder ball area and a passivation area adjacent to the solder ball area; forming a solder ball electrically connected with the rewiring layer on the rewiring layer of the solder ball area; and carrying out selective spraying treatment, spraying slurry to the rewiring layer, the front surface of the chip and the surface of the plastic packaging layer in the passivation area, and carrying out curing treatment on the slurry in the passivation area to form a passivation layer in the passivation area.

Compared with the prior art, the technical scheme provided by the invention has the following advantages:

in the technical scheme of the packaging method provided by the invention, the front surface of the chip and the surface of the plastic packaging layer are provided with a plurality of welding ball areas and passivation areas between the adjacent welding ball areas; forming a rewiring layer electrically connected with the electric connection structure of the chip on the front surface of each chip, wherein each rewiring layer spans across the solder ball area and the passivation area adjacent to the solder ball area; forming a solder ball electrically connected with the rewiring layer on the rewiring layer of the solder ball area; and carrying out selective spraying treatment, spraying slurry to the rewiring layer, the front surface of the chip and the surface of the plastic packaging layer in the passivation area, and carrying out curing treatment on the slurry in the passivation area to form a passivation layer in the passivation area. According to the invention, the process step of forming the passivation layer does not need to carry out a developing process or an etching process, so that the structure positioned in the solder ball area is prevented from being damaged by the etching caused by the developing process or the etching process, and the rewiring layer or the solder ball in the solder ball area keeps high quality, for example, the electrical connection performance of the rewiring layer or the solder ball is not influenced by the process of forming the passivation layer. Therefore, the invention improves the packaging effect, improves the performance of the packaging structure formed by packaging, and improves the electrical property and the reliability of the packaging structure.

Optionally, a moving path of the nozzle when the nozzle moves over the passivation region for the previous time is different from a moving path of the nozzle when the nozzle moves over the same passivation region for the subsequent time. The thickness uniformity and the thickness distribution condition of the slurry sprayed by the spray heads in different moving paths are different, and the slurry above the same passivation region is sprayed by the spray heads in different moving paths, so that the thickness distribution condition of the film layer formed by spraying the slurry twice is compensated or offset mutually, the thickness uniformity of the finally formed passivation layer is further improved, the protection effect of the passivation layer on the rewiring layer and the chip is improved, and the reliability of the packaging structure formed by packaging is further improved.

Optionally, the vertical distance between the spray head and the surface of the rewiring layer is 5 mm-30 mm, the area of a spraying area of the spray head spraying the slurry in unit time is moderate within the range of the vertical distance, and the thickness of a film layer formed by spraying the slurry in the passivation area in unit time is moderate correspondingly, so that the film layer formed in unit time has good thickness uniformity, and the thickness uniformity of a finally formed passivation layer is further improved.

Drawings

FIGS. 1-4 are schematic cross-sectional views illustrating a fan-out wafer level packaging process;

fig. 5 to fig. 11 are schematic structural diagrams corresponding to steps of a packaging method according to an embodiment of the present invention;

fig. 12 to fig. 15 are schematic structural diagrams corresponding to steps of a packaging method according to another embodiment of the present invention;

fig. 16 to 19 are schematic structural diagrams corresponding to steps of a packaging method according to yet another embodiment of the present invention.

Detailed Description

As is known from the background art, the performance of the package structure manufactured by the conventional packaging method is to be improved.

Now, an analysis is performed in combination with a packaging method, the packaging method is taken as a fan-out wafer level packaging counterfeit, fig. 1 to 4 are schematic cross-sectional structure diagrams of a fan-out wafer level packaging process, and the packaging method includes the following steps:

referring to fig. 1, a substrate 10 is provided, a plurality of chips 20 are provided on the substrate 10, an electrical connection structure 30 is provided in each chip 20, a surface of each chip 20 is exposed out of a surface of the electrical connection structure 30, and a molding layer 40 is formed on the substrate 10 between adjacent chips 20; a Redistribution-Layer (RDL) 50 is formed on the surface of each chip 20 to contact the electrical connection structure 30.

Referring to fig. 2, an Under Ball Metallurgy (UBM) 60 is formed on the surface of the redistribution layer 50 by a sputtering process; a photoresist layer 70 is formed on the surface of the ubm layer 60, the surface of the molding layer 40 and the surface of the chip 20, and a plurality of openings 80 are formed in the photoresist layer 70 to expose a portion of the surface of the ubm layer 60.

Referring to fig. 3, a solder layer filling the opening 80 is formed by an electroplating process; removing the photoresist layer 70 (refer to fig. 2) and removing the under ball metal layer 60 exposed by the solder layer; the solder layer is subjected to reflow processing to form a plurality of solder balls 91.

Referring to fig. 4, after the solder balls 91 are formed, a passivation layer 92 is formed in a region other than the solder balls 91, and the passivation layer 92 is used to protect the redistribution layer 50 and the chip 20.

The performance of the packaging structure formed by the packaging method needs to be improved. The process step of forming the passivation layer 92 was analyzed to be one of the main reasons for the poor performance of the package structure. Generally, the passivation layer 92 is formed by the following two processes:

firstly, a deposition process is adopted to form a passivation film on the rewiring layer 50, the chip 20 and the solder balls 91; and etching to remove the passivation film on the solder ball 91 to form the passivation layer 92. Generally, a dry etching process is adopted to etch and remove the passivation film on the solder ball 91, and the dry etching process is prone to causing etching damage to the solder ball 91, so that the electrical connection performance of the solder ball 91 is poor, and the performance of the formed packaging structure is affected.

Secondly, a coating process is adopted to form a passivation film on the rewiring layer 50, the chip 20 and the solder balls 91; and performing exposure treatment and development treatment on the passivation film, and removing the passivation film on the solder ball 91 to form the passivation layer 92. During the developing process, since the developing solution is in contact with the solder balls 91, the solder balls 91 are susceptible to corrosion by the developing solution, resulting in deterioration of the electrical connection performance of the solder balls 91, thereby affecting the performance of the formed package structure.

In addition, in some schemes, the passivation layer 92 may be formed before the solder balls 91 are formed, and accordingly, the process step of forming the passivation layer 91 may damage the redistribution layer 50, adversely affect the electrical connection performance of the redistribution layer 50, and even damage the chip 20, thereby affecting the performance of the chip 20, and causing the performance of the package structure to be degraded.

In order to solve the above problems, the present invention provides a packaging method, in which a passivation layer is formed in a passivation region by using selective spraying, so as to effectively avoid process damage to a redistribution layer or other structures in a solder ball region caused by a process for forming the passivation layer, thereby improving the performance of a packaging structure formed by packaging and improving the reliability of the packaging structure.

Fig. 5 to 11 are schematic structural diagrams corresponding to steps of a packaging method according to an embodiment of the present invention.

Referring to fig. 5 and 6, fig. 5 is a schematic top view, fig. 6 is a schematic cross-sectional view cut along AA1 in fig. 5, providing a plurality of chips 101, where the chip 101 has a front surface and a back surface opposite to the front surface, an electrical connection structure 102 is formed in the chip 101, the front surface of the chip 101 is exposed out of the surface of the electrical connection structure 102, a molding layer 103 is formed between adjacent chips 101, and the front surface of the chip 101 and the surface of the molding layer 103 have a plurality of solder ball regions I and passivation regions II between adjacent solder ball regions I.

The solder ball region I is indicated by a dashed box in fig. 5, and the chip 101 and the molding layer 103 are not shown in fig. 5 for convenience of illustration and explanation.

In this embodiment, the packaging method is applied to a wafer level package as an example, wherein the wafer level package is a fan-out wafer level package. It should be noted that, in other embodiments, the packaging method may also be applied to a wafer level system package, a system level package, or a 3D package.

The packaging method further includes providing a substrate 100, and the chip 101 and the molding layer 103 are located on the substrate 100. The substrate 100 is used to provide a bearing support effect for the chip 101, so as to improve the operability of the packaging process. In this embodiment, the substrate 100 is a metal substrate. In other embodiments, the substrate may also be a glass substrate, a ceramic substrate, a plastic substrate, or a resin substrate, and the substrate may also be a wafer.

The substrate 100 has a bonding surface, which is a surface on which the chip 101 is placed. In this embodiment, the bonding surface has a circular shape. In other embodiments, the shape of the bonding surface may also be a regular polygon, such as a rectangle, a hexagon, or an octagon, and the shape of the bonding surface may also be an irregular shape.

In other embodiments, the substrate may also be a circuit board, and the circuit board is electrically connected to the chip. The circuit board includes, but is not limited to, a PCB (printed circuit board), an FPC (flexible circuit board), or an RFPC (front-flex printed circuit board).

The chip 101 is used as a chip to be packaged and integrated in a fan-out wafer level package. The chip 101 may be one or more of an active element, a passive element, a micro electro mechanical system, an optical element, and the like. Specifically, the chip 101 may be a memory chip, a communication chip, a processing chip, a flash memory chip, a logic chip, or a specific function chip, for example, the processing chip may be an image sensor chip, a temperature sensor chip, or a pressure sensor chip, and the specific function chip is a chip developed for some specific functions, such as a Wifi chip, a bluetooth chip, or a power management chip.

In this embodiment, the plurality of chips 101 have the same function type, and the fan-out wafer level package is used to package chips having the same function type, and after a subsequent dicing process, a package structure having one chip is formed. Accordingly, the chips may be obtained by dicing the same wafer.

It should be noted that, in other embodiments, the functional types of the plurality of chips may not be different according to actual production process requirements, for example, the plurality of chips includes a first chip of a first functional type and a second chip of a second disclosed type, and the fan-out wafer level package is used to package the first chip and the second chip of different functional types in a package structure in combination. Accordingly, the plurality of chips may be obtained by cutting a plurality of wafers having different function types, respectively.

The electrical connection structure 102 is used for electrically connecting with a redistribution layer formed later, so as to electrically connect the chip 101 with an external circuit or other devices. The electrical connection structure 102 includes a metal interconnection structure and a pad electrically connected to the metal interconnection structure, wherein the surface of the chip 101 is exposed out of the pad. In this embodiment, the top of the pad is flush with the surface of the chip 101. In other embodiments, the bonding pad may protrude from the chip surface.

In this embodiment, the surface of the chip 101 exposed by the electrical connection structure 102 is the front surface of the chip 101.

The chip 101 may be fabricated using integrated circuit fabrication techniques. In this embodiment, the chip 101 is a chip made of a silicon wafer. In other embodiments, the chip 101 may be a chip formed by other materials, such as a germanium wafer, a silicon carbide wafer, a III-V compound wafer, a silicon on insulator wafer, or a sapphire substrate, wherein the III-V compound wafer may be a gallium arsenide wafer, an indium phosphide wafer, a gallium phosphide wafer, an indium gallium arsenide wafer, or an indium gallium phosphide wafer.

In this embodiment, the chip 101 is disposed on the substrate 100, and the front surface of the chip 101 faces upward relative to the back surface. In this embodiment, the plurality of chips 101 are temporarily bonded (temporarily bonding) to the substrate 100, and before or after a redistribution layer is formed subsequently, a debonding (bonding) process is performed to remove the substrate 100.

The molding layer 103 is used to provide physical protection to the chip 101, for example, to provide a supporting function to the chip 101, isolate external moisture or corrosive environment, and prevent the chip 101 from being corroded. In this embodiment, the plastic package layer 103 is made of epoxy resin.

The molding layer 103 is formed using an injection molding process (injection molding) or a transfer molding process (transfer molding). In this embodiment, the top of the molding layer 103 is flush with the front surface of the chip 101. In other embodiments, the top of the molding layer may be higher than the front surface of the chip, or the top of the molding layer may be lower than the front surface of the chip.

The solder ball area I is an area where solder balls are to be formed subsequently, each solder ball is electrically connected to the chip 101, and the solder ball is used as an input/output pin of the package structure. Through right the arrangement of a plurality of solder ball district I's position realizes right the rearrangement of chip 101's input/output pin position for packaging structure's input/output pin satisfies the requirement to solder ball minimum spacing, and will input/output pin arranges to new, the more loose region of pitch occupy-place, is convenient for form the packaging structure who has different solder ball spacings, and makes packaging structure's input/output pin arrange according to the array.

The passivation region II is a region where a passivation layer is to be formed later, and the passivation layer provides a protective effect for the chip 101 and a rewiring layer formed later.

In this embodiment, the shape of the solder ball region I is circular in a direction parallel to the front surface of the chip 101. In other embodiments, the shape of the solder ball region in a direction parallel to the front surface of the chip may also be a regular polygon, such as a quadrangle, a hexagon or an octagon, and the shape of the solder ball region may also be an irregular shape.

The plurality of solder ball areas I are distributed in an array mode along the X direction and the Y direction, wherein the X direction is the row direction of the array, and the Y direction is the column direction of the array.

Referring to fig. 7, a redistribution layer 104 electrically connected to the electrical connection structure 102 is formed on the front surface of each chip 101, and each redistribution layer 104 spans the solder ball region I and a passivation region II adjacent to the solder ball region I.

The re-routing layer 104 electrically connects the subsequently formed solder balls to the electrical connection structure 102, so as to re-arrange the input/output pins of the chip 101, and arrange the input/output pins to a new area with looser pitch occupation, thereby facilitating the formation of package structures with different solder ball pitches. The electrical connection structure 102 exposed from the front surface of the chip 101 is an input/output pin of the chip 101.

The redistribution layer 104 is made of one or more of copper, aluminum, tungsten, nickel, or gold. In this embodiment, the redistribution layer 104 is made of copper.

In this embodiment, in order to further increase the distance between the solder balls formed subsequently, the redistribution layer 104 is also located on the surface of the molding layer 103 adjacent to the chip 101.

In order to improve adhesion between the redistribution layer 104 and the chip 101 and reduce stress between the redistribution layer 104 and the chip 101, a buffer layer may be further formed between the redistribution layer 104 and the chip 101. The buffer layer is made of Polyimide (PI), Polybenzoxazole (PBO) or Benzocyclobutene (BCB).

After the rewiring layer 104 is formed, a debonding process is performed to remove the substrate 100. In other embodiments, before the redistribution layer is formed, a debonding process may be performed to remove the substrate. It should be noted that, in other embodiments, when the chip is disposed on the substrate and the back surface of the chip faces upward relative to the front surface, the substrate is removed to expose the front surface of the chip before a redistribution layer is formed subsequently.

It should be further noted that, in other embodiments, when the packaging method is applied to a fan-in wafer level package, the substrate is a wafer, the chips are manufactured on the wafer by using an integrated circuit process, and the front side of the chip faces upward relative to the back side, and accordingly, the substrate does not need to be removed before the redistribution layer is formed. When the packaging method is applied to packaging of a wafer-level system, the substrate is a device wafer, an internal chip is formed in the device wafer, the packaging method is used for packaging the internal chip and the chip in a packaging structure, the front side of the chip faces upwards relative to the back side of the chip, and correspondingly, the substrate does not need to be removed before the rewiring layer is formed. When the packaging method is applied to system-in-package, the substrate is a circuit board electrically connected with a chip, the front side of the chip faces upwards relative to the back side of the chip, and correspondingly, the substrate does not need to be removed before a rewiring layer is formed. When the packaging method is applied to 3D packaging, the substrate is a circuit board electrically connected with a chip, and correspondingly, the substrate does not need to be removed before the rewiring layer is formed.

Subsequent process steps include forming solder balls electrically connected to the redistribution layer 104 on the redistribution layer 104 in the solder ball area I; and performing selective spraying treatment, spraying slurry to the rewiring layer 104, the front surface of the chip 101 and the surface of the plastic packaging layer 102 in the passivation area II, and curing the slurry in the passivation area II to form a passivation layer in the passivation area II.

Wherein the process of forming the solder balls comprises: forming a solder layer electrically connected to the rewiring layer 104 on the rewiring layer 104 of the solder ball area I; and carrying out reflow treatment on the solder layer to form the solder ball. In this embodiment, the passivation layer is formed after the solder layer is formed and before the reflow process is performed. The following description will be made with reference to the accompanying drawings.

Referring to fig. 8, a solder layer 105 electrically connected to the redistribution layer 104 is formed on the redistribution layer 104 in the solder ball region I.

In this embodiment, an ubm layer 106 is further formed between the solder layer 105 and the redistribution layer 104.

The ubm layer 106 is beneficial to improving the adhesion between the redistribution layer 104 and the solder balls formed subsequently, and the ubm layer 106 can also play a role of diffusion barrier, so as to prevent metal ions in the solder balls formed subsequently from diffusing into the redistribution layer 104, thereby avoiding the problem of resistance increase of the redistribution layer 104 caused by the metal ions.

In this embodiment, the ubm layer 106 is not only located on the surface of the redistribution layer 104, but also located on the surface of the plastic package layer 103, the ubm layer 106 is a continuous film layer, and the ubm layer 106 is etched in the subsequent process steps to remove the ubm layer 106 not covered by the solder layer 105. In this embodiment, the ubm layer 107 has a laminated structure, and includes a chromium layer, a chromium-copper alloy layer located on a surface of the chromium layer, and a copper layer located on a surface of the chromium-copper alloy layer.

Specifically, an under-ball metal layer 106 is formed on the surface of the redistribution layer 104 in the solder ball region I and the passivation region I; the solder ball layer 105 is formed on the surface of the under-ball metal layer 106 of the solder ball region I.

In this embodiment, the process of forming the solder layer 105 includes: forming a photoresist layer on the surface of the under ball metal layer 106, wherein the photoresist layer has an opening located above the solder ball region I, and the under ball metal layer 106 of the solder ball region I is exposed at the bottom of the opening; forming a solder layer 105 filling the opening by using an electroplating process; after the solder layer 105 is formed, the photoresist layer is removed.

The material of the solder layer 105 includes tin, and may also include one or more of lead, antimony, zinc, copper, aluminum, iron, gold, silver, nickel, or bismuth.

In other embodiments, when the ubm layer is not formed, the solder layer is correspondingly formed on the surface of the redistribution layer in the solder ball region.

Referring to fig. 9, the ubm layer 106 not covered by the solder layer 105 is removed.

Specifically, the ubm layer 106 in the passivation region II is removed, and the redistribution layer 104, the chip 101, and the molding layer 103 in the passivation region II are exposed.

In this embodiment, the under-ball metal layer 106 in the passivation region II is removed by etching using a wet etching process. In other embodiments, a dry etching process may be further used to etch and remove the ubm layer in the passivation region.

With reference to fig. 5 and 10, after the ubm layer 106 not covered by the solder layer 105 is removed, a selective spraying process is performed, slurry is sprayed to the redistribution layer 104 in the passivation region II, the front surface of the chip 101, and the surface of the molding layer 103, and the slurry in the passivation region II is cured, so that a passivation layer 107 is formed in the passivation region II.

Specifically, during the selective spray treatment, the paste is not sprayed to the solder ball regions I, and only the passivation region II between the adjacent solder ball regions I is sprayed with the paste. The thickness of the passivation layer 107 formed is controlled by reasonably controlling the amount of the slurry sprayed by the selective spraying process according to different requirements of the packaging process.

In this embodiment, the material of the passivation layer 107 is polybenzoxazole. In other embodiments, the material of the passivation layer may also be polyimide or benzocyclobutene.

In this embodiment, the method of selective spray coating includes: providing a movable spray head; and moving the spray head above the chip 101 and the plastic package layer 103, and spraying slurry to the passivation area II by the spray head when the spray head moves through the passivation area II.

Specifically, a spray coating device is provided, the spray coating device having a movable spray head; and placing the chip 101 and the plastic packaging layer 103 on a bearing table (chuck), and finishing the selective spraying treatment by using the spraying device.

In order to improve the thickness uniformity of the formed passivation layer 107, the showerhead is moved at least twice over the same passivation region II during the selective spray process to form the passivation layer 107. Since the passivation layer 107 is formed by spraying the slurry at least twice for the same passivation region II, the slurry sprayed at the previous time flows on the passivation region II with a certain time and space before the slurry sprayed at the next time, and thus, when the slurry sprayed at the next time is sprayed, the uniformity of the thickness of the slurry sprayed at the previous time is improved, thereby improving the uniformity of the thickness of the finally formed passivation layer 107.

In this embodiment, in the selective spraying process, a moving path of the nozzle passing over the passivation region II before has a first direction, and a moving path of the nozzle passing over the same passivation region II after has a second direction, where the second direction is different from the first direction. This is advantageous for further improving the thickness uniformity of the passivation layer 107. The reason for this is that:

the thickness distribution of the slurry sprayed to the same passivation region II by the nozzles from different moving paths has difference, and therefore, when the nozzles having different moving paths are used for spraying the slurry to the same passivation region II, the difference thickness distributions compensate each other, thereby further improving the thickness uniformity of the formed passivation layer 107.

In this embodiment, the plurality of solder ball regions I are distributed in an array along the X direction and the Y direction, and correspondingly, the passivation regions II along the X direction form a plurality of rows of passivation regions II, and the passivation regions II along the Y direction form a plurality of columns of passivation regions II. Accordingly, the moving path of the spray head has a direction including: in one or more of the + X direction, -X direction, + Y direction, or-Y direction.

In this embodiment, the selective spray coating process includes: at least one X-direction spraying step, wherein the X-direction spraying step comprises: the spray head moves along the direction of plus X or minus X and passes over the passivation area II along the direction of X until the spray head moves over all rows of passivation areas II; at least one Y-direction spraying step, wherein the Y-direction spraying step comprises: the spray head moves along the direction of + Y or the direction of-Y and passes above the passivation area II along the direction of Y until the spray head moves above all the rows of passivation areas II.

In order to further improve the thickness uniformity of the formed passivation layer 107, improve the protection capability of the passivation layer 107, and improve the performance such as the density of the passivation layer 107, the X-direction spraying step and the Y-direction spraying step are alternately performed to form the passivation layer 107 until the thickness of the passivation layer 107 meets the requirement.

When the spraying step in the X direction is changed to the spraying step in the Y direction, the spraying can be realized by moving the spray head, or by rotating the chip 101 and the plastic package layer 103 by 90 degrees by using a bearing table.

In other embodiments, the step of selectively spraying may further include: at least two X-direction spraying steps, wherein the X-direction spraying step comprises the following steps: at least two X-direction spraying steps, wherein the X-direction spraying step comprises the following steps: the spray head moves along the + X direction and passes through the upper part of a row of passivation areas; the spray head moves along the-X direction and passes through the upper part of the passivation area of the next row; the showerhead is alternately moved in the + X direction and the-X direction until the showerhead is moved over all rows of passivation regions. It should be noted that the showerhead moves at least twice over the passivation region in the same row to form the passivation layer, and a moving path of the showerhead passing over the passivation region in the same row in the previous time is different from a moving path of the showerhead passing over the passivation region in the same row in the subsequent time.

Accordingly, in other embodiments, the showerhead may also be alternately moved in the + Y direction and the-Y direction until the showerhead is moved through all of the column passivation regions to form the passivation layer.

It should be noted that, for the whole row of passivation regions II located between the solder ball regions I of the adjacent rows, the spray head may spray the slurry to the whole row of passivation regions II, or may not spray the slurry to the whole row of passivation regions II if the whole row of passivation regions II is cut and removed in the subsequent cutting process. Accordingly, for the whole row of passivation regions II positioned between the solder ball regions I of the adjacent rows, the spray head can spray the slurry to the whole row of passivation regions II or not spray the slurry to the whole row of passivation regions II.

In other embodiments, the moving path of the spray head may have a direction further including: an oblique direction at 45 degrees to the X direction or an oblique direction at 45 degrees to the Y direction.

Before the selective spraying treatment, the position information of the passivation area II is required to be acquired; and performing the selective spraying treatment based on the acquired position information.

The passivation area II is provided with a first boundary and a second boundary which are opposite, the direction of the first boundary pointing to the second boundary is consistent with the moving direction of the spray head, and when the spray head moves to pass through the first boundary and is away from the first boundary by a first distance, the spray head starts to spray slurry; and when the spray head moves to a second distance from the second boundary and does not exceed the second boundary, the spray head finishes spraying the slurry.

The first distance should not be too large. If the first distance is too large, the effective spraying area of the spray head passing through the upper part of the same passivation area II at a time is too small, and the thickness of a film layer formed by corresponding spraying at a time is thin, so that the efficiency of selective spraying treatment is low. For this reason, in the present embodiment, the first distance ranges from 0mm to 30mm, for example, 5mm, 10mm, 15mm, and 25 mm.

The second distance should not be too small, nor too large. If the second distance is too small, the spray head is easy to spray the slurry to the region outside the passivation area II; if the second distance is too large, the effective spraying area of the spray head passing through the upper part of the same passivation area II at a time is too small, and the thickness of a film layer formed by corresponding spraying at a time is thin, so that the efficiency of selective spraying treatment is low. For this reason, in the present embodiment, the second distance ranges from 5mm to 30mm, for example, 10mm, 18mm, 23mm, and 28 mm.

In the selective spray coating process, the vertical distance between the spray head and the surface of the redistribution layer 104 should not be too small, nor too large. The closer the vertical distance between the nozzle and the surface of the redistribution layer 104 is, the smaller the area of the region sprayed by the nozzle in unit time is, the thicker the film layer formed by spraying the slurry in the passivation region II in unit time is, and the smaller the thickness uniformity of the film layer formed correspondingly is, which is not beneficial to improving the thickness uniformity of the passivation layer 107. The farther the vertical distance between the head and the surface of the redistribution layer 104, the more difficult it is to control the position accuracy of the head spraying the slurry, and the slurry loss is easily caused; moreover, the vertical distance between the head and the surface of the redistribution layer 104 is too long, and the slurry is exposed in the air for too long time before reaching the surface of the redistribution layer 104 and is easy to solidify, which affects the quality of the passivation layer 107.

For this reason, in the present embodiment, the perpendicular distance between the head and the surface of the redistribution layer 104 is 5mm to 30mm, for example, 10mm, 15mm, 20mm, and 28 mm.

In the selective spraying treatment process, the moving speed of the spray head is not too small or too fast. If the moving speed of the spray head is too low, the spraying efficiency of the selective spraying treatment is low, and the packaging process is influenced; and under the condition that the flow rate of the slurry sprayed by spraying is constant, the amount of the slurry sprayed by the spray head in the process of moving through the passivation region II at a single time is larger, so that the thickness of the film layer formed in the passivation region II at a single time is thicker, the uniformity of the thickness of the film layer is relatively poorer, and the improvement of the uniformity of the thickness of the finally formed passivation layer 107 is not facilitated. If the moving speed of the spray head is too high, the difficulty of controlling the spray head to spray the slurry is increased, and the slurry is easily sprayed to the area outside the passivation area II.

For this reason, in the present embodiment, the velocity at which the head moves during the selective spray treatment is 0.01m/s to 0.1m/s, for example, 0.03m/s, 0.05m/s, 0.07m/s, 0.9 m/s.

In the selective spraying treatment process, the flow rate of the slurry sprayed by the spray head is not too small or too large. If the flow rate of the slurry sprayed by the spray head is too small, the corresponding spraying efficiency of the selective spraying treatment is low, and the packaging process is influenced; if the flow rate of the slurry sprayed by the spray head is too large, the amount of the slurry sprayed in the process that the spray head moves through the passivation region II in a single time is large, the thickness of the film layer formed in the passivation region II in a single time is thick, the uniformity of the thickness of the film layer is relatively poor, and the improvement of the uniformity of the thickness of the finally formed passivation layer 107 is not facilitated. For this reason, in this embodiment, the flow rate of the slurry sprayed by the spray head during the selective spraying treatment is 1mL/s to 10mL/s, for example, 2mL/s, 4mL/s, 6mL/s, 9 mL/s.

And after the selective spraying treatment is finished, curing the slurry positioned in the passivation area II. The curing process is used to cure and shape the slurry in the passivation region II, and during the curing process, a cross-linking reaction occurs inside the slurry to form the passivation layer 107 having insulation, bending resistance, moisture resistance, and heat resistance.

Specifically, the curing treatment adopts a method comprising the following steps: under vacuum, N₂Or baking the slurry in the passivation area II in an inert gas environment.

In this embodiment, the process temperature used for the curing treatment should not be too low or too high. If the process temperature adopted by the curing treatment is too low, the internal crosslinking reaction of the slurry is incomplete in the curing treatment process, and the protective effect of the passivation layer 107 is influenced; if the process temperature used for the curing process is too high, the performance of the chip 101 may be adversely affected, and the process temperature used for the curing process is too high, the internal stress of the passivation layer 107 is correspondingly large, and the adhesion between the passivation layer 107 and the rewiring layer 104 is easily reduced.

For this reason, in this embodiment, the curing process is performed at a process temperature of 140 ℃ to 160 ℃, for example, 145 ℃, 150 ℃, 155 ℃, within the process temperature range, so that the internal crosslinking reaction of the slurry located in the passivation region II is gradually completed, and the number of the reactive groups and the reactive sites in the molecules is gradually reduced, thereby forming the passivation layer 107 having a stable three-dimensional network structure, so that the passivation layer 107 has high strength and high hardness, thereby ensuring that the passivation layer 107 has high bending resistance, humidity resistance, and heat resistance; and the passivation layer 107 has moderate internal stress, so the adhesion between the passivation layer 107 and the rewiring layer 104 is strong.

In this embodiment, before the curing treatment, the method further includes: and in the selective spraying treatment process, heating the slurry in the passivation area II, wherein the process temperature of the heating treatment is lower than that of the curing treatment.

In the heating treatment process, the fluidity of the slurry in the passivation region II is improved, which is beneficial to improving the thickness uniformity of the formed passivation layer 107; and, the solvent molecules which hinder the cross-linking reaction exist in the slurry, and the heating treatment is beneficial to volatilizing the solvent from the slurry, so that the cross-linking reaction degree in the subsequent curing treatment process is improved, and the strength and the hardness of the formed passivation layer 107 are improved.

The process temperature of the heating treatment is not suitable to be too low or too high. If the process temperature of the heating treatment is too low, the fluidity of the slurry in the passivation area II is relatively poor, and the volatilization degree of a solvent which can influence the crosslinking reaction in the slurry is low; if the process temperature of the heat treatment is too high, the slurry in the passivation region II is easily hardened too early, and the passivation layer 107 is easily delaminated.

Therefore, in this embodiment, the process temperature of the heating treatment is 20 ℃ to 120 ℃, for example, 30 ℃, 60 ℃, 100 ℃. The process temperature adopted by the heating treatment is moderate, so that the slurry in the passivation region II is ensured to have proper fluidity, the solvent in the slurry is volatilized as much as possible, and meanwhile, the problem of the delamination of the passivation layer 107 caused by the overhigh process temperature of the heating treatment can be avoided.

In other embodiments, the curing process may be performed during the selective spraying process.

Referring to fig. 11, after the passivation layer 107 is formed, the solder layer 105 (see fig. 10) is subjected to a reflow process, and a solder ball 108 electrically connected to the redistribution layer 104 is formed on the redistribution layer 104 in the solder ball region I.

In the reflow process, the solder layer 205 is heated to melt the solder layer 205, and the shape of the solder layer 205 is changed by the surface tension, thereby forming the solder ball 108.

After the reflow process, the solder balls 108 having shapes meeting the process requirements are formed. In this embodiment, the solder ball 108 is spherical.

During the reflow process, the passivation layer 107 around the solder layer 105 functions to block metal ions in the solder layer from diffusing into the rewiring layer 104.

In this embodiment, an ubm layer 106 is further formed between the redistribution layer 104 and the solder balls 108, during the reflow process, adhesion between the ubm layer 106 and the solder balls 108 is enhanced, and the ubm layer 106 blocks metal ions in the solder balls 108, so as to prevent the metal ions from diffusing into the redistribution layer 104.

According to the packaging method provided by the embodiment, the passivation layer 107 is formed by using selective spraying treatment, so that the solder balls 108 are prevented from being damaged by a process for forming the passivation layer 107, and the solder balls 108 always have good electric connection performance, so that the packaging effect is improved, and the reliability of the formed packaging structure is improved.

Another embodiment of the present invention further provides a packaging method, different from the previous embodiment, in this embodiment, a passivation layer is formed before the solder layer is formed. The system-in-package method provided by the present embodiment will be described in detail below with reference to the accompanying drawings, and it should be noted that the same or corresponding parts as those in the previous embodiment will not be described in detail below.

Fig. 12 to fig. 15 are schematic structural diagrams corresponding to steps of a packaging method according to another embodiment of the present invention.

Referring to fig. 12, providing a plurality of chips 201, where each chip 201 has a front surface and a back surface opposite to the front surface, an electrical connection structure 202 is formed in each chip 201, the front surface of each chip 201 exposes out of the surface of the electrical connection structure 202, a molding compound layer 203 is formed between adjacent chips 201, and the front surface of each chip 201 and the surface of each molding compound layer 203 have a plurality of solder ball regions I and passivation regions II between adjacent solder ball regions I; a redistribution layer 204 electrically connected with the electrical connection structure 202 is formed on the front surface of each chip 201, and each redistribution layer 204 spans the solder ball region I and a passivation region II adjacent to the solder ball region I.

For the corresponding descriptions of the chip 201, the molding layer 203 and the redistribution layer 204, reference may be made to the corresponding descriptions of the foregoing embodiments, and further description is omitted here.

The subsequent process steps comprise: forming solder balls electrically connected with the redistribution layer 204 on the redistribution layer 204 of the solder ball area I; and performing selective spraying treatment, spraying slurry to the rewiring layer 204 of the passivation area II, the front surface of the chip 201 and the surface of the plastic packaging layer 203, and curing the slurry of the passivation area II to form a passivation layer in the passivation area II.

Wherein the process of forming the solder balls comprises: forming a solder layer electrically connected with the redistribution layer 204 on the redistribution layer 204 of the solder ball region I; and carrying out reflow treatment on the solder layer to form the solder ball. In this embodiment, the passivation layer is formed before the solder layer is formed. The following detailed description will be made in conjunction with the accompanying drawings.

Referring to fig. 13, a selective spraying process is performed, slurry is sprayed to the redistribution layer 204 in the passivation region II, the front surface of the chip 201, and the surface of the molding layer 203, and the slurry in the passivation region II is cured, so that the passivation layer 207 is formed in the passivation region II.

The passivation layer 207 exposes the surface of the redistribution layer 204 in the solder ball region I. For the process steps for forming the passivation layer 207, reference may be made to the corresponding description of the previous embodiment, and further description is omitted here.

In this embodiment, the passivation layer 207 is formed by selective spraying, so that the problem of process damage to the redistribution layer 204 in the solder ball region I is avoided, and the redistribution layer 204 in the solder ball region I maintains good conductivity, thereby improving the performance of the formed package structure.

In the prior art, the process step of forming the passivation layer includes removing the passivation film on the surface of the redistribution layer in the solder ball area, and the redistribution layer in the solder ball area is exposed in the process environment of removing the passivation film in the solder ball area, so that the redistribution layer in the solder ball area is easily damaged to cause poor conductivity, and further the electrical connection performance between the redistribution layer and the subsequently formed solder ball is affected, and the package structure is low or even fails.

It should be noted that, in other embodiments, the ubm layer may be formed first, and then the passivation layer may be formed.

Referring to fig. 14, an ubm layer 206 is formed on the surface of the redistribution layer 204 in the ball region I and on the surface of the passivation layer 207; forming a solder layer 205 on the surface of the ubm layer 206 in the solder ball region I; the ubm layer 206 not covered by the solder layer 205 is removed.

In this embodiment, the ubm layer 206 is formed between the solder layer 205 and the redistribution layer 204.

In other embodiments, the solder layer may be directly formed on the surface of the redistribution layer in the solder ball region without forming the ubm layer.

Referring to fig. 15, the solder layer 205 (see fig. 14) is subjected to a reflow process to form the solder balls 208.

For the description of the reflow process, reference may be made to the corresponding description of the foregoing embodiments, and further description is omitted here.

It should be noted that, in other embodiments, the passivation layer may also be formed after the solder balls are formed, that is, after the reflow process is performed.

A further embodiment of the present invention further provides a packaging method, which is different from the previous embodiment in that a copper pillar is further formed between the solder ball and the redistribution layer in this embodiment, and the copper pillar penetrates through the passivation layer. The packaging method provided by the present embodiment will be described in detail below with reference to the accompanying drawings, and it should be noted that the same or corresponding portions as those of the previous embodiments will not be described in detail below.

Referring to fig. 16, providing a plurality of chips 301, where each chip 301 has a front surface and a back surface opposite to the front surface, an electrical connection structure 302 is formed in each chip 301, the front surface of each chip 301 exposes out of the surface of the electrical connection structure 302, a molding compound layer 303 is formed between adjacent chips 301, and the front surface of each chip 301 and the surface of each molding compound layer 303 have a plurality of solder ball regions I and passivation regions II between adjacent solder ball regions I; a redistribution layer 304 electrically connected to the electrical connection structure 302 is formed on the front surface of each chip 301, and each redistribution layer 304 spans the solder ball region I and a passivation region II adjacent to the solder ball region I.

Referring to fig. 17, a conductive pillar (pillar)306 is formed on the surface of the redistribution layer 304 in the solder ball region I.

In this embodiment, the conductive pillar 306 is made of copper. In other embodiments, the material of the conductive pillar may also be aluminum or tungsten.

Referring to fig. 18, a selective spraying process is performed to spray slurry onto the redistribution layer 304, the front surface of the chip 301, and the surface of the molding layer 303 in the passivation region II, and the slurry in the passivation region II is cured to form a passivation layer 307 in the passivation region II.

Specifically, the passivation layer 307 is formed between adjacent conductive pillars 306, and the passivation layer 307 covers the sidewall surfaces of the conductive pillars 306.

For a detailed description of the selective spray coating process, reference is made to the corresponding description of the previous embodiments.

In this embodiment, the passivation layer 307 is formed by selective spraying, which avoids process damage to the conductive pillar 307 caused by a process for forming the passivation layer 307, so that the conductive pillar 307 has good conductive performance all the time, and thus the conductive pillar 307 has good electrical connection performance with a subsequently formed solder ball, thereby improving a packaging effect.

In addition, in this embodiment, the passivation layer 307 is formed after the conductive pillars 306 are formed, and since the passivation layer 307 has a relatively thick thickness, during the selective spraying process, the conductive pillars 306 function to block slurry from flowing to the solder ball region I, which is beneficial to improving the position accuracy of the formed passivation layer 307.

Referring to fig. 19, a solder ball 308 electrically connected to the redistribution layer 304 is formed on the redistribution layer 304 in the solder ball area I.

Specifically, the solder ball 308 is formed on the surface of the conductive post 306.

In this embodiment, the process steps for forming the solder balls 308 include: forming a solder layer electrically connected with the redistribution layer 304 on the redistribution layer 304 in the solder ball region I, wherein the solder layer is in contact with the conductive pillar; and performing reflow processing on the solder layer to form the solder balls 308.

The packaging method provided by the embodiment reduces or even avoids the damage of the process for forming the passivation layer 307 to the redistribution layer 304 of the solder ball area I, and avoids the damage of the process for forming the passivation layer 307 to the conductive post 306, so that the redistribution layer 304 and the conductive post 306 have good conductive performance all the time, thereby improving the reliability of the packaging structure formed by packaging and improving the packaging effect.

It should be noted that, the above embodiments of the present invention take wafer level packaging as an example for description, and the packaging method provided by the present invention can also be applied to system level packaging, wafer level system packaging and 3D packaging.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A method of packaging, comprising:

providing a plurality of chips, wherein each chip is provided with a front surface and a back surface opposite to the front surface, an electric connection structure is formed in each chip, the front surface of each chip is exposed out of the surface of the electric connection structure, a plastic package layer is formed between every two adjacent chips, and the front surface of each chip and the surface of the plastic package layer are provided with a plurality of welding ball areas and passivation areas between every two adjacent welding ball areas;

forming a rewiring layer electrically connected with the electric connection structure on the front surface of each chip;

forming a solder ball electrically connected with the rewiring layer on the rewiring layer of the solder ball area;

and carrying out selective spraying treatment, spraying slurry to the rewiring layer, the front surface of the chip and the surface of the plastic packaging layer in the passivation area, and carrying out curing treatment on the slurry in the passivation area to form a passivation layer in the passivation area.

2. The encapsulation method of claim 1, wherein the selective spray coating process comprises: providing a movable spray head; and moving the spray head above the chip and the plastic package layer, and spraying slurry to the passivation area by the spray head when the spray head moves to pass through the passivation area.

3. The encapsulation method of claim 2, wherein the showerhead is moved at least twice over the same passivation region to form the passivation layer; and the moving path of the spray head passing through the passivation area for the previous time has a first direction, and the moving path of the spray head passing through the same passivation area for the next time has a second direction, wherein the second direction is different from the first direction.

4. The method of packaging as claimed in claim 3, wherein the plurality of solder ball areas are arranged in an array along an X-direction and a Y-direction; the moving path of the spray head has a direction including: in one or more of the + X direction, -X direction, + Y direction, or-Y direction.

5. The encapsulation method of claim 4, wherein the path of travel of the nozzle head has a direction further comprising: an oblique direction at 45 degrees to the X direction or an oblique direction at 45 degrees to the Y direction.

6. The encapsulation method according to claim 1, wherein before the selective spray coating process, position information of the passivation region is acquired; and performing the selective spraying treatment based on the acquired position information.

7. The encapsulation method according to claim 2, wherein the moving speed of the head is in a range of 0.01m/s to 0.1 m/s.

8. The encapsulation method according to claim 1, wherein the passivation layer is made of polybenzoxazole, polyimide, or benzocyclobutene.

9. The encapsulation method according to claim 1, wherein the curing process is performed after the selective spray process is finished; and before the curing treatment, heating the slurry in the passivation region during the selective spraying treatment, wherein the process temperature of the heating treatment is lower than that of the curing treatment.

10. The packaging method according to claim 9, wherein the process temperature of the heating treatment is in a range of 20 ℃ to 120 ℃; the process temperature range of the curing treatment is 140-160 ℃.

11. The packaging method of claim 1, wherein the process step of forming the solder balls comprises: forming a solder layer electrically connected with the rewiring layer on the rewiring layer of the solder ball area; and carrying out reflow treatment on the solder layer to form the solder ball.

12. The packaging method according to claim 11, wherein the passivation layer is formed after the solder layer is formed and before a reflow process is performed.

13. The packaging method according to claim 12, wherein an under ball metal layer is further formed between the solder layer and the re-wiring layer; the process steps for forming the passivation layer, the under ball metal layer and the solder layer include: forming an under-ball metal layer on the surface of the rewiring layer of the solder ball area and the passivation area; forming the solder ball layer on the surface of the under-ball metal layer of the solder ball area; removing the metal layer under the ball which is not covered by the solder layer; forming a passivation layer on the passivation region after removing the UBM layer not covered by the solder layer.

14. The packaging method of claim 11, wherein the passivation layer is formed before the solder layer is formed.

15. The packaging method according to claim 14, wherein an under ball metal layer is further formed between the solder layer and the re-wiring layer; forming the passivation layer before forming the ubm layer; the process steps for forming the passivation layer, the under-ball metal layer and the solder layer include: forming the passivation layer in the passivation region; forming an under-ball metal layer on the surface of the rewiring layer of the solder ball area by using the surface of the passivation layer; forming the solder layer on the surface of the metal layer under the ball in the solder ball area; and removing the metal layer under the ball which is not covered by the solder layer.

16. The packaging method according to claim 15, wherein a conductive pillar is further formed between the solder ball and the redistribution layer, and the conductive pillar penetrates through the passivation layer; after forming the conductive pillars, forming the passivation layer.

17. The packaging method according to claim 1, wherein the packaging method is applied to a wafer level system package, a wafer level package, a system level package or a 3D package.