CN111369949B - Display panel and scanning driving method thereof - Google Patents

Display panel and scanning driving method thereof Download PDF

Info

Publication number
CN111369949B
CN111369949B CN202010348250.XA CN202010348250A CN111369949B CN 111369949 B CN111369949 B CN 111369949B CN 202010348250 A CN202010348250 A CN 202010348250A CN 111369949 B CN111369949 B CN 111369949B
Authority
CN
China
Prior art keywords
transistor
electrically connected
pixel
terminal
signal line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202010348250.XA
Other languages
Chinese (zh)
Other versions
CN111369949A (en
Inventor
张蒙蒙
李玥
杨帅
周星耀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan Tianma Microelectronics Co Ltd
Original Assignee
Shanghai Tianma AM OLED Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Tianma AM OLED Co Ltd filed Critical Shanghai Tianma AM OLED Co Ltd
Priority to CN202010348250.XA priority Critical patent/CN111369949B/en
Publication of CN111369949A publication Critical patent/CN111369949A/en
Application granted granted Critical
Publication of CN111369949B publication Critical patent/CN111369949B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of El Displays (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The invention discloses a display panel and a scanning driving method thereof, wherein the display panel comprises: a display area; the display area comprises a plurality of sub-pixels which are arranged in an array mode, and the sub-pixels are arranged along a first direction to form a pixel row; the pixel array further comprises n signal line groups arranged along the second direction, each signal line group comprises scanning signal lines extending along the first direction and reset control signal lines extending along the first direction, and the signal line groups correspond to the pixel rows one to one; the scanning signal line in the ith signal line group is electrically connected with the reset control signal line in the ith + j signal line group, n and i are both positive integers, j is a positive integer greater than or equal to 3, and i + j is less than or equal to n; the 1 st to jth reset control signal lines are not electrically connected with the scanning signal line; the first direction intersects the second direction. The display panel and the scanning driving method thereof provided by the invention can improve the hysteresis characteristic of the driving transistor and reduce the power consumption caused by resetting.

Description

Display panel and scanning driving method thereof
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display panel and a scan driving method thereof.
Background
Organic Light-Emitting diodes (OLEDs) are one of the hot spots in the field of current flat panel Display research, and compared with Liquid Crystal Displays (LCDs), OLED displays have the advantages of low power consumption, self-luminescence, wide viewing angle, and fast response speed.
The OLED display is provided with a plurality of pixel circuits, each pixel circuit generally comprises a driving transistor, a plurality of switching transistors, a storage capacitor and an organic light emitting diode, and driving current generated by the driving transistor drives the organic light emitting diode to emit light for display. When a pixel displays a plurality of frames of black pictures, the driving transistor is in a cut-off state for a long time, at the moment, because the control end of the driving transistor is higher in potential, the driving transistor is under a forward bias for a long time, the threshold voltage drifts, and then the driving transistor is switched to a white picture, because the threshold voltage of the driving transistor cannot be recovered in time, namely, the display brightness is lower when the first frames of white pictures are caused by the hysteresis effect of the driving transistor, and the display effect is poorer.
Disclosure of Invention
In view of the above, the present invention provides a display panel and a scan driving method thereof, which can reduce power consumption while improving the hysteresis characteristic of a driving transistor.
In one aspect, the present invention provides a display panel, comprising:
a display area;
the display area comprises a plurality of sub-pixels which are arranged in an array mode, and the sub-pixels are arranged along a first direction to form a pixel row;
the pixel array further comprises n signal line groups arranged along the second direction, each signal line group comprises scanning signal lines extending along the first direction and reset control signal lines extending along the first direction, and the signal line groups correspond to the pixel rows one to one;
the scanning signal line in the ith signal line group is electrically connected with the reset control signal line in the ith + j signal line group, n and i are both positive integers, j is a positive integer greater than or equal to 3, and i + j is less than or equal to n;
the 1 st to jth reset control signal lines are not electrically connected with the scanning signal line;
the first direction intersects the second direction.
In another aspect, the present invention provides a scan driving method of a display panel, the display panel including:
a display area;
the display area comprises a plurality of sub-pixels which are arranged in an array mode, and the sub-pixels are arranged along a first direction to form a pixel row;
the pixel array further comprises n signal line groups arranged along the second direction, each signal line group comprises scanning signal lines extending along the first direction and reset control signal lines extending along the first direction, and the signal line groups correspond to the pixel rows one to one;
the scanning signal line in the ith signal line group is electrically connected with the reset control signal line in the ith + j signal line group, n and i are both positive integers, j is a positive integer greater than or equal to 3, and i + j is less than or equal to n;
the 1 st to jth reset control signal lines are not electrically connected with the scanning signal line;
the first direction intersects the second direction;
each sub-pixel comprises a pixel driving circuit;
the scanning driving method comprises the following steps:
inputting a first effective level signal to a first scanning signal input end of a pixel driving circuit of a 1 st to a jth pixel row in sequence through a first effective level signal sent by a 1 st to a jth reset control signal line, and resetting the pixel driving circuit; inputting a third effective level signal to a second scanning signal input end of the pixel driving circuit of the 1 st to nth pixel rows in sequence through a third effective level signal sent by the 1 st to nth scanning signal lines, and writing data into the pixel driving circuit; simultaneously, second effective level signals sent by the j +1 th to the nth reset control signal lines are sequentially input to the first scanning signal input ends of the pixel driving circuits of the j +1 th to nth pixel rows, and the pixel driving circuits are reset;
the third effective level signal of the ith pixel row and the second effective level signal of the (i + j) th pixel row are the same effective level signal.
In another aspect, the present invention provides a scan driving method of a display panel, the display panel including:
a display area;
the display area comprises a plurality of sub-pixels which are arranged in an array mode, and the sub-pixels are arranged along a first direction to form a pixel row;
the pixel array further comprises n signal line groups arranged along the second direction, each signal line group comprises scanning signal lines extending along the first direction and reset control signal lines extending along the first direction, and the signal line groups correspond to the pixel rows one to one;
the scanning signal line in the ith signal line group is electrically connected with the reset control signal line in the ith + j signal line group, n and i are both positive integers, j is a positive integer greater than or equal to 3, and i + j is less than or equal to n;
the 1 st to jth reset control signal lines are not electrically connected with the scanning signal line;
the first direction intersects the second direction;
each sub-pixel comprises a pixel driving circuit;
the scanning driving method comprises the following steps:
a first effective level signal is sent through 1 st to jth reset control signal lines, and a first effective level signal is input to a first scanning signal input end of a pixel driving circuit of 1 st to jth pixel rows at the same time, and the pixel driving circuit is reset; inputting a third effective level signal to a second scanning signal input end of the pixel driving circuit of the 1 st to nth pixel rows in sequence through a third effective level signal sent by the 1 st to nth scanning signal lines, and writing data into the pixel driving circuit; simultaneously, second effective level signals sent by the j +1 th to the nth reset control signal lines are sequentially input to the first scanning signal input ends of the pixel driving circuits of the j +1 th to nth pixel rows, and the pixel driving circuits are reset;
the third effective level signal of the ith pixel row and the second effective level signal of the (i + j) th pixel row are the same effective level signal.
Compared with the prior art, the display panel and the scanning driving method thereof provided by the invention at least realize the following beneficial effects:
the invention discloses a display panel and a scanning driving method thereof.A first effective level signal is sent by 1 st to jth reset control signal lines, and simultaneously, the first effective level signal is input to a first scanning signal input end of a pixel driving circuit of 1 st to jth pixel rows and resets the pixel driving circuit; inputting a third effective level signal to a second scanning signal input end of the pixel driving circuit of the 1 st to nth pixel rows in sequence or simultaneously through a third effective level signal sent by the 1 st to nth scanning signal lines, and writing data into the pixel driving circuit; simultaneously, second effective level signals sent by the j +1 th to the nth reset control signal lines are sequentially input to the first scanning signal input ends of the pixel driving circuits of the j +1 th to nth pixel rows, and the pixel driving circuits are reset; the third effective level signal of the ith pixel row and the second effective level signal of the (i + j) th pixel row are the same effective level signal. The display panel and the scanning driving method thereof increase the holding time of low voltage during resetting, prolong the time from resetting to data writing to be more than 3 times of line time, namely the time interval of the resetting time before the data writing time is more than or equal to 3 line times, and can reduce the power consumption caused by resetting while improving the hysteresis characteristic of the driving transistor.
Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
Fig. 1 is a display panel in the related art;
FIG. 2 is a timing diagram of scan driving signals of the display panel of FIG. 1;
FIG. 3 is a display panel provided by the present invention;
FIG. 4 is a schematic diagram of a pixel driving circuit in the display panel of FIG. 3;
FIG. 5 is a signal timing diagram of a driving method of the pixel driving circuit of FIG. 4;
FIG. 6 is a further display panel provided by the present invention;
FIG. 7 is a further display panel provided by the present invention;
FIG. 8 is a timing diagram of signals for a driving method of the pixel driving circuit of the 1 st pixel row of the display panel of FIG. 7;
FIG. 9 is a timing diagram of the signals of the driving method of the pixel driving circuit of the 2 nd pixel row of the display panel of FIG. 7;
FIG. 10 is a timing diagram of the driving method of the pixel driving circuit of the 3 rd pixel row of the display panel of FIG. 7;
FIG. 11 is a further display panel provided by the present invention;
fig. 12 is a further display panel provided by the present invention.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
In the related art, please refer to fig. 1 and fig. 2, fig. 1 is a display panel in the related art; fig. 2 is a timing diagram of scan driving signals of the display panel of fig. 1. In a related art, a display panel 100 is provided, where the display panel 100 includes a display area 01; the display area 01 includes a plurality of sub-pixels 021 arranged in an array, the sub-pixels 021 are arranged along a first direction X to form a pixel row 02; the pixel array further comprises n signal line groups 03 arranged along the second direction Y, each signal line group 03 comprises a scanning signal line 031 extending along the first direction X, a reset control signal line 032 extending along the first direction X, and a light-emitting control signal line 033 extending along the first direction X, and the signal line groups 03 correspond to the pixel rows one to one; the first direction X intersects the second direction Y.
In a displayed frame time, before the light-emitting stage, N times of reset stages and N times of data writing stages are included, after the nth time of light-emitting reset stages, N is more than or equal to 3 and less than or equal to N-1, and N and N are positive integers. Fig. 2 only illustrates the case where N is 3.
Reset phase T01: sequentially sending a first effective level signal to the reset control terminal S1 and a low level signal to the reset control terminal S1 through a reset control signal line 031, initializing the driving transistor, that is, resetting the pixel driving circuit of the pixel row 02;
data write phase T02: sequentially sending a second effective level signal to the data write control terminal S2 through the scanning signal line 032, sending a low level signal to the data write control terminal S2, and writing a data signal voltage to the driving transistor, that is, writing data to the pixel driving circuit of the pixel row 02;
lighting phase T03: the third effective level signal is sequentially sent to the emission signal control end Emit through the emission control signal line 033, the low level signal is sent to the emission signal control end Emit, the pixel driving circuit of the pixel row 02 is controlled, and the driving transistor is controlled to drive the light emitting element to Emit light.
Meanwhile, one pulse signal of the invalid level signal between the adjacent third valid level signals sent by the light emission control signal line 033 overlaps the three pulse signals of the first valid level signal sent by the reset control signal line 031 and the three pulse signals of the second valid level signal sent by the scanning signal line 032. Therefore, in a display frame time, before a light-emitting stage, N times of reset stages and N times of data writing stages are used, N times of large current flows in the driving transistor, the hysteresis effect caused by threshold voltage drift of the driving transistor is improved, and the display effect of the display panel is improved.
In order to solve the problem of hysteresis of the driving transistor in the display panel while reducing power consumption, the inventors have made the following studies on the display panel in the related art: the invention provides a display panel. As for a display panel provided by the present invention, the following will be described in detail.
Fig. 3 is a display panel 200 according to an embodiment of the present invention, in which the display panel 200 includes a display area AA; the display area AA includes a plurality of sub-pixels p arranged in an array, and the sub-pixels p are arranged along a first direction X to form a pixel row 1; n signal line groups 2 arranged along the second direction Y are further included, each signal line group 2 includes a scanning signal line 21 extending along the first direction X and a reset control signal line 22 extending along the first direction X, and the signal line groups 2 correspond to the pixel rows 1 one to one; the scanning signal line 21 in the i-th signal line group 2 is electrically connected to the reset control signal line 22 in the i + j-th signal line group 2, that is, signals are simultaneously transmitted to the scanning signal line 21 in the i-th signal line group 2 and the reset control signal line 22 in the i + j-th signal line group 2; n and i are both positive integers, j is a positive integer greater than or equal to 3, and i + j is less than or equal to n; the 1 st to jth reset control signal lines 22 are not electrically connected to the scanning signal line 21; the first direction X intersects the second direction Y. The ith signal line group refers to a signal line group corresponding to the ith pixel row 1, the 1 st reset control signal line refers to a reset control signal line corresponding to the 1 st pixel row 1, and the jth reset control signal line refers to a reset control signal line corresponding to the jth pixel row 1.
With reference to fig. 3, fig. 3 only illustrates the cases where n is 8 and j is 3, and the present invention does not specifically require specific values of n, i, and j, and the above conditions are satisfied.
It is further understood that the present invention provides a display panel 200, in which the scan signal lines 21 in the first signal group D1 are electrically connected to the reset control signal lines 22 in the fourth signal group D4, the scan signal lines 21 in the second signal group D2 are electrically connected to the reset control signal lines 22 in the fifth signal group D5, the scan signal lines 21 in the third signal group D3 are electrically connected to the reset control signal lines 22 in the sixth signal group D6, the scan signal lines 21 in the fourth signal group D4 are electrically connected to the reset control signal lines 22 in the seventh signal group D7, and the scan signal lines 21 in the fifth signal group D5 are electrically connected to the reset control signal lines 22 in the eighth signal group D8. That is, signals are simultaneously transmitted to the scanning signal line 21 in the i-th signal line group 2 and the reset control signal line 22 in the i + j-th signal line group 2, which corresponds to the case where the i + j-th signal line group 2 transmits a signal to the reset control signal line 22 before j line times for scanning the scanning signal line 21, and the threshold voltage of the driving transistor of the i + j-th pixel row is maintained at a long negative bias voltage, where the line time is the time taken to scan one row of pixel rows 1. The hysteresis effect caused by the threshold voltage drift of the driving transistors in the pixel rows can be improved, the problem of nonuniform brightness during the switching of black and white pictures in the display process is solved, and the display effect of the display panel is improved; meanwhile, compared with the prior art, the power consumption can be reduced without resetting for many times.
With continued reference to fig. 3, the 1 st to jth reset control signal lines 22, that is, the first to third reset control signal lines 22, which are individually disposed, may sequentially send signals to the first to third pixel rows, and after the first reset control signal line 221 sends the reset control signal to the first pixel row 11, send a scan signal to the first pixel row 11 by using the first scan signal line 211 at an interval of 3 line times; after the second reset control signal line 222 transmits the reset control signal to the second pixel row 12, the scan signal is transmitted to the second pixel row 12 by the second scan signal line 212 at an interval of 3 line times; after the third reset control signal line 223 transmits the reset control signal to the third pixel row 13, the scan signal is transmitted to the third pixel row 13 with the third scan signal line 213 at an interval of 3 line times; the hysteresis effect caused by the threshold voltage drift of the driving transistors in the first pixel row, the second pixel row and the third pixel row can be solved, the problem of nonuniform brightness during the switching of black and white pictures in the display process is solved, and the display effect of the display panel is improved; meanwhile, multiple resets are not needed, and power consumption can be further reduced.
Referring to fig. 4, fig. 4 is a schematic diagram of a pixel driving circuit in the display panel of fig. 3; the display panel 200 includes pixel driving circuits 300, and each sub-pixel p includes one pixel driving circuit 300. The pixel driving circuit 300 includes:
a first transistor M1, having a control terminal electrically connected to the light-emitting signal input terminal, a first terminal electrically connected to the first power signal terminal PVDD, and a second terminal electrically connected to the first terminal of the driving transistor M;
a second transistor M2, having a control terminal electrically connected to the second scan signal input terminal S2, a first terminal electrically connected to the data signal input terminal Vdata, and a second terminal electrically connected to the first terminal of the driving transistor M;
a driving transistor M having a control terminal electrically connected to the second terminal of the fourth transistor M4, and a first terminal electrically connected to the second terminal of the first transistor M1 and the second terminal of the second transistor M2;
a third transistor M3 having a control terminal electrically connected to the second scan signal input terminal S2, a first terminal electrically connected to the second terminal of the fourth transistor M4 and the second terminal of the storage capacitor Cst, and a second terminal electrically connected to the second terminal of the driving transistor M and the first terminal of the fifth transistor M5;
a fourth transistor M4, having a control terminal electrically connected to the first scan signal input terminal S1, a first terminal electrically connected to the reference voltage signal input terminal Vref, and a second terminal electrically connected to the control terminal of the driving transistor M;
a fifth transistor M5 having a control terminal electrically connected to the emission signal input terminal Emit, a first terminal electrically connected to the second terminal of the driving transistor M and the second terminal of the third transistor M3, and a second terminal electrically connected to the anode of the light emitting element O;
a sixth transistor M6 having a control terminal electrically connected to the second scan signal input terminal, a first terminal electrically connected to the reference voltage signal input terminal, and a second terminal electrically connected to the first terminal of the light emitting element O;
a light emitting element O having a first terminal electrically connected to the second terminal of the fifth transistor M5 and the second terminal of the sixth transistor M6, and a second terminal electrically connected to the second power signal terminal PVEE;
the storage capacitor Cst has a first terminal electrically connected to the first power signal terminal PVDD and a second terminal electrically connected to the control terminal of the driving transistor M, the first terminal of the third transistor M3, and the second terminal of the fourth transistor M4.
With continued reference to fig. 3 and 4, the scan signal line 21 in the display panel 200 is electrically connected to the control terminal of the second transistor M2 and the control terminal of the third transistor M3; the reset control signal line 22 is electrically connected to the control terminal of the fourth transistor M4.
It is understood that the signal transmitted through the scan signal line 21 may control the second transistor M2 and the third transistor M3 in the pixel driving circuit to be turned on; the fourth transistor M4 is controlled to be turned on by the reset control signal line 22.
With continuing reference to fig. 3 and 4, the present invention further provides a scan driving method of the display panel, which is applied to the display panel in fig. 3, the display panel 200 includes a pixel driving circuit 300, each sub-pixel p includes a pixel driving circuit 300, and the scan driving method includes:
the first active level signal sent through the 1 st to jth reset control signal lines 22 sequentially inputs the first active level signal to the first scan signal input terminal S1 of the pixel driving circuit 300 of the 1 st to jth pixel rows, and resets the pixel driving circuit 300, specifically, resets the control terminal of the driving transistor M in the pixel driving circuit 300;
the third effective level signal is sequentially input to the second scanning signal input terminal S2 of the pixel driving circuit 300 of the 1 st to nth pixel rows through the third effective level signal sent from the 1 st to nth scanning signal line 21, and data is written to the pixel driving circuit 300; meanwhile, the second effective level signals transmitted through the j +1 th to nth reset control signal lines 22 are sequentially input to the first scan signal input terminals S1 of the pixel driving circuits 300 of the j +1 th to nth pixel rows, and reset the pixel driving circuits 300; the third effective level signal of the ith pixel row and the second effective level signal of the (i + j) th pixel row are the same effective level signal.
After sequentially inputting a first effective level signal to the first scan signal input terminal S1 of the pixel driving circuit 300 of the 1 st to jth pixel rows and resetting the pixel driving circuit 300, sequentially inputting a third effective level signal to the second scan signal input terminal S2 of the pixel driving circuit 300 of the 1 st to nth pixel rows at an interval of j row times, and writing data into the pixel driving circuit 300;
the term "simultaneously" means that when the i-th scanning signal line 21 transmits the third active level signal, the i + j-th reset control signal line 22 also transmits the second active level signal. For example: a third active level signal is input to the second scanning signal input terminal S2 of the pixel driving circuit 300 of the first pixel row 11 by the third active level signal sent through the first scanning signal line 211, and data writing is performed to the pixel driving circuit 300 of the first pixel row 11; at the same time, the second active level signal transmitted through the fourth reset control signal line 22 inputs the second active level signal to the first scan signal input terminal S1 of the pixel driving circuit 300 of the fourth pixel row, and resets the pixel driving circuit 300 of the fourth pixel row.
It will be further appreciated that the scanning signal line 21 of the pixel drive circuit 300 transmits a signal at least j line times later than the signal transmitted by the reset control signal line 22 for the same row. The hysteresis effect caused by the drift of the threshold voltage of the driving transistor M in the 1 st to the nth pixel rows can be solved, the condition of nonuniform brightness during the switching of black and white pictures in the display process is solved, and the display effect of the display panel is improved; and multiple resets are not needed, so that the power consumption can be further reduced.
With continuing reference to fig. 3 and 4, the scan driving method provided by the present invention specifically includes:
reset phase T1: the first active level signal transmitted through the 1 st to jth reset control signal lines 22, that is, the low level signal transmitted through the 1 st to jth reset control signal lines 22 to the control terminal of the fourth transistor M4, sequentially turns on the control terminals of the fourth transistors M4 of the pixel driving circuits 300 in the 1 st to jth pixel rows, and resets the control terminal of the driving transistor M; the second active level signal transmitted through the j +1 th to nth reset control signal lines 22, that is, the low level signal transmitted through the j +1 th to nth reset control signal lines 22 to the control terminal of the fourth transistor M4, sequentially turns on the control terminal of the fourth transistor M4 of the pixel driving circuit 300 of the j +1 th to nth pixel rows, and resets the control terminal of the driving transistor M.
The first active level signal and the second active level signal are signals that can control the control terminal of the fourth transistor M4 to be turned on.
Data write phase T2: the third active level signals transmitted through the 1 st to nth scan signal lines 21, that is, the low level signals are transmitted through the 1 st to nth scan signal lines 21 to the control terminal of the second transistor M2 and the control terminal of the third transistor M3, the control terminals of the second transistor M2 and the third transistor M3 of the pixel driving circuit 300 of the 1 st to nth pixel rows are sequentially turned on, and data writing is performed on the pixel driving circuit 300.
The third active level signal is a signal that can control the control terminals of the second transistor M2 and the third transistor M3 to be turned on.
The scanning signal line 21 of the pixel driving circuit 300 transmits a signal at least j line times later than the signal transmitted from the reset control signal line 22 for the same row. That is, the start time of the data writing phase of the pixel driving circuit 300 for the same row is later than the start time of the reset phase by j row time.
Fig. 5 is a signal timing diagram of a driving method of the pixel driving circuit of fig. 4, and with continued reference to fig. 3 to 5, the driving method of the pixel driving circuit includes:
reset phase T1: the first active level signal S1 is sent to the control terminal of the fourth transistor M4 in the pixel driving circuit 300 through the reset control signal line 22, and controls the fourth transistor M4 to be turned on, so as to send the reference voltage Vref to the first node N1, initialize the driving transistor M through the first node N1, and reset the control terminal of the driving transistor M. Data write phase T2: the third active level signal S2 transmitted through the scan signal line 21 turns on the control terminal of the second transistor M2 and the control terminal of the third transistor M3 of the pixel driving circuit 300, and data writing is performed on the pixel driving circuit 300. The third active level signal is a low level signal, which controls the second transistor M2 and the third transistor M3 to be turned on, the first node N1 keeps a low level under the action of the storage capacitor Cst, which controls the driving transistor M to be turned on, and the data signal Vdata is transmitted to the first node N1 through the second transistor M2, the driving transistor M and the third transistor M3 in sequence, that is, data is written into the pixel driving circuit 300.
Wherein the start time of the data writing phase T2 of the pixel driving circuit 300 is later than the start time of the reset phase T1 by j row time. The start time of the data write phase T2 for pixel drive circuit 300 is later than the start time of the reset phase T1 by j row times. The hysteresis effect caused by the threshold voltage drift of the driving transistor M in the pixel driving circuit 300 can be solved, the condition of nonuniform brightness during the switching of black and white pictures in the display process is solved, and the display effect of the display panel is improved; multiple reset phases are not required, and power consumption can be further reduced.
Fig. 6 is still another display panel provided by the present invention, and with continued reference to fig. 3 to 6, the display panel 200 further includes 1 st to nth light emitting signal lines 23 extending along the first direction X and arranged along the second direction Y, and each signal line group 2 includes the light emitting signal line 23.
The present embodiment provides a scan driving method of a display panel, the scan driving method further including: the light-emitting period T3 is a period in which the control terminals of the first transistor M1 and the fifth transistor M5 of the pixel driving circuit 300 of the 1 st to nth pixel rows are sequentially turned on by the fourth active level signal transmitted by the 1 st to nth light-emitting signal lines 23 extending in the first direction X and arranged in the second direction Y, so as to control the driving transistor M to drive the light-emitting element O to emit light. The fourth active level signal is a low level signal, which controls the first transistor M1 and the fifth transistor M5 of the pixel driving circuit in the 1 st to nth pixel rows to be turned on, so that the driving transistor M generates a driving current to the light emitting element O, and the light emitting element emits light in response to the driving current.
In another embodiment, in the above embodiment of the driving method for a pixel driving circuit, the method further includes:
lighting phase T3: the fourth active level signal sent by the light-emitting signal line 23, that is, the low level signal sent by the light-emitting signal line 23 controls the first transistor M1 and the fifth transistor M5 to be turned on, at this time, the signals sent by the reset control signal line 22 and the scanning signal line 21 are both high level signals, that is, the sent signals are all inactive level signals, the second transistor M2, the fourth transistor M4 and the sixth transistor M6 are all in an off state, the voltage of the first end of the driving transistor M is the power supply voltage signal sent by the first power supply signal end, the voltage difference between the first end and the control end of the driving transistor M is the difference between the power supply voltage signal and the voltage signal of the first node N1, the driving transistor M generates a driving current, and the light-emitting element O can be driven to emit light by the driving current.
Fig. 7 is a further display panel provided by the present invention, and fig. 7 only illustrates the case where n is 8 and j is 3, and the 1 st to j-th reset control signal lines are simultaneously connected to the same signal output terminal, that is, the first to third reset control signal lines 22 are electrically connected to each other, so that signals can be simultaneously transmitted to the first to third pixel rows. After the first reset control signal line 221, the second reset control signal line 222, and the third reset control signal line 223 simultaneously transmit signals to the first to third pixel rows 1, signals are sequentially transmitted to the first to eighth pixel rows through the first scanning signal line 211, the second scanning signal line 212, and up to the eighth scanning signal line 218 at an interval of j rows. It can be understood that, because the reset control signal lines 22 in the 1 st to j-th pixel rows are connected to the same signal output end at the same time, it may be defined that, in the 1 st to j-th pixel rows, the signal sent to the scanning signal line 21 of the pixel driving circuit 300 in the same row is at least 3 line times later than the signal sent by the reset control signal line 22, but the interval between the start time of the signal sent by the reset control signal line 22 of the pixel in the same row and the start time of the signal sent to the scanning signal line 21 cannot exceed the line time of half the number of the total row 1 of the pixel rows in the display panel 200, and the specific value of the line time at the interval is not specifically defined in the present invention, and may be set according to the actual situation, and will not be described in detail below.
Further, the threshold voltage of the driving transistor of each pixel row can be maintained at a longer negative bias voltage, the hysteresis effect caused by the threshold voltage drift of the driving transistor in the pixel row is improved, and the display effect of the display panel is improved; meanwhile, the time length of the reset stage of the previous j rows of pixel rows can be saved, and the power consumption is reduced.
FIG. 8 is a timing diagram of signals for a driving method of the pixel driving circuits of the 1 st pixel row of the display panel of FIG. 7, and FIG. 9 is a timing diagram of signals for a driving method of the pixel driving circuits of the 2 nd pixel row of the display panel of FIG. 7; FIG. 10 is a timing diagram of the driving method of the pixel driving circuit of the 3 rd pixel row of the display panel of FIG. 7; in the 1 st to jth pixel rows of the display panel, the signal sent by the scanning signal line 21 of the pixel driving circuit 300 for the same row is at least 3 row time later than the signal sent by the reset control signal line 22. With continued reference to fig. 8-10, the present invention provides a method for driving a display panel, comprising
A first active level signal transmitted through the 1 st to jth reset control signal lines 22 while inputting the first active level signal to the first scan signal input terminal S1 of the pixel driving circuit 300 of the 1 st to jth pixel rows, and resetting the pixel driving circuit 300;
it can be understood that, since the 1 st to jth reset control signal lines are simultaneously connected to the same signal output terminal and simultaneously transmit signals to the first to third pixel rows, compared with the 1 st to jth reset control signal lines which are independently arranged and sequentially transmit signals to the first to third pixel rows, the driving method can be simplified and the reset time can be saved.
The third effective level signal is sequentially input to the second scanning signal input terminal S2 of the pixel driving circuit 300 of the 1 st to nth pixel rows through the third effective level signal sent from the 1 st to nth scanning signal line 21, and data is written to the pixel driving circuit 300; meanwhile, the second effective level signals transmitted through the j +1 th to nth reset control signal lines 22 are sequentially input to the first scan signal input terminals S1 of the pixel driving circuits 300 of the j +1 th to nth pixel rows, and reset the pixel driving circuits 300; the third effective level signal of the ith pixel row and the second effective level signal of the (i + j) th pixel row are the same effective level signal.
After a first effective level signal is simultaneously input to the first scanning signal input terminal S1 of the pixel driving circuit 300 of the 1 st to the jth pixel row and the pixel driving circuit 300 is reset, a third effective level signal is sequentially input to the second scanning signal input terminal S2 of the pixel driving circuit 300 of the 1 st to the nth pixel row 1 at an interval of f-1 row time, and data is written into the pixel driving circuit 300, wherein f is a positive integer greater than or equal to 2 and less than or equal to j;
the term "simultaneously" means that the i + j-th reset control signal line 22 transmits the second active level signal while the i-th scanning signal line 21 transmits the third active level signal. For example: a third active level signal is input to the second scanning signal input terminal S2 of the pixel driving circuit 300 of the first pixel row 11 by the third active level signal sent through the first scanning signal line 211, and data writing is performed to the pixel driving circuit 300 of the first pixel row 11; at the same time, the second active level signal transmitted through the fourth reset control signal line 22 inputs the second active level signal to the first scan signal input terminal S1 of the pixel driving circuits 300 of the fourth pixel row, and resets the pixel driving circuits 300 of the fourth pixel row 11.
It can be further understood that, for at least three line times before the signal sent by the scanning signal line 21, the signal sent by the reset control signal line 22 in the same pixel row from the 1 st to the nth pixel row maintains the longer negative bias voltage of the threshold voltage of the driving transistor in the pixel row, so that the hysteresis effect caused by the drift of the threshold voltage of the driving transistor M in the 1 st to nth pixel rows can be solved, the non-uniform brightness during the black-and-white image switching in the display process can be solved, and the display effect of the display panel can be improved; multiple reset phases are not required, and power consumption can be further reduced.
Continuing with fig. 5, 7-10. The signal timing diagram of the pixel driving circuit in fig. 5 is applicable to the pixel driving circuits of the pixels in the j +1 th row to the n th row in the display panel shown in fig. 7, and fig. 8, 9 and 10 only show the schematic diagrams of the pixel driving circuits 300 in the 1 st row to the j th row in the display panel shown in fig. 7, and the signal sent by the scanning signal line 21 of the pixel driving circuit 300 for the same row is at least 3 row time later than the signal sent by the reset control signal line 22. The driving method of the pixel driving circuit in this embodiment includes:
reset phase T1: the first active level signal sent through the 1 st to jth reset control signal lines 22 simultaneously turns on the control terminal of the fourth transistor M4 of the pixel driving circuit 300 of the 1 st to jth pixel rows and resets the control terminal of the driving transistor M; the second active level signal transmitted through the j +1 th to nth reset control signal lines 22 sequentially turns on the control terminal of the fourth transistor M4 of the pixel driving circuit 300 of the j +1 th to nth pixel rows and resets the control terminal of the driving transistor M. The first level valid signal is a low level signal, which controls the fourth transistor M4 of the pixel driving circuit 300 in the 1 st to jth pixel rows to be turned on, and then the reference voltage Vref is sent to the first node N1, so that the driving transistor M is initialized through the first node N1, and the control terminal of the driving transistor M is reset. The second level signal is a low level signal, which controls the fourth transistor M4 of the pixel driving circuit 300 in the j +1 th to nth pixel rows to be turned on, so that the reference voltage Vref is sent to the first node N1, and the driving transistor M is initialized through the first node N1, so as to reset the control terminal of the driving transistor M.
Data write phase T2: the third active level signal transmitted through the 1 st to nth scan signal lines 21 sequentially turns on the control terminal of the second transistor M2 and the control terminal of the third transistor M3 of the pixel driving circuit 300 of the 1 st to nth pixel rows, and writes data to the pixel driving circuit 300. The third active level signal is a low level signal, which controls the second transistor M2 and the third transistor M3 of the pixel driving circuit in the 1 st to nth pixel rows to turn on, the first node N1 controls the driving transistor M to turn on under the action of the storage capacitor Cst, and the data signal Vdata sequentially passes through the second transistor M2, the driving transistor M, the third transistor M3 and the first node N1, i.e., data is written into the pixel driving circuit 300.
In this embodiment, the driving method of the pixel driving circuit is explained by taking j-3 as an example;
the start time of the data writing phase for the pixel driving circuits in the 1 st pixel row is 3 row time later than the start time of the reset phase.
The start time of the data write phase for the pixel drive circuits in the 2 nd row of pixels is 4 row time later than the start time of the reset phase.
The start time of the data write phase for the pixel drive circuits in the 3 rd pixel row is 5 row time later than the start time of the reset phase. The start time of the data writing phase for the pixel driving circuits in the 4 th pixel row is 3 row time later than the start time of the reset phase; that is, the start time of the data writing phase of the pixel driving circuit for the same one of the j +1 th to n-th pixel rows is later than the start time of the reset phase by j row time.
It can be understood that, by the above scan driving method, referring to fig. 8, fig. 8 is a timing diagram of the driving circuit of the pixels of the first pixel row, the start time of the data writing phase of the first pixel row is later than the start time of the reset phase by 3 row time, referring to fig. 9, fig. 9 is a timing diagram of the driving circuit of the pixels of the second pixel row, the start time of the data writing phase of the second pixel row is later than the start time of the reset phase by 4 row time, referring to fig. 10, fig. 10 is a timing diagram of the pixels of the third pixel row, the start time of the data writing phase of the third pixel row is later than the start time of the reset phase by 5 row time; referring to fig. 5, the start time of the fourth to eighth pixel line data writing phases is 3 line row time later than the start time of the reset phase. In short, the starting time of the data writing phase of the pixel driving circuit in the same row from the j +1 th pixel row to the n th pixel row is later than the starting time of the reset phase by the row time of j, so that the threshold voltage of the driving transistor in the pixel row is kept at a longer negative bias, the hysteresis effect caused by the drift of the threshold voltage of the driving transistor M in the 1 st pixel row to the n th pixel row can be further solved, the condition of nonuniform brightness during the switching of black and white pictures in the display process is solved, and the display effect of the display panel is improved; multiple reset phases are not required, and power consumption can be further reduced. With continued reference to fig. 3, the scanning signal line 21 in the ith signal line group in the display panel 200 is electrically connected to the reset control signal line 22 in the (i + j) th signal line group, n and i are both positive integers, j is a positive integer greater than or equal to 3, and i + j is less than or equal to n; the 1 st to jth reset control signal lines 22 are not electrically connected to the scanning signal line 21. Wherein j is less than or equal to 0.5 n.
It can be understood that the row time of the reset control signal line 22 for setting the same pixel row to send a signal earlier than the row time of the scanning signal line 21 sending signal interval is more than 3 row times, i.e. the limitation j is a positive integer which is more than or equal to 3, and the display effect of the display panel can be effectively improved. In addition, the duration of the reset phase T1 and the duration of the data write phase T2 may cause the duration of the light-emitting phase T3 of the display panel to be relatively reduced, and the duration of the reset phase T1 and the duration of the data write phase T2 need to be limited, otherwise, the display image may flicker, and the display effect may be further affected. That is, it is necessary to set a line time in which the interval between the start time of signal transmission to the reset control signal lines 22 of the pixels in the same row and the start time of signal transmission to the scanning signal lines 21 cannot exceed half the number of rows of the total pixel rows 1 in the display panel 200. Therefore, 3 < j < 0.5n can effectively improve the hysteresis effect caused by the threshold voltage drift of the driving transistor and avoid the problem of flicker of a display picture, thereby further improving the display effect of the display panel.
Fig. 11 is a schematic diagram of another display panel provided by the present invention, the display panel 200 further includes a non-display area BB surrounding the display area AA, the non-display area BB includes a first gate driving circuit 41, the scanning signal line 21 is electrically connected to the first gate driving circuit 41, and the j +1 th to n-th reset control signal lines 22 are electrically connected to the first gate driving circuit 41;
the non-display region further includes a second gate driving circuit 42, the second gate driving circuit 42 is located in the non-display region BB, and the 1 st to jth reset control signal lines 22 are electrically connected to the second gate driving circuit 42.
It can be understood that, since the scanning signal line 21 in the i-th signal line group is electrically connected to the reset control signal line 22 in the i + j-th signal line group, the scanning signal line 21 in the i-th signal line group and the reset control signal line 22 in the i + j-th signal line group transmit the same signal, so that the scanning signal line 21 in the i-th signal line group and the reset control signal line 22 in the i + j-th signal line group can be electrically connected to the same first gate driving circuit 41, which is beneficial to reducing the area of the non-display area BB of the display panel 200.
With continued reference to fig. 11, the method for driving the display panel further includes sending a third active level signal to the scan signal line 21 and sending a second active level signal to the j +1 th to n-th reset control signal lines 22 through the first gate driving circuit 41.
The third active level signal is sent to the scanning signal line 21 through the first gate driving circuit 41, that is, the low level signal is sent to the scanning signal line 21, the control terminal of the second transistor M2 and the control terminal of the third transistor M3 of the pixel driving circuit 300 of the 1 st to nth pixel rows are turned on, and data writing is performed on the pixel driving circuit 300. Sending the second active level signal to the j +1 th to nth reset control signal lines 22, that is, sending the low level signal to the j +1 th to nth reset control signal lines 22 through the first gate driving circuit 41, turning on the control terminal of the fourth transistor M4 of the pixel driving circuit 300 in the j +1 th to nth pixel rows, and resetting the control terminal of the driving transistor M.
With continued reference to fig. 11, the method for driving the display panel further includes sending the first active level signal to the 1 st to jth reset control signal lines 22 through the second gate driving circuit 42. That is, a low potential signal is transmitted to the 1 st to jth reset control signal lines 22, the control terminal of the fourth transistor M4 of the pixel driving circuit 300 in the 1 st to jth pixel rows is controlled, and the control terminal of the driving transistor M is reset.
Fig. 12 shows another display panel provided by the present invention, in which the non-display area BB of the display panel 200 further includes a third gate driving circuit 43, the signal line group 2 in the display area AA further includes a light-emitting signal line 23, and the light-emitting signal line 23 is electrically connected to the third gate driving circuit 43.
The present embodiment provides a scan driving method of a display panel, including: the fourth active level signal is sent to the 1 st to nth light emitting signal lines 23 through the third gate driving circuit 43. That is, the third gate driving circuit 43 sends a low signal to the 1 st to nth light emitting signal lines 23, and the control terminals of the first transistor M1 and the fifth transistor M5 of the pixel driving circuit 300 of the 1 st to nth pixel rows are sequentially turned on, so that the driving transistor M is controlled to drive the light emitting element O to emit light.
With continued reference to fig. 3, the scan signal lines 21 and the reset control signal lines 22 of two adjacent signal line groups 2 in the display panel 200 are disposed adjacent to each other. That is, the scan signal lines 21 and the reset control signal lines 22 in the display panel are alternately arranged, the circuit routing arrangement of the display panel can be simplified.
Note that, all the transistors used in the embodiments of the present invention are P-type transistors, but the present invention is not limited thereto, and N-type transistors may be used in all the transistors, or a mixture of P-type transistors and N-type transistors may be used in the present invention. And thus the type of each transistor is not limited.
As can be seen from the foregoing embodiments, the display panel and the scan driving method thereof provided by the present invention at least achieve the following beneficial effects:
the invention discloses a display panel and a scanning driving method thereof.A first effective level signal is sent by 1 st to jth reset control signal lines, and simultaneously, the first effective level signal is input to a first scanning signal input end of a pixel driving circuit of 1 st to jth pixel rows and resets the pixel driving circuit; inputting a third effective level signal to a second scanning signal input end of the pixel driving circuit of the 1 st to nth pixel rows in sequence or simultaneously through a third effective level signal sent by the 1 st to nth scanning signal lines, and writing data into the pixel driving circuit; simultaneously, second effective level signals sent by the j +1 th to the nth reset control signal lines are sequentially input to the first scanning signal input ends of the pixel driving circuits of the j +1 th to nth pixel rows, and the pixel driving circuits are reset; the third effective level signal of the ith pixel row and the second effective level signal of the (i + j) th pixel row are the same effective level signal. The display panel and the scanning driving method thereof increase the holding time of the low voltage after reset, prolong the time from reset to data writing to be more than 3 times of line time, namely the time interval of the reset time before the data writing time is more than or equal to 3 line times, and can reduce the power consumption caused by reset while improving the hysteresis characteristic of the driving transistor.
Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims (16)

1. A display panel, comprising:
a display area;
the display area comprises a plurality of sub-pixels which are arranged in an array mode, and the sub-pixels are arranged along a first direction to form a pixel row;
the pixel array further comprises n signal line groups arranged along a second direction, each signal line group comprises scanning signal lines extending along the first direction and reset control signal lines extending along the first direction, and the signal line groups correspond to the pixel rows one to one;
the scanning signal line in the ith signal line group is electrically connected with the reset control signal line in the ith + j signal line group, n and i are both positive integers, j is a positive integer greater than or equal to 3, and i + j is less than or equal to n;
the 1 st to jth reset control signal lines are not electrically connected with the scanning signal line;
the first direction intersects the second direction.
2. The display panel according to claim 1, wherein the 1 st to jth reset control signal lines are simultaneously connected to the same signal output terminal.
3. The display panel of claim 1, wherein 3 < j < 0.5 n.
4. The display panel according to claim 1, further comprising a non-display region surrounding the display region, the non-display region including a first gate driver circuit, the scan signal line being electrically connected to the first gate driver circuit, and j +1 th to n-th reset control signal lines being electrically connected to the first gate driver circuit;
the non-display area further comprises a second grid driving circuit, the second grid driving circuit is located in the non-display area, and the 1 st to the jth reset control signal lines are electrically connected with the second grid driving circuit.
5. The display panel according to claim 1, further comprising a pixel drive circuit, the pixel drive circuit comprising:
the control end of the first transistor is electrically connected with the light-emitting signal input end, the first end of the first transistor is electrically connected with the first power signal end, and the second end of the first transistor is electrically connected with the first end of the driving transistor;
a control end of the second transistor is electrically connected with the second scanning signal input end, a first end of the second transistor is electrically connected with the data signal input end, and a second end of the second transistor is electrically connected with the first end of the driving transistor;
a control end of the driving transistor is electrically connected with a second end of the fourth transistor, and a first end of the driving transistor is electrically connected with a second end of the first transistor and a second end of the second transistor;
a third transistor, a control terminal of which is electrically connected to the second scan signal input terminal, a first terminal of which is electrically connected to the second terminal of the fourth transistor and the second terminal of the storage capacitor, and a second terminal of which is electrically connected to the second terminal of the driving transistor and the first terminal of the fifth transistor;
a control end of the fourth transistor is electrically connected with the first scanning signal input end, a first end of the fourth transistor is electrically connected with the reference voltage signal input end, and a second end of the fourth transistor is electrically connected with the control end of the driving transistor;
a fifth transistor having a control terminal electrically connected to the light-emission signal input terminal, a first terminal electrically connected to the second terminal of the driving transistor and the second terminal of the third transistor, and a second terminal electrically connected to an anode of the light-emitting element;
a sixth transistor having a control terminal electrically connected to the second scan signal input terminal, a first terminal electrically connected to the reference voltage signal input terminal, and a second terminal electrically connected to the first terminal of the light emitting element;
a first end of the light-emitting element is electrically connected with a second end of the fifth transistor and a second end of the sixth transistor, and a second end of the light-emitting element is electrically connected with a second power signal end;
and a first end of the storage capacitor is electrically connected with the first power signal end, and a second end of the storage capacitor is electrically connected with the control end of the driving transistor, the first end of the third transistor and the second end of the fourth transistor.
6. The display panel according to claim 5, wherein the scan signal line is electrically connected to a control terminal of the second transistor and a control terminal of the third transistor;
the reset control signal line is electrically connected with the control end of the fourth transistor.
7. The display panel according to claim 1, wherein the scan signal line and the reset control signal line of two adjacent signal line groups are disposed adjacent to each other.
8. A scan driving method of a display panel, the display panel comprising:
a display area;
the display area comprises a plurality of sub-pixels which are arranged in an array mode, and the sub-pixels are arranged along a first direction to form a pixel row;
the pixel array further comprises n signal line groups arranged along a second direction, each signal line group comprises scanning signal lines extending along the first direction and reset control signal lines extending along the first direction, and the signal line groups correspond to the pixel rows one to one;
the scanning signal line in the ith signal line group is electrically connected with the reset control signal line in the ith + j signal line group, n and i are both positive integers, j is a positive integer greater than or equal to 3, and i + j is less than or equal to n;
the 1 st to the jth reset control signal lines are not electrically connected with the scanning signal line;
the first direction intersects the second direction;
each sub-pixel comprises a pixel driving circuit;
the scan driving method includes:
inputting a first effective level signal to a first scanning signal input end of the pixel driving circuit of the 1 st to the jth pixel rows in sequence through the first effective level signal sent by the 1 st to the jth reset control signal line, and resetting the pixel driving circuit; inputting a third effective level signal to a second scanning signal input end of the pixel driving circuit of the 1 st to nth pixel rows in sequence through the third effective level signal sent by the 1 st to nth scanning signal lines, and writing data into the pixel driving circuit; simultaneously, second effective level signals sent by the j +1 th to the nth reset control signal lines are sequentially input to the first scanning signal input ends of the pixel driving circuits of the j +1 th to nth pixel rows, and the pixel driving circuits are reset;
the third effective level signal of the ith pixel row and the second effective level signal of the (i + j) th pixel row are the same effective level signal.
9. The scan driving method of a display panel according to claim 8, wherein the pixel driving circuit comprises:
the control end of the first transistor is electrically connected with the light-emitting signal input end, the first end of the first transistor is electrically connected with the first power signal end, and the second end of the first transistor is electrically connected with the first end of the driving transistor;
a control end of the second transistor is electrically connected with the second scanning signal input end, a first end of the second transistor is electrically connected with the data signal input end, and a second end of the second transistor is electrically connected with the first end of the driving transistor;
a control end of the driving transistor is electrically connected with a second end of the fourth transistor, and a first end of the driving transistor is electrically connected with a second end of the first transistor and a second end of the second transistor;
a third transistor, a control terminal of which is electrically connected to the second scan signal input terminal, a first terminal of which is electrically connected to the second terminal of the fourth transistor and the second terminal of the storage capacitor, and a second terminal of which is electrically connected to the second terminal of the driving transistor and the first terminal of the fifth transistor;
a control end of the fourth transistor is electrically connected with the first scanning signal input end, a first end of the fourth transistor is electrically connected with the reference voltage signal input end, and a second end of the fourth transistor is electrically connected with the control end of the driving transistor;
a fifth transistor having a control terminal electrically connected to the light-emission signal input terminal, a first terminal electrically connected to the second terminal of the driving transistor and the second terminal of the third transistor, and a second terminal electrically connected to an anode of the light-emitting element;
a sixth transistor having a control terminal electrically connected to the second scan signal input terminal, a first terminal electrically connected to the reference voltage signal input terminal, and a second terminal electrically connected to the first terminal of the light emitting element;
a first end of the light-emitting element is electrically connected with a second end of the fifth transistor and a second end of the sixth transistor, and a second end of the light-emitting element is electrically connected with a second power signal end;
a first end of the storage capacitor is electrically connected with the first power supply signal end, and a second end of the storage capacitor is electrically connected with a control end of the driving transistor, a first end of the third transistor and a second end of the fourth transistor;
the scanning driving method comprises the following steps:
a reset stage: sequentially turning on the control ends of the fourth transistors M4 of the 1 st to jth pixel rows through a first effective level signal sent by the 1 st to jth reset control signal lines, and resetting the control ends of the driving transistors; sequentially turning on the control ends of the fourth transistors of the j +1 th to nth pixel rows through second effective level signals sent by the j +1 th to nth reset control signal lines, and resetting the control ends of the driving transistors;
a data writing stage: sequentially turning on the control end of the second transistor and the control end of the third transistor of the pixel driving circuit of the 1 st to nth pixel rows through a third effective level signal sent by the 1 st to nth scanning signal lines, and writing data into the pixel driving circuit;
the starting time of the data writing phase of the pixel driving circuit for the same row is later than the starting time of the reset phase, and the starting time is j rows of row time.
10. The scan driving method of a display panel according to claim 9, further comprising:
and a light-emitting stage, in which the control ends of the first transistor and the fifth transistor of the pixel driving circuit of the 1 st to nth pixel rows are sequentially turned on by a fourth active level signal sent by the 1 st to nth light-emitting signal lines extending along the first direction and arranged along the second direction, so as to control the driving transistor to drive the light-emitting element to emit light.
11. The scan driving method of a display panel according to claim 10, wherein the display panel further includes a non-display region surrounding the display region;
the non-display area comprises a first grid driving circuit, the first grid driving circuit sends the third effective level signal to the scanning signal line, and sends the second effective level signal to the j +1 th to the n th reset control signal lines.
12. The scan driving method of a display panel according to claim 11, wherein the non-display region includes a third gate driver circuit, and the fourth active level signal is sent to the 1 st to nth light emitting signal lines through the third gate driver circuit.
13. The scan driving method of a display panel according to claim 11, wherein the non-display region includes a second gate driving circuit, and the first active level signal is transmitted to the 1 st to jth reset control signal lines through the second gate driving circuit.
14. A scan driving method of a display panel, the display panel comprising:
a display area;
the display area comprises a plurality of sub-pixels which are arranged in an array mode, and the sub-pixels are arranged along a first direction to form a pixel row;
the pixel array further comprises n signal line groups arranged along a second direction, each signal line group comprises scanning signal lines extending along the first direction and reset control signal lines extending along the first direction, and the signal line groups correspond to the pixel rows one to one;
the scanning signal line in the ith signal line group is electrically connected with the reset control signal line in the ith + j signal line group, n and i are both positive integers, j is a positive integer greater than or equal to 3, and i + j is less than or equal to n;
the 1 st to the jth reset control signal lines are not electrically connected with the scanning signal line;
the first direction intersects the second direction;
each sub-pixel comprises a pixel driving circuit;
the scan driving method includes:
a first effective level signal is sent through the 1 st to the jth reset control signal lines, and the first effective level signal is simultaneously input to the first scanning signal input ends of the pixel driving circuits of the 1 st to the jth pixel rows and resets the pixel driving circuits; inputting a third effective level signal to a second scanning signal input end of the pixel driving circuit of the 1 st to nth pixel rows in sequence through the third effective level signal sent by the 1 st to nth scanning signal lines, and writing data into the pixel driving circuit; simultaneously, second effective level signals sent by the j +1 th to the nth reset control signal lines are sequentially input to the first scanning signal input ends of the pixel driving circuits of the j +1 th to nth pixel rows, and the pixel driving circuits are reset;
the third effective level signal of the ith pixel row and the second effective level signal of the (i + j) th pixel row are the same effective level signal.
15. The scan driving method of a display panel according to claim 14, wherein the pixel driving circuit comprises:
after the pixel driving circuits of the 1 st to the jth pixel rows are reset, the third effective level signals are sequentially input to the second scanning signal input ends of the pixel driving circuits of the 1 st to the nth pixel rows at intervals of j-1 row time through the third effective level signals sent by the 1 st to the nth scanning signal lines.
16. The scan driving method of a display panel according to claim 14, wherein the pixel driving circuit comprises:
the control end of the first transistor is electrically connected with the light-emitting signal input end, the first end of the first transistor is electrically connected with the first power signal end, and the second end of the first transistor is electrically connected with the first end of the driving transistor;
a control end of the second transistor is electrically connected with the second scanning signal input end, a first end of the second transistor is electrically connected with the data signal input end, and a second end of the second transistor is electrically connected with the first end of the driving transistor;
a control end of the driving transistor is electrically connected with a second end of the fourth transistor, and a first end of the driving transistor is electrically connected with a second end of the first transistor and a second end of the second transistor;
a third transistor, a control terminal of which is electrically connected to the second scan signal input terminal, a first terminal of which is electrically connected to the second terminal of the fourth transistor and the second terminal of the storage capacitor, and a second terminal of which is electrically connected to the second terminal of the driving transistor and the first terminal of the fifth transistor;
a control end of the fourth transistor is electrically connected with the first scanning signal input end, a first end of the fourth transistor is electrically connected with the reference voltage signal input end, and a second end of the fourth transistor is electrically connected with the control end of the driving transistor;
a fifth transistor having a control terminal electrically connected to the light-emission signal input terminal, a first terminal electrically connected to the second terminal of the driving transistor and the second terminal of the third transistor, and a second terminal electrically connected to an anode of the light-emitting element;
a sixth transistor having a control terminal electrically connected to the second scan signal input terminal, a first terminal electrically connected to the reference voltage signal input terminal, and a second terminal electrically connected to the first terminal of the light emitting element;
a first end of the light-emitting element is electrically connected with a second end of the fifth transistor and a second end of the sixth transistor, and a second end of the light-emitting element is electrically connected with a second power signal end;
a first end of the storage capacitor is electrically connected with the first power supply signal end, and a second end of the storage capacitor is electrically connected with a control end of the driving transistor, a first end of the third transistor and a second end of the fourth transistor;
the scanning driving method comprises the following steps:
a reset stage: a first effective level signal is sent through the 1 st to the jth reset control signal lines, and meanwhile, the control end of the fourth transistor of the pixel driving circuit in the 1 st to the jth pixel rows is started, and the control end of the driving transistor is reset; sequentially turning on the control ends of the fourth transistors of the pixel driving circuits of the j +1 th to nth pixel rows through second effective level signals sent by the j +1 th to nth reset control signal lines, and resetting the control ends of the driving transistors;
a data writing stage: sequentially turning on the control end of the second transistor and the control end of the third transistor of the pixel driving circuit of the 1 st to nth pixel rows through a third effective level signal sent by the 1 st to nth scanning signal lines, and writing data into the pixel driving circuit;
the starting time of the data writing phase of the pixel driving circuit for the same row from the j +1 th pixel row to the n th pixel row is later than the starting time of the reset phase by j row time.
CN202010348250.XA 2020-04-28 2020-04-28 Display panel and scanning driving method thereof Active CN111369949B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010348250.XA CN111369949B (en) 2020-04-28 2020-04-28 Display panel and scanning driving method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010348250.XA CN111369949B (en) 2020-04-28 2020-04-28 Display panel and scanning driving method thereof

Publications (2)

Publication Number Publication Date
CN111369949A CN111369949A (en) 2020-07-03
CN111369949B true CN111369949B (en) 2021-04-02

Family

ID=71211106

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010348250.XA Active CN111369949B (en) 2020-04-28 2020-04-28 Display panel and scanning driving method thereof

Country Status (1)

Country Link
CN (1) CN111369949B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114863875B (en) * 2022-05-25 2023-05-05 武汉天马微电子有限公司 Display panel, driving method thereof and display device

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101847360A (en) * 2009-03-25 2010-09-29 索尼公司 Display device and electronic device
CN102959609A (en) * 2010-09-06 2013-03-06 松下电器产业株式会社 Display device and control method therefor
CN104332138A (en) * 2014-12-02 2015-02-04 京东方科技集团股份有限公司 Pixel driving circuit, display device and pixel driving method
CN105938698A (en) * 2015-03-04 2016-09-14 三星显示有限公司 Display panel and method of testing the same
CN106469547A (en) * 2015-08-21 2017-03-01 三星显示有限公司 Demultiplexer, display device and the method for driving this display device
CN106887216A (en) * 2017-03-09 2017-06-23 京东方科技集团股份有限公司 The driving method of gate driving circuit, display panel and gate driving circuit
CN107342044A (en) * 2017-08-15 2017-11-10 上海天马有机发光显示技术有限公司 The driving method of image element circuit, display panel and image element circuit
CN107452339A (en) * 2017-07-31 2017-12-08 上海天马有机发光显示技术有限公司 Image element circuit, its driving method, organic electroluminescence display panel and display device
CN107680537A (en) * 2017-11-21 2018-02-09 上海天马微电子有限公司 A kind of driving method of image element circuit
CN110718193A (en) * 2019-10-28 2020-01-21 合肥京东方卓印科技有限公司 Display panel, driving method thereof and display device
CN111028811A (en) * 2019-12-25 2020-04-17 厦门天马微电子有限公司 Display panel and display device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015125366A (en) * 2013-12-27 2015-07-06 株式会社ジャパンディスプレイ Display device

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101847360A (en) * 2009-03-25 2010-09-29 索尼公司 Display device and electronic device
CN102959609A (en) * 2010-09-06 2013-03-06 松下电器产业株式会社 Display device and control method therefor
CN104332138A (en) * 2014-12-02 2015-02-04 京东方科技集团股份有限公司 Pixel driving circuit, display device and pixel driving method
CN105938698A (en) * 2015-03-04 2016-09-14 三星显示有限公司 Display panel and method of testing the same
CN106469547A (en) * 2015-08-21 2017-03-01 三星显示有限公司 Demultiplexer, display device and the method for driving this display device
CN106887216A (en) * 2017-03-09 2017-06-23 京东方科技集团股份有限公司 The driving method of gate driving circuit, display panel and gate driving circuit
CN107452339A (en) * 2017-07-31 2017-12-08 上海天马有机发光显示技术有限公司 Image element circuit, its driving method, organic electroluminescence display panel and display device
CN107342044A (en) * 2017-08-15 2017-11-10 上海天马有机发光显示技术有限公司 The driving method of image element circuit, display panel and image element circuit
CN107680537A (en) * 2017-11-21 2018-02-09 上海天马微电子有限公司 A kind of driving method of image element circuit
CN110718193A (en) * 2019-10-28 2020-01-21 合肥京东方卓印科技有限公司 Display panel, driving method thereof and display device
CN111028811A (en) * 2019-12-25 2020-04-17 厦门天马微电子有限公司 Display panel and display device

Also Published As

Publication number Publication date
CN111369949A (en) 2020-07-03

Similar Documents

Publication Publication Date Title
CN109036279B (en) Array substrate, driving method, organic light emitting display panel and display device
CN110223636B (en) Pixel driving circuit, driving method thereof and display device
US20240119897A1 (en) Pixel Circuit and Driving Method Therefor and Display Panel
US11069298B2 (en) Driving circuit, display panel, driving method and display device
KR100962768B1 (en) Display apparatus and drive control method thereof
CN108492783B (en) Pixel driving circuit of AMOLED display device and driving method of AMOLED display device
CN110634446B (en) Pixel and organic light emitting display device including the same
US11600225B2 (en) Display panel and driving method
CN113950715B (en) Pixel circuit, driving method thereof and display device
CN113192463B (en) Light emitting control shift register, gate driving circuit, display device and method
KR20170105683A (en) Scan driver and display apparatus having the same
KR20040019207A (en) Organic electro-luminescence device and apparatus and method driving the same
CN110189691B (en) Pixel driving circuit and display panel
US11663955B2 (en) Pixel circuit, drive method thereof, display substrate, and display device
WO2020001037A1 (en) Array substrate, driving method therefor, and display panel
CN113707090A (en) Driving method of pixel driving circuit, display panel and display device
CN112289269A (en) Pixel circuit, control method thereof and display panel
KR20190048736A (en) Organic light emitting display device and method for driving the same
CN111179849A (en) Control unit, control circuit, display device and control method thereof
WO2019085119A1 (en) Oled pixel driving circuit, oled display panel, and driving method
US20220036791A1 (en) Driving method of display panel and display device
CN111369949B (en) Display panel and scanning driving method thereof
CN110675826A (en) Display panel, driving method thereof and display device
US11626079B2 (en) Display device and method for driving the same
US11361705B2 (en) Display device having interlaced scan signals

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20211025

Address after: No.8, liufangyuanheng Road, Donghu New Technology Development Zone, Wuhan City, Hubei Province, 430074

Patentee after: WUHAN TIANMA MICRO-ELECTRONICS Co.,Ltd.

Patentee after: Wuhan Tianma Microelectronics Co.,Ltd. Shanghai Branch

Address before: Room 509, building 1, No. 6111, Longdong Avenue, Pudong New Area, Shanghai, 201201

Patentee before: SHANGHAI TIANMA AM-OLED Co.,Ltd.