CN111368513A - Method for converting XDL circuit netlist file into directed hypergraph - Google Patents
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Abstract
A method for converting XDL circuit netlist file to directed hypergraph includes using mathematical model of directed hypergraph to construct forward topological relation between signals of XDL circuit netlist, representing effective pins of each circuit unit as hypergraph nodes in directed hypergraph, representing external connection between circuit pins and circuit logic function in circuit pins as directed hypergraph edge in hypergraph. Each directed super edge can be connected with more than two nodes, and corresponding to the connection between circuit units, more than two effective pins can be connected, or the circuit logic function can be connected with multiple input pins. The invention provides a more accurate model for the XDL circuit netlist by adopting the directed hypergraph, and can be used for accurately analyzing the single-particle soft error sensitivity of the SRAM type FPGA device.
Description
Technical Field
The invention relates to a mathematical modeling method of a forward topological relation between signals of an XDL circuit netlist, in particular to a method for converting an XDL circuit netlist file into a directed hypergraph.
Background
Xdl (Xilinx Design language) is a featured physical Design language provided by Xilinx corporation for describing internal structure information of FPGA Design, and describes a netlist-level circuit of FPGA implementing a specific function hardware Design by using BNF bacco paradigm, wherein configuration information of logic resources and interconnection information of routing resources are included. The development full flow from hardware design to FPGA configuration flow can be realized through a synthesis tool xst based on the ISE suite of Xilinx corporation, a translation tool ngdbuild, a mapping tool map, a layout tool par (-r), a wiring tool par (-p), a configuration flow tool bitgen and a netlist conversion tool xdl. In the development process, the NCD netlist files after FPGA mapping, placement and routing are computer-oriented binary format netlist files, which are not convenient for people to understand and analyze, and need to be converted into XDL text format netlist files by means of the netlist conversion tool XDL. Each XDL netlist level circuit description file corresponds to the hardware implementation of one FPGA design, and the basic information and the layout and wiring information of the whole FPGA design are described in detail by using a BNF (binary tree format) paradigm, and comprise design, module, instance, net and other statements.
As the manufacturing process of very large scale integrated circuits (VLSI) enters the nanometer process era from the deep submicron process era, the noise margin of Field Programmable Gate Arrays (FPGAs) is decreasing increasingly, the noise interference and radiation of high energy particles are becoming more sensitive, and the Soft Error Rate (SER) is increasing exponentially. Configuration words of Static Random Access Memory (SRAM) type FPGA logic resources and wiring resources account for about 95% -99% of SRAM units, and are easily interfered by high-energy particle radiation and circuit internal noise, so that not only can soft errors of the FPGA logic resource configuration words change the logic functions of circuits of the FPGA logic resources, but also the soft errors of the FPGA wiring resource configuration words can change the structures of the circuits of the FPGA logic resources and the wiring resources.
The invention constructs a signal propagation model of a netlist-level circuit based on an XDL circuit netlist of an SRAM (static random Access memory) type FPGA (field programmable Gate array) device, analyzes a forward topological relation between signals facing the XDL netlist-level circuit and converts the signals into a directed hypergraph. Therefore, the method can be used for accurately analyzing the single-particle soft error sensitivity of the SRAM type FPGA device and improving the fault-tolerant reliability calculation accuracy of the SRAM type FPGA device, thereby better reflecting the propagation characteristic of the single-particle soft error in the SRAM type FPGA device.
Disclosure of Invention
The invention aims to provide a method for converting an XDL circuit netlist file into a directed hypergraph aiming at the defects in the prior art, and provides a propagation model of a forward topological relation between XDL netlist level circuit signals for accurately analyzing the single-particle soft error sensitivity of an SRAM type FPGA device. In order to achieve the above purpose, the idea of the invention is as follows: and (3) performing mathematical modeling on the XDL circuit netlist by adopting the directed hypergraph, converting the XDL circuit network into the directed hypergraph, and storing the directed hypergraph as a directed hypergraph file. The effective pins of each circuit unit are represented as nodes of the directed hypergraph, external connecting lines among the circuit pins and circuit logic functions in the circuit pins are represented as directed hyper edges in the hypergraph, each directed hyper edge can be connected with more than two nodes, the connecting lines corresponding to the circuit units can be connected with more than two effective pins, or the circuit logic functions can be connected with multiple input pins. In each directed super edge, the only output pin corresponds to the tail end node of the directed super edge, and the other input pins correspond to the directed super edge source terminal aggregation points.
According to the inventive concept, the technical scheme of the invention is realized as follows: a method for converting an XDL circuit netlist file into a directed hypergraph is characterized by comprising the following specific steps.
And 2, analyzing the syntax of the XDL circuit netlist file, decomposing a word sequence into various syntax phrases on the basis of lexical analysis, and determining whether the whole character stream forms a grammatically correct structure description file or not according to the syntax rule of the netlist file.
And 3, performing semantic analysis on the XDL circuit netlist file, checking whether semantic errors exist in the source code on the basis of the syntactic analysis, and collecting type information for the intermediate code generation stage.
And 4, generating an intermediate code of the XDL circuit netlist file, generating the intermediate code of the source code on the basis of syntactic analysis and semantic analysis, and expressing the intermediate code by using an internal intermediate format.
And 5, extracting Inst and Net module information of the XDL circuit netlist file, and generating Inst and Net module information of the XDL circuit netlist file based on the internal intermediate format.
And 6, generating a directed hypergraph file, extracting logic configuration information of the XDL circuit netlist from the Ins module information, extracting interconnection configuration information of the XDL circuit netlist from the Net module information, further constructing a complete circuit network based on the logic configuration information and the interconnection configuration information, converting the circuit network into a directed hypergraph and storing the directed hypergraph file.
And 7, reading the directed hypergraph file, and storing the directed hypergraph by adopting an improved compressed storage format.
In the above step 6, the step of generating the directed hypergraph file is as follows.
And 6.1, traversing Inst circuit unit module information of the circuit netlist, sequentially processing each Inst circuit unit module, extracting logic configuration information of the XDL circuit netlist, and generating a hypergraph node and a directed hypergraph edge.
And 6.2, traversing Net circuit signal module information of the circuit netlist, sequentially processing each Net circuit signal module, extracting interconnection configuration information of the XDL circuit netlist, and generating a directed over edge.
Step 6.3, traversing each hyper-graph node and directed hyper-edge of the directed hyper-graph, numbering each hyper-graph node independently, and i is the number of the hyper-graph node in the directed hyper-graph; and j is the number of the directed super edge in the directed super graph.
And 6.4, storing each numbered hyper-graph node and each numbered directed hyper-graph edge as a directed hyper-graph file.
In step 6.1 above, the steps described for processing each Inst circuit cell module are as follows.
Step 6.1.1, the SITEDEF type information of the Inst circuit unit module is read.
And 6.1.2, reading the CFG configuration information of the Inst circuit unit module, and acquiring an effective pin information list.
And 6.1.3, generating a hypergraph node for each effective pin of the Inst circuit unit module.
And 6.1.4, analyzing the logic function expression of each output pin according to different SITEDEF types of the Inst circuit unit and by combining the configuration state of the bottom layer circuit acquired by the CFG configuration information.
Step 6.1.5, generating a directed super edge for each output pin, wherein the tail end node of the directed super edge is the corresponding hyper graph node of the output pin; and adding the hypergraph nodes corresponding to the input pins into the source terminal set of the directed hypergraph according to the logic function expression of the output pins.
In the above step 6.2, the step of processing each Net circuit signal module is as follows.
And 6.2.1, generating a directed super edge for the Net circuit signal module.
And 6.2.2, reading INPUT end point information of the Net circuit signal module, and finding a corresponding hypergraph node as a tail end node of the directed hypergraph according to the Inst circuit unit and the pin information given in the INPUT end point information.
And 6.2.3, reading the information of each OUTPUT end point of the Net circuit signal module, finding a corresponding hypergraph node according to an Inst circuit unit and pin information given in the information of the OUTPUT end points, and adding the hypergraph node into the source terminal set with the directed hyper-edge.
In the step 6.4, the step of saving the directed hypergraph obtained by conversion as the directed hypergraph file is as follows.
And 6.4.1, outputting a first line of the directed hypergraph file, wherein the first parameter is the number of directed hyperedges, and the second parameter is the number of nodes of the hypergraph.
And 6.4.2, traversing each directed hyper-edge of the directed hyper-graph, outputting each hyper-edge as one line of the directed hyper-graph file, outputting the serial number of the tail end node of the directed hyper-graph, and then outputting the serial number of the hyper-graph node in the source terminal set of the directed hyper-edge.
In step 7, the improved compressed storage format of the directed hypergraph is as follows.
And 7.1, storing the initial position information of all adjacent directed super-edge lists of each node by using a xadj array, namely, the termination position of the ith node is the initial position minus 1 of the (i + 1) th node, the size of the xadj array is the number of the nodes in the directed super-graph plus 1, and the last element of the xadj array is used for storing the termination position of the last node.
And 7.2, storing the list information of all adjacent directed super edges of each node by using an adjncy array, wherein the adjacent directed super edge list of the ith node is stored in the adjncy array from adjncy [ xadj [ i ] ] to adjncy [ xadj [ i +1] -1 ].
And 7.3, storing the initial position information of the node list contained by each directed super edge by using an eptr array, namely, the terminal position of the jth directed super edge is the initial position of the jth +1 directed super edge minus 1, the size of the eptr array is the number of the directed super edges in the directed super graph plus 1, and the last element of the eptr array is used for storing the terminal position of the last directed super edge.
And 7.4, storing the list information of the nodes contained in each directed super edge by using an eind array, storing the adjacent node list of the jth directed super edge in the eind array from eind [ eptr [ j ] to eind [ eptr [ j +1] -1], and storing the tail end node of the directed super edge in an array element eind [ eptr [ j ] ].
And 7.5, storing the weight information of the nodes by using the vwgts array, wherein the size of the vwgts array is the number of the nodes in the directed hypergraph.
And 7.6, storing the weight information of the directed super-edges by using a hewts array, wherein the size of the hewts array is the number of the directed super-edges in the directed super-graph.
Compared with the prior art, the invention has the following obvious and substantial characteristics and remarkable advantages.
1. The directed hypergraph improves the accuracy of mathematical modeling of the XDL circuit netlist.
Compared with the prior art that a graph is adopted to model a circuit netlist, the invention adopts the directed hypergraph to provide a more accurate model for the XDL circuit netlist: each directed super edge can be connected with more than two nodes, and the connecting lines corresponding to the circuit pins can be connected with more than two circuit pins, thereby achieving remarkable technical progress and outstanding substantive characteristics. The invention adopts a mathematical model of a directed hypergraph to construct the forward topological relation between signals of an XDL circuit netlist, effective pins of each circuit unit in the modeling process are represented as hypergraph nodes in the directed hypergraph, external connecting lines among the circuit pins and circuit logic functions in the circuit pins are represented as directed hypergraph edges in the hypergraph, each directed hypergraph edge can be connected with more than two nodes, the connecting lines corresponding to the circuit units can be connected with more than two effective pins, or the circuit logic functions can be connected with multiple input pins. In each directed super edge, the only output pin corresponds to the tail end node of the directed super edge, and the other input pins correspond to the directed super edge source terminal aggregation points.
Compared with the prior art that circuit units are represented as hypergraph nodes, the invention represents effective pins of the circuit units as hypergraph nodes in a directed hypergraph, provides a more accurate model for an XDL circuit netlist, and particularly delicately describes the forward topological relation among signals of the XDL circuit netlist when the number of the pins reaches twenty or more large circuit units such as SLICEs, SLICEMs and the like.
And thirdly, compared with the prior art that external connecting lines are only expressed as edges or excess edges, the invention expresses the external connecting lines among circuit pins and the circuit logic function in the circuit pins as directed excess edges in the hypergraph, particularly the circuit logic function realized by the circuit units, namely the circuit logic function in the circuit pins, and provides a more accurate model for the XDL circuit netlist. The invention adopts the directed overcrossing to finely depict the forward topological relation among the signals of the XDL circuit netlist, thereby obtaining remarkable technical progress and prominent substantive characteristics.
2. The compression storage format storage directed hypergraph is simple in structure and convenient to maintain.
The physical storage structure of data, which is a physical storage method of the logical structure of data, is to create a data storage map in the memory according to response speed, processing time, modification time, storage space, processing amount per unit time, and the like required for a problem. The directed hypergraph can cause different time complexity and space complexity of the same algorithm under different physical storage structures, and particularly tail end nodes of the directed hypergraph are stored in array elements ein [ eptr [ j ] ]. The invention adopts the characteristic that the most compressed storage format is that no pointer linked list is used, thereby avoiding the retrieval of the adjacent relation and the complicated maintenance work, effectively reducing the space waste, having simple structure and being convenient for maintenance.
The objects, specific structural features and advantages of the present invention will be further understood from the following description of an example of the method of converting an XDL circuit netlist file to a directed hypergraph in accordance with the present invention, taken in conjunction with the accompanying drawings.
FIG. 1 is a flow chart of the method of the present invention for converting an XDL circuit netlist file to a directed hypergraph.
FIG. 2 is an improved compressed storage format for the directed hypergraph of the present invention.
FIG. 3 is a flow diagram of directed hypergraph file generation of the present invention.
Detailed description of the preferred embodiments.
In order to more clearly understand the technical content of the method for converting an XDL circuit netlist file into a directed hypergraph, the following examples are specifically illustrated in detail.
A flow chart of the method for converting an XDL circuit netlist file into a directed hypergraph in this embodiment is shown in fig. 1, and an XDL circuit netlist file 101 is generated by describing a circuit with an XDL circuit netlist language to obtain a circuit source code 102; analyzing the source code of the circuit by a lexical method to obtain a corresponding word symbol 103; performing syntactic analysis on the basis of lexical analysis to obtain corresponding syntactic phrases 104; performing semantic analysis on the basis of the syntactic analysis to obtain corresponding type information 105; constructing corresponding internal intermediate codes 106 on the basis of semantic analysis; the method comprises the steps of extracting Inst and Net module information 107 described by a text based on an internal intermediate code, extracting logic configuration information of an XDL circuit netlist from the Ins module information, extracting interconnection configuration information of the XDL circuit netlist from the Net module information, further constructing a complete circuit network 108 based on the logic configuration information and the interconnection configuration information, converting the complete circuit network into a directed hypergraph and storing the directed hypergraph as a directed hypergraph file 109, reading the directed hypergraph file 109, and storing the directed hypergraph by adopting an improved compression storage format to obtain an improved compression storage format 110 of the directed hypergraph.
The improved compressed storage format of the directed hypergraph of the present embodiment is shown in FIG. 2. The storage structure uses the adjncy array 204 to store the list information of all adjacent directed hyper-edges of each node. And storing the initial position information of all adjacent directed super-edge lists of each node by using a xadj array 203, namely, the termination position of the ith node is the initial position minus 1 of the (i + 1) th node, the size of the xadj array 203 is the number of the nodes in the directed super-graph plus 1, and the last element of the xadj array 203 is used for storing the termination position of the last node. The find array 207 is used to store the list information of the nodes contained by each directed hyper-edge. And storing the initial position information of the node list contained in each directed super edge by using an eptr array 206, namely, the termination position of the jth directed super edge is the initial position of the jth +1 directed super edge minus 1, the size of the eptr array 206 is the sum of 1 of the number of the super edges in the directed super graph, and the last element of the eptr array 206 is used for storing the termination position of the last directed super edge. The vwgts array 202 is used to store the weight information of the nodes, and the size of the vwgts array 202 is the number of the nodes in the directed hypergraph. The hewts array 205 is used to store the weight information of the directed super-edge, and the size of the hewts array 205 is the number of the super-edges in the directed super-graph. Assuming that the array address starts from zero and the node number starts from zero, the list of adjacent directed super edges of the ith node is stored in the adjncy array 204 from adjncy [ xadj [ i ] ] to adjncy [ xadj [ i +1] -1 ]; the list of adjacent nodes for the jth directed super edge is stored in the eind array 207, from eind [ eptr [ j ] to eind [ eptr [ j +1] -1], and the tail node for the directed super edge is stored in the array element eind [ eptr [ j ] ]. The legend 201 contains a total of 7 nodes and 8 super edges, where the 6 th node has a weight of 7, there are 2 adjacent super edges f, h, the corresponding weights are 4, 1, and the corresponding adjacent nodes are nodes 7, 3, 6 and nodes 4, 6, respectively.
The flowchart of the directed hypergraph file generation of this embodiment is shown in fig. 3, and the steps are as follows.
A01: traversing Inst circuit unit module information of the circuit netlist, sequentially processing each Inst circuit unit module, extracting logic configuration information of the XDL circuit netlist, and generating a hypergraph node and a directed hypergraph edge.
A02: and traversing Net circuit signal module information of the circuit netlist, sequentially processing each Net circuit signal module, extracting interconnection configuration information of the XDL circuit netlist, and generating a directed over edge.
A03: traversing each hyper-graph node and each directed hyper-edge of the directed hyper-graph, numbering each hyper-graph node independently, and i is the number of the hyper-graph node in the directed hyper-graph; and j is the number of the directed super edge in the directed super graph.
A04: and storing each numbered hyper-graph node and each numbered directed hyper-edge as a directed hyper-graph file.
Claims (1)
1. A method for converting an XDL circuit netlist file into a directed hypergraph is characterized by comprising the following specific steps:
step 1, performing lexical analysis on an XDL circuit netlist file, reading the XDL circuit netlist file from left to right one by one, and scanning and decomposing a character stream forming a source code so as to recognize words;
step 2, syntax analysis of the XDL circuit netlist file is carried out, word sequences are decomposed into various syntax phrases on the basis of lexical analysis, and whether the whole character stream forms a grammatically correct structure description file or not is determined according to syntax rules of the netlist file;
step 3, performing semantic analysis on the XDL circuit netlist file, checking whether semantic errors exist in the source code on the basis of the syntactic analysis, and collecting type information for the intermediate code generation stage;
step 4, generating an intermediate code of the XDL circuit netlist file, generating the intermediate code of the source code on the basis of syntactic analysis and semantic analysis, and expressing the intermediate code by using an internal intermediate format;
step 5, extracting Inst and Net module information of the XDL circuit netlist file, and generating Inst and Net module information of the XDL circuit netlist file based on an internal intermediate format;
step 6, generating a directed hypergraph file, extracting logic configuration information of an XDL circuit netlist from Ins module information, extracting interconnection configuration information of the XDL circuit netlist from Net module information, further constructing a complete circuit network based on the logic configuration information and the interconnection configuration information, converting the circuit network into a directed hypergraph and storing the directed hypergraph file;
step 7, reading the directed hypergraph file, and storing the directed hypergraph by adopting an improved compressed storage format;
in the above step 6, the step of generating the directed hypergraph file is as follows;
step 6.1, traversing Inst circuit unit module information of the circuit netlist, sequentially processing each Inst circuit unit module, extracting logic configuration information of the XDL circuit netlist, and generating a hypergraph node and a directed hypergraph edge;
step 6.2, traversing Net circuit signal module information of the circuit netlist, sequentially processing each Net circuit signal module, extracting interconnection configuration information of the XDL circuit netlist, and generating a directed overcide;
step 6.3, traversing each hyper-graph node and directed hyper-edge of the directed hyper-graph, numbering each hyper-graph node independently, and i is the number of the hyper-graph node in the directed hyper-graph; numbering each directed supercide independently, wherein j is the number of the directed supercide in the directed hypergraph;
step 6.4, storing each numbered hyper-graph node and each numbered directed hyper-graph edge as a directed hyper-graph file;
in the above step 6.1, the step of processing each Inst circuit unit module is as follows;
step 6.1.1, reading SITEDEF type information of the Inst circuit unit module;
step 6.1.2, reading the CFG configuration information of the Inst circuit unit module, and acquiring an effective pin information list;
6.1.3, generating a hypergraph node for each effective pin of the Inst circuit unit module;
step 6.1.4, analyzing a logic function expression of each output pin according to different SITEDEF types of the Inst circuit unit and by combining a bottom layer circuit configuration state obtained by CFG configuration information;
step 6.1.5, generating a directed super edge for each output pin, wherein the tail end node of the directed super edge is the corresponding hyper graph node of the output pin; adding the hypergraph nodes corresponding to the input pins into the source terminal set of the directed hypergraph according to the logic function expression of the output pins;
in the step 6.2, the step of processing each Net circuit signal module is as follows;
step 6.2.1, generating a directed overcide for the Net circuit signal module;
step 6.2.2, reading INPUT end point information of the Net circuit signal module, and finding a corresponding hypergraph node as a tail end node of the directed hypergraph according to an Inst circuit unit and pin information given in the INPUT end point information;
step 6.2.3, reading each OUTPUT endpoint information of the Net circuit signal module, finding a corresponding hypergraph node according to an Inst circuit unit and pin information given in the OUTPUT endpoint information, and adding the hypergraph node into the source terminal set with the directed hyper-edge;
in the step 6.4, the step of saving the directed hypergraph obtained by conversion into the directed hypergraph file is as follows;
step 6.4.1, outputting a first line of the directed hypergraph file, wherein the first parameter is the number of directed hypergraph edges, and the second parameter is the number of nodes of the hypergraph;
step 6.4.2, traversing each directed hyper-edge of the directed hyper-graph, wherein each hyper-edge is output as a line of the directed hyper-graph file, and firstly outputting the serial number of the tail end node of the directed hyper-graph and then outputting the serial number of the hyper-graph node in the source terminal set of the directed hyper-edge;
in the above step 7, the improved compressed storage format of the directed hypergraph is as follows;
step 7.1, storing the initial position information of all adjacent directed super-edge lists of each node by using a xadj array, namely, the end position of the ith node is the initial position of the (i + 1) th node minus 1, the size of the xadj array is the number of the nodes in the directed super-graph plus 1, and the last element of the xadj array is used for storing the end position of the last node;
step 7.2, storing list information of all adjacent directed super edges of each node by using an adjncy array, wherein the adjacent directed super edge list of the ith node is stored in the adjncy array from adjncy [ xadj [ i ] ] to adjncy [ xadj [ i +1] -1 ];
step 7.3, storing the initial position information of the node list contained by each directed super edge by using an eptr array, namely, the terminal position of the jth directed super edge is the initial position of the jth +1 directed super edge minus 1, the size of the eptr array is the number of the directed super edges in the directed super graph plus 1, and the last element of the eptr array is used for storing the terminal position of the last directed super edge;
step 7.4, storing list information of nodes contained in each directed super edge by using an eind array, storing an adjacent node list of the jth directed super edge in the eind array from eind [ eptr [ j ] to eind [ eptr [ j +1] -1], and storing tail end nodes of the directed super edges in array elements eind [ eptr [ j ];
step 7.5, storing the weight information of the nodes by using a vwgts array, wherein the size of the vwgts array is the number of the nodes in the directed hypergraph;
and 7.6, storing the weight information of the directed super-edges by using a hewts array, wherein the size of the hewts array is the number of the directed super-edges in the directed super-graph.
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| CN116258111B (en) * | 2023-05-15 | 2023-08-04 | 贝叶斯电子科技(绍兴)有限公司 | Static analog integrated circuit layout analysis method |
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