CN111367829A - Linear address acquisition method and device - Google Patents
Linear address acquisition method and device Download PDFInfo
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Abstract
The embodiment of the invention provides a linear address acquisition method and a device, wherein the method comprises the following steps: receiving an addressing instruction, wherein the addressing instruction comprises an address identification; calculating a wafer Die address corresponding to the addressing instruction according to the address identifier; according to the address identification, calculating a Plane address of a flash memory chip corresponding to the addressing instruction; calculating a Block address corresponding to the addressing instruction according to the address identifier; calculating a Word Line (WL) address corresponding to the addressing instruction according to the address identifier; and obtaining a target address according to the Die address, the Plane address, the Block address and the WL address. The embodiment of the invention takes the WL which is one level higher than the Page in the nonvolatile memory as the minimum addressing unit, so that the phenomenon that the addressing mark and the Page can not be aligned can be avoided, and the addressing accuracy is greatly improved.
Description
Technical Field
The present invention relates to the field of memory processing technologies, and in particular, to a method and an apparatus for obtaining a linear address.
Background
With the development of various electronic devices, embedded systems, and the like, nonvolatile memory devices are widely used in electronic products. Taking a non-volatile Memory NAND Flash Memory (NAND Flash Memory) as an example, a NAND Flash Memory is a device (device), one device may have 2 chips (Die), one chip may be divided into two Flash Memory slices (Plane), one Flash Memory slice may be divided into 2048 blocks (Block), one Block may be divided into 256 pages (Page), and one Block may also correspond to 256 WL (Word Line).
In the prior art, the address of the nonvolatile memory is generally in units of pages, so when the nonvolatile memory is addressed, the address is generally in units of pages.
However, the inventor finds that the above technical solution has the following defects in the process of researching the above technical solution: the NandFlash is further classified into MLC NandFlash (Multi Level Cell, Multi-Level Cell flash), TLC NandFlash (Triple Level Cell, three-Level Cell flash), and the like; for MLCNand flash, the number of pages contained in each WL is an integral multiple of 2, for TLC Nandflash, the number of pages contained in each WL is an integral multiple of 3, and when addressing is carried out by taking the pages as a unit, an addressing error phenomenon often occurs in the TLCNand flash.
Disclosure of Invention
In view of the above problems, a method and an apparatus for obtaining a linear address according to embodiments of the present invention are provided to solve the problem of an addressing error occurring in TLCNandFlash.
According to a first aspect of the present invention, there is provided a linear address obtaining method applied to a nonvolatile memory, the method including:
receiving an addressing instruction, wherein the addressing instruction comprises an address identification;
calculating a wafer Die address corresponding to the addressing instruction according to the address identifier;
according to the address identification, calculating a Plane address of a flash memory chip corresponding to the addressing instruction;
calculating a Block address corresponding to the addressing instruction according to the address identifier;
calculating a Word Line (WL) address corresponding to the addressing instruction according to the address identifier;
and obtaining a target address according to the Die address, the Plane address, the Block address and the WL address.
Preferably, the calculating a Die address corresponding to the addressing instruction according to the address identifier includes:
after the address identifier is moved to the right by a Plane Bit, carrying out AND calculation with a Die address mask; the PlaneBit is determined according to the number of planes included in the nonvolatile memory, and the Die address mask is determined by the number of bits occupied by the Die included in the nonvolatile memory.
Preferably, the calculating a Plane address of a flash memory slice corresponding to the addressing instruction according to the address identifier includes:
performing AND calculation on the address identifier and a Plane address mask; wherein the Plane address mask is determined by a number of bits occupied by a Plane included in the nonvolatile memory.
Preferably, the calculating, according to the address identifier, a Block address corresponding to the addressing instruction includes:
after the address identification is shifted to the right by a first digit, performing AND calculation with a Block address mask; wherein the first digit is: the Plane Bit, the Die Bit and the WL Bit are summed, the Die Bit is determined according to the number of the Dies included in the nonvolatile storage, the WL Bit is determined according to the number of the WLs included in the nonvolatile storage, and the Block address mask is determined by the number of bits occupied by the Block included in the nonvolatile storage.
Preferably, the calculating a word line WL address corresponding to the addressing instruction according to the address identifier includes:
after the address identifier is shifted to the right by a second digit, performing AND calculation with a WL address mask; wherein the second number of bits is: a sum of the Plane Bit and the Die Bit, the WL address mask being determined by a number of bits occupied by WLs included in the non-volatile memory.
According to a second aspect of the present invention, there is provided a linear address obtaining apparatus applied to a nonvolatile memory, the apparatus comprising:
the device comprises a receiving module, a processing module and a processing module, wherein the receiving module is used for receiving an addressing instruction, and the addressing instruction comprises an address identifier;
a Die address calculation module for calculating a Die address corresponding to the addressing instruction according to the address identifier;
the Plane address calculation module is used for calculating a Plane address of the flash memory slice corresponding to the addressing instruction according to the address identifier;
the Block address calculation module is used for calculating a Block address corresponding to the addressing instruction according to the address identifier;
the WL address calculation module is used for calculating a word line WL address corresponding to the addressing instruction according to the address identifier;
and the target address obtaining module is used for obtaining a target address according to the Die address, the Plane address, the Block address and the WL address.
Preferably, the module for calculating according to the Die address includes:
the Die address calculation submodule is used for carrying out AND calculation on the address identifier and a Die address mask after the address identifier is moved to the right by the Plane Bit; the Plane Bit is determined according to the number of planes included in the nonvolatile memory, and the Die address mask is determined by the number of bits occupied by the Die included in the nonvolatile memory.
Preferably, the Plane address calculation module includes:
the Plane address calculation submodule is used for carrying out AND calculation on the address identifier and a Plane address mask; wherein the Plane address mask is determined by a number of bits occupied by a Plane included in the nonvolatile memory.
Preferably, the Block address calculation module includes:
the Block address calculation submodule is used for carrying out AND calculation on the address identifier and a Block address mask after the address identifier is shifted to the right by a first digit; wherein the first digit is: the Plane Bit, the Die Bit and the WL Bit are summed, the Die Bit is determined according to the number of the Dies included in the nonvolatile storage, the WL Bit is determined according to the number of the WLs included in the nonvolatile storage, and the Block address mask is determined by the number of bits occupied by the Block included in the nonvolatile storage.
Preferably, the WL address calculation module includes:
the WL address calculation submodule is used for carrying out AND calculation on the WL address mask after the address identifier is shifted to the right by a second digit; wherein the second number of bits is: a sum of the Plane Bit and the Die Bit, the WL address mask being determined by a number of bits occupied by WLs included in the non-volatile memory.
In the embodiment of the present invention, it is found that the reason why the non-programmed memory cell is programmed in the prior art is: TLC NandFlash, each WL contains an integer multiple of 3, therefore, when Page is taken as addressing unit, the phenomenon that addressing identification and Page can not be aligned can occur, and the addressing error is caused. Therefore, when the embodiment of the invention acquires the linear address of the nonvolatile memory, the WL is taken as the addressing counting unit, after the addressing instruction including the address identifier is received, the Die address, the Plane address, the Block address and the WL address are obtained through the address identifier calculation, and the target address corresponding to the address identifier can be corresponding according to the hierarchical relationship of the Die address, the Plane address, the Block address and the WL address. In the embodiment of the invention, the WL which is one level higher than the Page in the nonvolatile memory is taken as the minimum addressing unit, so that the phenomenon that the addressing identification and the Page cannot be aligned can be avoided, the addressing accuracy is greatly improved, and the WL is taken as the minimum unit when the nonvolatile memory is operated, and the operation speed can be greatly improved because the operation on the Page address is not needed during the addressing.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
fig. 1 is a flowchart of a linear address obtaining method according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a linear address provided by an embodiment of the present invention;
fig. 3 is a schematic diagram of address mapping according to an embodiment of the present invention;
fig. 4 is a block diagram of a linear address obtaining apparatus according to an embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below. It should be understood that the specific embodiments described herein are merely illustrative of the invention, but do not limit the invention to only some, but not all embodiments.
Example one
Referring to fig. 1, a flowchart of a linear address obtaining method is shown, which is applied to a nonvolatile memory, and specifically includes the following steps:
step 101: an addressing instruction is received, wherein the addressing instruction includes an address identification.
In the embodiment of the present invention, an address identifier is taken as an example of a FWA address identifier, where the FWA is a linear address used by an FTL (Flash translation layer), and the address includes a Die address, a Block address, a Plane address, and a WL address. Taking the non-volatile memory as TLC NandFlash as an example, the TLC NandFlash may be: there are 2 Die, one Die has two planes, one Plane has 2048 blocks, one Block has 256 WLs, and the composition of FWA can be as shown in FIG. 2.
In a specific application, as shown in fig. 3, the FWA0 may identify the address of the FWA as 0; FWA1 may identify the address of FWA as 1; the FWA2 may identify the FWA address as 10, and so on. Through steps 102 to 105, a Die address, a Block address, a Plane address, and a WL address can be respectively obtained according to the address identifier.
In the embodiment of the present invention, referring to fig. 3, there are 2 Die: die0, Die 1; there are two planes per Die: plane0, Plane 1; each Plane had 2 blocks: block0, Block 1; each Block has 2 WLs: WL0 and WL1 are examples to illustrate specific implementations of steps 102 to 105.
Step 102: and calculating the wafer Die address corresponding to the addressing instruction according to the address identifier.
Assuming that the address in step 101 is identified as 10 in binary, referring to fig. 3, the Die address corresponding to FWA2 in the non-volatile memory is to be obtained.
In a preferred embodiment, the Die address corresponding to the FWA may be obtained by:
after the address identifier is moved to the right by a Plane Bit, carrying out AND calculation with a Die address mask; the PlaneBit is determined according to the number of planes included in the nonvolatile memory, and the Die address mask is determined by the number of bits occupied by the Die included in the nonvolatile memory.
In the embodiment of the invention, the Plane Bit is determined according to the number of the planes included in the nonvolatile memory, for example, if only two planes are included in the Die, the two planes can be identified through 0 and 1, so that the Plane only needs to occupy one Bit, and the Plane Bit is 1; it can be understood that if there are only four planes in Die, the planes need to be labeled with 00, 01, 10, and 11, and then the Plane needs to occupy two bits, and the Plane Bit is 2, and so on, and the description is omitted here.
In the embodiment of the present invention, a Die address Mask (Die Bit Mask) is determined by a Bit number occupied by a Die included in a nonvolatile memory, and in a specific application, a Bit occupied by the Die may be set to 1, and a Bit not occupied by the Die may be set to 0.
In a specific application, after the address identifier is shifted to the right by the Plane Bit, the step of performing and calculation with the Die address mask may be expressed as a formula:
(FWA>>Plane Bit)&Die Bit Mask
taking the address identifier of FWA as 10 and the Plane Bit as 1 as an example, shifting 10 to the right by one Bit to obtain 1, and performing an and operation on 1 and the DieBit Mask, the bits except the Die address are all 0, and only the position corresponding to the Die address is subjected to the and operation on 1, and then taking the Die Bit Mask as 01 as an example, 1 can be obtained, so that it can be determined that the Die address is 1. For example, referring to fig. 3, FWA2 corresponds to Die 1.
Step 103: and calculating the Plane address of the flash memory sheet corresponding to the addressing instruction according to the address identification.
Assuming that the address in step 101 is identified as 10 in binary, referring to fig. 3, a Plane address corresponding to FWA2 in the nonvolatile memory is to be obtained.
In a preferred embodiment, the Plane address corresponding to the FWA can be obtained by:
performing AND calculation on the address identifier and a Plane address mask; wherein the Plane address mask is determined by a number of bits occupied by a Plane included in the nonvolatile memory.
In the embodiment of the present invention, a Plane address Mask (Plane Bit Mask) is determined by a Bit number occupied by a Plane included in a nonvolatile memory, and in a specific application, a Bit occupied by the Plane may be set to 1, and a Bit not occupied by the Plane may be set to 0.
In a specific application, the step of performing and calculation on the address identifier and the Plane address mask may be expressed as a formula:
FWA&Plane Bit Mask
taking the address label of FWA as 10 and Die Bit Mask as 001 as an example, and performing an and operation on 10 and Die Bit Mask to obtain 0, it can be determined that the Plane address is 0. For example, referring to fig. 3, FWA2 corresponds to Plane 0.
Step 104: and calculating the Block address corresponding to the addressing instruction according to the address identifier.
By way of example, assuming that the address in step 101 is identified as 10 in binary, referring to fig. 3, the Block address corresponding to FWA2 in the non-volatile memory is to be obtained.
In a preferred embodiment, the Block address corresponding to the FWA may be obtained by:
after the address identification is shifted to the right by a first digit, performing AND calculation with a Block address mask; wherein the first digit is: the Plane Bit, the Die Bit and the WL Bit are summed, the Die Bit is determined according to the number of the Dies included in the nonvolatile storage, the WL Bit is determined according to the number of the WLs included in the nonvolatile storage, and the Block address mask is determined by the number of bits occupied by the Block included in the nonvolatile storage.
In the embodiment of the invention, the Die Bit is determined according to the number of the Die included in the nonvolatile memory, for example, if there are only two dice, the two dice can be identified through 0 and 1, so that the Die only needs to occupy one Bit, and the Die Bit is 1; it can be understood that if there are four Die, they need to be identified by 00, 01, 10, and 11, and then Die needs to occupy two bits, and Die Bit is 2, and so on, and will not be described herein again.
In the embodiment of the invention, the WL Bit is determined according to the number of Die included in the nonvolatile memory, for example, if one Block has only two WLs, the two WLs can be identified through 0 and 1, so that the WL only needs to occupy one Bit, and the WLbit is 1; it can be understood that if there are four WLs, they need to be identified by 00, 01, 10, 11, and the WL needs to occupy two bits, and the WL Bit is 2, and so on, and will not be described herein again.
In the embodiment of the present invention, a Block address Mask (Block Bit Mask) is determined by a Bit number occupied by a Block included in a nonvolatile memory, and in a specific application, a Bit occupied by the Block may be set to 1, and a Bit not occupied by the Block may be set to 0.
In a specific application, after the address identifier is shifted to the right by the first digit, the step of performing and calculation with the Block address mask may be expressed as a formula:
(FWA>>(WL Bit+Die Bit+Plane Bit))&Block Bit Mask
taking the address label of FWA as 10, Plane Bit as 1, Die Bit as 1, and WL Bit as 1 as examples, shifting 10 to the right by 3 bits to obtain 0, and performing an and operation on 0 and Die Bit Mask to obtain 0, it can be determined that the Block address is 0. For example, referring to fig. 3, FWA2 corresponds to Block 0.
Step 105: and calculating the word line WL address corresponding to the addressing instruction according to the address identification.
Assuming the address is identified as 10 in binary by way of example in step 101, referring to fig. 3, the FWA2 is to be obtained corresponding to the WL address in the non-volatile memory.
In a preferred embodiment, the WL address corresponding to the FWA may be obtained by:
after the address identifier is shifted to the right by a second digit, performing AND calculation with a WL address mask; wherein the second number of bits is: a sum of the Plane Bit and the Die Bit, the WL address mask being determined by a number of bits occupied by WLs included in the non-volatile memory.
In the embodiment of the present invention, a WL address Mask (WL Bit Mask) is determined by the number of bits occupied by WLs included in the nonvolatile memory, and in a specific application, the number of bits occupied by WLs may be set to 1, and the number of bits not occupied by WLs may be set to 0.
In a specific application, after the address identifier is shifted to the right by the second digit, the step of performing and calculation with the WL address mask may be expressed as a formula:
(FWA>>(Die Bit+Plane Bit))&WL Bit Mask
taking the address label of FWA as 10, Plane Bit as 1, and Die Bit as 1 as examples, shifting 10 by 2 bits to the right to obtain 0, and performing an and operation on 0 and WL Bit Mask to obtain 0, it can be determined that the WL address is 0. For example, referring to fig. 3, FWA2 corresponds to WL 0.
Step 106: and obtaining a target address according to the Die address, the Plane address, the Block address and the WL address.
In the embodiment of the present invention, as determined in step 102, for example, Die address is Die1, Plane address is Plane0, Block address is Block0, and WL address is WL0, it may be located that the target address corresponding to FWA2 is WL0 in Block0 included in Plane0 in Die 1.
It can be understood that in a specific application, if only the Block address needs to be accessed, for example, data in Block0 is read, the step of obtaining WL does not need to be performed, and similarly, only the Plane address may be accessed, which is not specifically limited in the embodiment of the present invention.
In summary, the embodiments of the present invention find out that the reason why the non-programmed memory cell is programmed in the prior art is: TLC NandFlash, each WL contains an integer multiple of 3, therefore, when Page is taken as addressing unit, the phenomenon that addressing identification and Page can not be aligned can occur, and the addressing error is caused. Therefore, when the embodiment of the invention acquires the linear address of the nonvolatile memory, the WL is taken as the addressing counting unit, after the addressing instruction including the address identifier is received, the Die address, the Plane address, the Block address and the WL address are obtained through the address identifier calculation, and the target address corresponding to the address identifier can be corresponding according to the hierarchical relationship of the Die address, the Plane address, the Block address and the WL address. In the embodiment of the invention, the WL which is one level higher than the Page in the nonvolatile memory is taken as the minimum addressing unit, so that the phenomenon that the addressing identification and the Page cannot be aligned can be avoided, the addressing accuracy is greatly improved, and the WL is taken as the minimum unit when the nonvolatile memory is operated, and the operation speed can be greatly improved because the operation on the Page address is not needed during the addressing.
It should be noted that the foregoing method embodiments are described as a series of acts or combinations for simplicity in explanation, but it should be understood by those skilled in the art that the present invention is not limited by the order of acts or acts described, as some steps may occur in other orders or concurrently in accordance with the invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no particular act is required to implement the invention.
Example two
Referring to fig. 4, a block diagram of a linear address obtaining apparatus is shown, where the apparatus may specifically include:
a receiving module 410, configured to receive an addressing instruction, where the addressing instruction includes an address identifier;
a Die address calculation module 420, configured to calculate a Die address corresponding to the addressing instruction according to the address identifier;
a Plane address calculation module 430, configured to calculate a Plane address of the flash memory slice corresponding to the addressing instruction according to the address identifier;
a Block address calculation module 440, configured to calculate, according to the address identifier, a Block address corresponding to the addressing instruction;
a WL address calculation module 450, configured to calculate, according to the address identifier, a word line WL address corresponding to the addressing instruction;
a target address obtaining module 460, configured to obtain a target address according to the Die address, the Plane address, the Block address, and the WL address.
Preferably, the module 420 for calculating the Die address includes:
the Die address calculation submodule is used for carrying out AND calculation on the address identifier and a Die address mask after the address identifier is moved to the right by the Plane Bit; the Plane Bit is determined according to the number of planes included in the nonvolatile memory, and the Die address mask is determined by the number of bits occupied by the Die included in the nonvolatile memory.
Preferably, the Plane address calculation module 430 includes:
the Plane address calculation submodule is used for carrying out AND calculation on the address identifier and a Plane address mask; wherein the Plane address mask is determined by a number of bits occupied by a Plane included in the nonvolatile memory.
Preferably, the Block address calculation module 440 includes:
the Block address calculation submodule is used for carrying out AND calculation on the address identifier and a Block address mask after the address identifier is shifted to the right by a first digit; wherein the first digit is: the Plane Bit, the Die Bit and the WL Bit are summed, the Die Bit is determined according to the number of the Dies included in the nonvolatile storage, the WL Bit is determined according to the number of the WLs included in the nonvolatile storage, and the Block address mask is determined by the number of bits occupied by the Block included in the nonvolatile storage.
Preferably, the WL address calculation module 450 includes:
the WL address calculation submodule is used for carrying out AND calculation on the WL address mask after the address identifier is shifted to the right by a second digit; wherein the second number of bits is: a sum of the Plane Bit and the Die Bit, the WL address mask being determined by a number of bits occupied by WLs included in the non-volatile memory.
In summary, the embodiments of the present invention find out that the reason why the non-programmed memory cell is programmed in the prior art is: TLC NandFlash, each WL contains an integer multiple of 3, therefore, when Page is taken as addressing unit, the phenomenon that addressing identification and Page can not be aligned can occur, and the addressing error is caused. Therefore, when the embodiment of the invention acquires the linear address of the nonvolatile memory, the WL is taken as the addressing counting unit, after the addressing instruction including the address identifier is received, the Die address, the Plane address, the Block address and the WL address are obtained through the address identifier calculation, and the target address corresponding to the address identifier can be corresponding according to the hierarchical relationship of the Die address, the Plane address, the Block address and the WL address. In the embodiment of the invention, the WL which is one level higher than the Page in the nonvolatile memory is taken as the minimum addressing unit, so that the phenomenon that the addressing identification and the Page cannot be aligned can be avoided, the addressing accuracy is greatly improved, and the WL is taken as the minimum unit when the nonvolatile memory is operated, and the operation speed can be greatly improved because the operation on the Page address is not needed during the addressing.
For the device embodiment, since it is basically similar to the method embodiment, the description is simple, and for the relevant points, refer to the partial description of the method embodiment.
The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
In a typical configuration, the computer device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory. The memory may include forms of volatile memory in a computer readable medium, Random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of a computer-readable medium. Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include non-transitory computer readable media (fransitory media), such as modulated data signals and carrier waves.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable linear address acquisition terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable linear address acquisition terminal device, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable linear address acquisition terminal to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable linear address acquisition terminal device to cause a series of operational steps to be performed on the computer or other programmable terminal device to produce a computer implemented process such that the instructions which execute on the computer or other programmable terminal device provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.
The above detailed description is made on a linear address obtaining method and a linear address obtaining apparatus provided by the present invention, and a specific example is applied in the present document to explain the principle and the implementation of the present invention, and the description of the above embodiment is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (10)
1. A linear address acquisition method applied to a nonvolatile memory, the method comprising:
receiving an addressing instruction, wherein the addressing instruction comprises an address identification;
calculating a wafer Die address corresponding to the addressing instruction according to the address identifier;
according to the address identification, calculating a Plane address of a flash memory chip corresponding to the addressing instruction;
calculating a Block address corresponding to the addressing instruction according to the address identifier;
calculating a Word Line (WL) address corresponding to the addressing instruction according to the address identifier;
and obtaining a target address according to the Die address, the Plane address, the Block address and the WL address.
2. The method according to claim 1, wherein said calculating a Die address corresponding to the addressing instruction according to the address identifier comprises:
after the address identifier is moved to the right by a Plane Bit, carrying out AND calculation with a Die address mask; the Plane Bit is determined according to the number of planes included in the nonvolatile memory, and the Die address mask is determined by the number of bits occupied by the Die included in the nonvolatile memory.
3. The method of claim 1, wherein calculating a flash disk Plane address corresponding to the addressing instruction according to the address identifier comprises:
performing AND calculation on the address identifier and a Plane address mask; wherein the Plane address mask is determined by a number of bits occupied by a Plane included in the nonvolatile memory.
4. The method according to claim 2, wherein the calculating, according to the address identifier, a Block address corresponding to the addressing instruction includes:
after the address identification is shifted to the right by a first digit, performing AND calculation with a Block address mask; wherein the first digit is: the Plane Bit, the Die Bit and the WL Bit are summed, the Die Bit is determined according to the number of the Dies included in the nonvolatile storage, the WL Bit is determined according to the number of the WLs included in the nonvolatile storage, and the Block address mask is determined by the number of bits occupied by the Block included in the nonvolatile storage.
5. The method of claim 4, wherein calculating a Word Line (WL) address corresponding to the addressing instruction according to the address identifier comprises:
after the address identifier is shifted to the right by a second digit, performing AND calculation with a WL address mask; wherein the second number of bits is: a sum of the Plane Bit and the Die Bit, the WL address mask being determined by a number of bits occupied by WLs included in the non-volatile memory.
6. A linear address obtaining apparatus, applied to a nonvolatile memory, the apparatus comprising:
the device comprises a receiving module, a processing module and a processing module, wherein the receiving module is used for receiving an addressing instruction, and the addressing instruction comprises an address identifier;
a Die address calculation module for calculating a Die address corresponding to the addressing instruction according to the address identifier;
the Plane address calculation module is used for calculating a Plane address of the flash memory slice corresponding to the addressing instruction according to the address identifier;
the Block address calculation module is used for calculating a Block address corresponding to the addressing instruction according to the address identifier;
the WL address calculation module is used for calculating a word line WL address corresponding to the addressing instruction according to the address identifier;
and the target address obtaining module is used for obtaining a target address according to the Die address, the Plane address, the Block address and the WL address.
7. The apparatus of claim 6, wherein the means for calculating the Die address comprises:
the Die address calculation submodule is used for carrying out AND calculation on the address identifier and a Die address mask after the address identifier is moved to the right by the Plane Bit; the Plane Bit is determined according to the number of planes included in the nonvolatile memory, and the Die address mask is determined by the number of bits occupied by the Die included in the nonvolatile memory.
8. The apparatus of claim 6, wherein the Plane address calculation module comprises:
the Plane address calculation submodule is used for carrying out AND calculation on the address identifier and a Plane address mask; wherein the Plane address mask is determined by a number of bits occupied by a Plane included in the nonvolatile memory.
9. The apparatus of claim 7, wherein the Block address calculation module comprises:
the Block address calculation submodule is used for carrying out AND calculation on the address identifier and a Block address mask after the address identifier is shifted to the right by a first digit; wherein the first digit is: the Plane Bit, the Die Bit and the WL Bit are summed, the Die Bit is determined according to the number of the Dies included in the nonvolatile storage, the WL Bit is determined according to the number of the WLs included in the nonvolatile storage, and the Block address mask is determined by the number of bits occupied by the Block included in the nonvolatile storage.
10. The apparatus of claim 9, wherein the WL address calculation module comprises:
the WL address calculation submodule is used for carrying out AND calculation on the WL address mask after the address identifier is shifted to the right by a second digit; wherein the second number of bits is: a sum of the Plane Bit and the Die Bit, the WL address mask being determined by a number of bits occupied by WLs included in the non-volatile memory.
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