CN111314699A - Image decoding method, device, electronic equipment and storage medium - Google Patents

Image decoding method, device, electronic equipment and storage medium Download PDF

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CN111314699A
CN111314699A CN202010131316.XA CN202010131316A CN111314699A CN 111314699 A CN111314699 A CN 111314699A CN 202010131316 A CN202010131316 A CN 202010131316A CN 111314699 A CN111314699 A CN 111314699A
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image
decoded
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董学辉
虞科华
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Beijing QIYI Century Science and Technology Co Ltd
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Beijing QIYI Century Science and Technology Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/13—Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/124—Quantisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/625—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding using discrete cosine transform [DCT]

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Abstract

The application discloses an image decoding method, an image decoding device, terminal equipment and a storage medium, wherein the method comprises the steps of obtaining image data of an image to be decoded through a first processor, wherein the image data comprises file header data; executing analysis operation on the file header data to obtain analysis data and storing the analysis data; transmitting the analysis data and the image data; receiving decoded data corresponding to the image data; and generating a decoded image by using the decoded data. Receiving the analysis data of the file header data of the image to be decoded and the image data through a second processor; decoding the image data according to the analysis data to obtain decoded data; and transmitting the decoded data. According to the embodiment of the application, the first processor is matched with the second processor, so that efficient hardware decoding of the image to be decoded is realized, the hardware decoding speed is high, the power consumption is low, and the comprehensive cost of image decoding is reduced.

Description

Image decoding method, device, electronic equipment and storage medium
Technical Field
The present application relates to the field of image processing technologies, and in particular, to an image decoding method and apparatus, an electronic device, and a storage medium.
Background
With the rapid development of the internet, the current mainstream picture format is mainly the JPEG image format, and due to different screen sizes of different devices, the requirement of picture size conversion often exists; meanwhile, as the internet uses more and more pictures, the demand for picture compression is increasing to reduce the storage and bandwidth cost, and the first step of the processing operation related to the pictures is decoding. Currently, the mainstream decoding method is decoding by using software through a CPU.
In the related art, the CPU as a multitasking processor is not specially designed for the decoding task, so the decoding efficiency is not high, and the decoding cost is high when the CPU is used alone in terms of throughput delay and the like, and the conventional decoding based on Real Time Language (RTL) has a disadvantage of long development period and poor flexibility.
In view of the above problems, no effective solution has been proposed.
Disclosure of Invention
In order to solve the technical problems described above or at least partially solve the technical problems, the present application provides an image decoding method, an apparatus, a terminal device and a storage medium.
In view of the foregoing, in a first aspect, an embodiment of the present application provides an image decoding method, which is executed on a first processor, and includes the following steps:
acquiring image data of an image to be decoded, wherein the image data comprises file header data;
executing analysis operation on the file header data to obtain analysis data and storing the analysis data;
transmitting the analysis data and the image data;
receiving decoded data corresponding to the image data;
and generating a decoded image by using the decoded data.
Optionally, before generating a decoded image by using the decoded data, the method further includes:
acquiring pixel format data of the decoded data;
performing pixel format conversion on the pixel format data according to components to obtain a plurality of pixel format component data;
and splicing and combining the plurality of pixel format component data to obtain target pixel format data.
Optionally, the performing pixel format conversion on the pixel format data according to components includes:
reading the pixel format data in components from the corresponding read addresses;
and storing the read data to the target write address.
In a second aspect, the present application provides an image decoding method, which is executed on a second processor, the method comprising the steps of:
receiving analysis data and image data of file header data of an image to be decoded;
decoding the image data according to the analysis data to obtain decoded data;
and transmitting the decoded data.
Optionally, the decoding the image data according to the analysis data to obtain decoded data includes:
performing Huffman decoding on the image data to obtain Huffman decoding data;
performing stroke decoding on the Huffman decoding data to obtain stroke decoding data;
carrying out inverse quantization on the stroke decoding data to obtain inverse quantization data; and
and performing inverse discrete cosine transform on the inverse quantization data to obtain decoded data.
Optionally, before sending the decoded data, the method further includes:
converting the decoded data from YC by color space conversion formulaBCRThe format is converted to RGB format.
In a third aspect, the present application provides an image decoding method, where the method is performed in an electronic device, where a first processor and a second processor are disposed in the electronic device, and the method includes:
the first processor acquires image data of an image to be decoded, wherein the image data comprises file header data;
the first processor executes analysis operation on the file header data to obtain analysis data and store the analysis data;
the first processor sending the parsed data and the image data to the second processor;
the second processor receiving the parsed data and image data;
the second processor decodes the image data according to the analysis data to obtain decoded data;
the second processor sending the decoded data to the first processor;
the first processor receiving the decoded data;
the first processor generates a decoded image using the decoded data.
In a fourth aspect, an embodiment of the present application provides an image decoding apparatus, including:
the device comprises an acquisition unit, a decoding unit and a decoding unit, wherein the acquisition unit is used for acquiring image data of an image to be decoded, and the image data comprises file header data;
the analysis unit is used for executing analysis operation on the file header data to obtain analysis data and storing the analysis data;
a data transmitting unit configured to transmit the analysis data and the image data;
a data receiving unit for receiving decoded data corresponding to the image data;
and an image generation unit configured to generate a decoded image using the decoded data.
In a fifth aspect, the present application provides an image decoding apparatus, comprising:
the data receiving unit is used for receiving the analysis data of the file header data of the image to be decoded and the image data;
a decoding unit, configured to decode the image data according to the analysis data to obtain decoded data;
and a decoded data transmitting unit for transmitting the decoded data.
In a sixth aspect, an embodiment of the present application provides an image decoding apparatus, including:
the device comprises a first processor, a second processor and a third processor, wherein the first processor is used for acquiring image data of an image to be decoded, and the image data comprises file header data; executing analysis operation on the file header data to obtain analysis data and storing the analysis data; transmitting the analysis data and the image data; receiving the decoded data; generating a decoded image using the decoded data;
a second processor for receiving the parsed data and image data; decoding the image data according to the analysis data to obtain decoded data; and transmitting the decoded data.
In a seventh aspect, an embodiment of the present application provides an electronic device, where the electronic device includes: at least one processor, memory, at least one network interface, and a user interface;
the at least one processor, memory, at least one network interface, and user interface are coupled together by a bus system;
the processor is configured to perform the steps of the image decoding method according to the first aspect, the second aspect, or the third aspect by calling a program or instructions stored in the memory.
In an eighth aspect, the present application provides a computer-readable storage medium, on which an image decoding program is stored, and when executed by a processor, the image decoding program implements the steps of the image decoding method according to the first aspect, the second aspect, or the third aspect.
Compared with the prior art, the technical scheme provided by the embodiment of the application has the following advantages:
according to the method provided by the embodiment of the application, the first processor is used for acquiring the image data of an image to be decoded, wherein the image data comprises file header data; executing analysis operation on the file header data to obtain analysis data and storing the analysis data; transmitting the analysis data and the image data; receiving decoded data corresponding to the image data; and generating a decoded image by using the decoded data. Receiving the analysis data of the file header data of the image to be decoded and the image data through a second processor; decoding the image data according to the analysis data to obtain decoded data; and transmitting the decoded data. According to the embodiment of the application, the first processor is matched with the second processor, so that efficient hardware decoding of the image to be decoded is realized, the hardware decoding speed is high, the power consumption is low, and the comprehensive cost of image decoding is reduced.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.
Fig. 1 is a schematic flowchart of an image decoding method according to an embodiment of the present application;
fig. 2 is a schematic flowchart of another image decoding method according to an embodiment of the present application;
fig. 3 is a schematic flowchart of another image decoding method according to an embodiment of the present application;
fig. 4 is a schematic flowchart of another image decoding method according to an embodiment of the present application;
fig. 5 is a schematic flowchart of another image decoding method according to an embodiment of the present application;
fig. 6 is a schematic flowchart of another image decoding method according to an embodiment of the present application;
fig. 7 is a flowchart illustrating a further image decoding method according to an embodiment of the present application;
fig. 8 is a schematic structural diagram of an image decoding apparatus according to an embodiment of the present application;
fig. 9 is a schematic structural diagram of another image decoding apparatus according to an embodiment of the present application;
fig. 10 is a schematic structural diagram of another image decoding apparatus according to an embodiment of the present application;
fig. 11 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
A server implementing various embodiments of the present invention will now be described with reference to the accompanying drawings. In the following description, suffixes such as "module", "component", or "unit" used to denote elements are used only for facilitating the explanation of the present invention, and have no specific meaning in themselves. Thus, "module" and "component" may be used in a mixture.
An embodiment of the present application provides an image decoding method, which is executed on a first processor, and as shown in fig. 1, the method may include the following steps:
s101, a first processor acquires image data of an image to be decoded, wherein the image data comprises file header data.
Optionally, the embodiment of the present application is mainly applied to realize decoding of an image to be decoded based on OpenCL (Open Computing Language), and the advantage of fast development iteration of OpenCL is utilized to realize fast decoding of a JPEG image format, where the picture format of the image to be decoded includes but is not limited to: JPG, PNG, GIF, RAW, JPEG, and the like.
S102, the first processor executes analysis operation on the file header data to obtain analysis data and store the analysis data.
S103, the first processor sends the analysis data and the image data.
And S104, receiving decoding data corresponding to the image data by the first processor.
And S105, generating a decoded image by the first processor by using the decoded data.
Optionally, on the basis of the embodiment shown in fig. 1, an embodiment of the present application further provides an image decoding method, where the method is executed by a first processor, as shown in fig. 2, and the method includes the following steps:
s201, a first processor acquires image data of an image to be decoded, wherein the image data comprises file header data.
S202, the first processor executes analysis operation on the file header data to obtain analysis data and store the analysis data.
S203, the first processor sends the analysis data and the image data.
S204, the first processor receives decoding data corresponding to the image data.
S205, the first processor acquires pixel format data of the decoded data.
S206, the first processor converts the pixel format data according to the pixel format according to the components to obtain a plurality of pixel format component data.
Optionally, performing pixel format conversion on the pixel format data according to components, including:
reading the pixel format data in components from the corresponding read addresses;
and storing the read data to the target write address.
And S207, the first processor splices and combines the pixel format component data to obtain target pixel format data.
Optionally, the splicing and combining of the multiple pixel format component data may be implemented by rearranging the positions of the gray scale data, and finally, the rearranged gray scale data is combined.
And S208, generating a decoded image by the first processor according to the target pixel format data and by using the decoded data.
The embodiment of the application can also solve the problem that image data formats required by different types of hardware chips are different, and secondary processing is performed on the processed image data, for example, pixel format conversion is performed on pixel format data of the decoded data according to components to obtain the decoded data after the secondary processing, so that the decoded data after the secondary processing conforms to the data format required by the hardware chip, decoding errors caused by data format errors in the decoding process are avoided, and the decoding success rate and the decoding rate are improved.
An embodiment of the present application provides an image decoding method, which is executed in a second processor, and as shown in fig. 3, the method may include the following steps:
s301, the second processor receives the analysis data of the file header data of the image to be decoded and the image data.
S302, decoding the image data by the second processor according to the analysis data to obtain decoded data.
And S303, the second processor sends the decoded data.
Compared with single CPU software decoding, the embodiment of the application has the advantages that the hardware decoding speed is high, the power consumption is low and the cost is lower by combining with the FPGA; compared with the development cycle of the RTL (real time Language) and the poor flexibility, the development method and the development system of the RTL have the advantages that the OpenCL (Open Computing Language) is adopted to facilitate the expansion and the transplantation, and the development efficiency is higher.
Optionally, on the basis of the embodiment shown in fig. 3, an embodiment of the present application further provides an image decoding method, where the method is executed by a second processor, as shown in fig. 4, and the method includes the following steps:
s401, the second processor receives the analysis data of the file header data of the image to be decoded and the image data.
S402, carrying out Huffman decoding on the image data by the second processor to obtain Huffman decoding data.
And S403, the second processor performs run length decoding on the Huffman decoding data to obtain run length decoding data.
S404, the second processor performs inverse quantization on the stroke decoding data to obtain inverse quantization data.
S405, the second processor performs inverse discrete cosine transform on the inverse quantization data to obtain decoding data.
S406, the second processor sends the decoding data.
Optionally, on the basis of the embodiment shown in fig. 4, an embodiment of the present application further provides an image decoding method, where the method is executed by a second processor, as shown in fig. 5, and the method includes the following steps:
s501, the second processor receives analysis data of file header data of an image to be decoded and image data.
S502, carrying out Huffman decoding on the image data by the second processor to obtain Huffman decoding data.
And S503, the second processor performs stroke decoding on the Huffman decoding data to obtain stroke decoding data.
And S504, the second processor performs inverse quantization on the stroke decoding data to obtain inverse quantization data.
And S505, the second processor performs inverse discrete cosine transform on the inverse quantized data to obtain decoded data.
S506, the second processor converts the decoded data into YC through a color space conversion formulaBCRThe format is converted to RGB format.
And S507, the second processor sends the decoded data in the RGB format.
Optionally, YCBCRWherein Y: brightness, i.e., gray scale value; cB: refers to the difference between the luminance values of the blue portion of the RGB input signal and the RGB input signal; cR: refer to RGB inputThe difference between the luminance values of the red part of the signal and the RGB input signal.
YCBCRAnd the conversion equation for RGB is as follows:
Y＝0.299R+0.587G+0.114B；
CB＝-0.1687R-0.3313G+0.5B+128；
CR＝0.5R-0.4187G-0.0813B+128；
R＝Y+1.402(CR-128)；
G＝Y-0.34414(CB-128)-0.71414(CR-128)；
B＝Y+1.772(CB-128)。
optionally, the first processor adopts a CPU, the second processor adopts an FPGA (Field Programmable Gate Array), the CPU is combined with the FPGA to implement heterogeneous decoding of an image to be decoded, the CPU end is mainly responsible for related tasks such as file header analysis, rearrangement of output results, and control of global pipeline, and the FPGA end is mainly responsible for parallel processing of decoding related tasks such as Huffman decoding, inverse quantization, and inverse DCT transform (inverse discrete cosine transform).
In the embodiment of the application, the second processor, for example, an FPGA (Field Programmable Gate Array) is used in cooperation with the first processor (for example, a CPU) to implement efficient hardware decoding on the image to be decoded, so that the decoding speed is high, the power consumption is low, and the comprehensive decoding cost is reduced.
The embodiment of the application can achieve the aim of saving storage and bandwidth cost when being applied to picture size conversion and compression.
When image decoding is performed on a plurality of images to be decoded, multi-path parallel decoding may be implemented in a multi-thread manner, and optionally, an embodiment of the present application further provides an image decoding method, as shown in fig. 6, the method includes the following steps:
s601, a first processor (CPU) acquires image data of a plurality of images to be decoded, wherein the image data comprises file header data.
And S602, the first processor executes analysis operation on the file header data to obtain analysis data and store the analysis data.
S603, the first processor transmits the image data and the analysis data of the images to be decoded to the second processor through a plurality of decoding threads respectively.
Optionally, the first processor (e.g., a CPU) starts a plurality of decoding threads by creating a buffer (i.e., defining a buffer class, which is used to create a buffer area specially used for storing binary data), and stores the parsed data in the created buffer.
S604, a second processor (FPGA) receives the analysis data and the image data of the file header data of the images to be decoded.
S605, decoding the image data by the second processor according to the received analytic data of the plurality of images to be decoded to obtain decoding data corresponding to the plurality of images to be decoded respectively.
S606, the second processor sends the decoding data to the first processor.
S607, the first processor generates a decoded image corresponding to each image to be decoded by using the received decoded data corresponding to the plurality of images to be decoded.
As shown in fig. 7, for a flowchart of an image decoding method provided in this embodiment of the present application, multi-path parallel decoding on multiple images to be decoded is implemented in a multi-thread manner, decoding operations on the multiple images to be decoded can be executed in parallel by multiple decoding threads, and an execution flow of each decoding thread is an interactive execution step of the first processor and the second processor.
According to the embodiment of the application, the multi-path parallel decoding of the multiple images to be decoded is realized in a multi-thread mode through interaction of the first processor and the second processor, so that the high-efficiency hardware decoding of the multiple images to be decoded is realized, the hardware decoding speed is high, the power consumption is low, and the comprehensive cost of image decoding is reduced.
As shown in fig. 8, an embodiment of the present application further provides an image decoding apparatus, including:
an obtaining unit 81 configured to obtain image data of an image to be decoded, where the image data includes header data;
and the analysis unit 82 is used for executing analysis operation on the header data to obtain analysis data and storing the analysis data.
A data transmitting unit 83 configured to transmit the analysis data and the image data;
a data receiving unit 84 for receiving decoded data corresponding to the image data;
an image generating unit 85 for generating a decoded image using the decoded data.
Optionally, the apparatus further comprises:
a pixel format data acquisition unit (not shown in the figure) for acquiring pixel format data of the decoded data;
a pixel format conversion unit (not shown in the figure) for performing pixel format conversion on the pixel format data according to components to obtain a plurality of pixel format component data;
and a splicing and combining unit (not shown in the figure) for splicing and combining the plurality of pixel format component data to obtain target pixel format data.
Optionally, the pixel format conversion unit (not shown in the figure) includes:
a data reading unit (not shown in the figure) for reading the pixel format data in components from the corresponding read addresses;
and a data storage unit (not shown) for storing the read data to the target write address.
As shown in fig. 9, an embodiment of the present application further provides an image decoding apparatus, including:
a data receiving unit 91 for receiving the parsing data of the header data of the image to be decoded and the image data;
a decoding unit 92, configured to decode the image data according to the analysis data to obtain decoded data;
a decoded data transmitting unit 93, configured to transmit the decoded data.
Optionally, the decoding unit 92 includes:
a huffman decoding subunit (not shown in the figure) for performing huffman decoding on the image data to obtain huffman decoded data;
a run-length decoding subunit (not shown in the figure) configured to perform run-length decoding on the huffman decoded data to obtain run-length decoded data;
an inverse quantization subunit (not shown in the figure), configured to perform inverse quantization on the run length decoded data to obtain inverse quantization data; and
and an inverse discrete cosine transform subunit (not shown in the figure) for performing inverse discrete cosine transform on the inverse quantized data to obtain decoded data.
Optionally, the apparatus further comprises:
a data format conversion unit (not shown) for converting the decoded data into YC by color space conversion formulaBCRThe format is converted to RGB format.
As shown in fig. 10, an embodiment of the present application further provides an image decoding apparatus, including:
a first processor 101, configured to obtain image data of an image to be decoded, where the image data includes header data; executing analysis operation on the file header data to obtain analysis data and storing the analysis data; transmitting the analysis data and the image data; receiving the decoded data; generating a decoded image using the decoded data;
a second processor 102 for receiving the parsed data and image data; decoding the image data according to the analysis data to obtain decoded data; and transmitting the decoded data.
An embodiment of the present application further provides a computer-readable storage medium, on which an image decoding program is stored, where the image decoding program, when executed by a processor, implements the steps of the image decoding method according to the embodiments of the method, for example, including:
acquiring image data of an image to be decoded, wherein the image data comprises file header data;
executing analysis operation on the file header data to obtain analysis data and storing the analysis data;
transmitting the analysis data and the image data;
receiving decoded data corresponding to the image data;
and generating a decoded image by using the decoded data.
An embodiment of the present application further provides a computer-readable storage medium, on which an image decoding program is stored, where the image decoding program, when executed by a processor, implements the steps of the image decoding method according to the embodiments of the method, for example, including:
receiving analysis data and image data of file header data of an image to be decoded;
decoding the image data according to the analysis data to obtain decoded data;
and transmitting the decoded data.
An embodiment of the present application further provides a computer-readable storage medium, on which an image decoding program is stored, where the image decoding program, when executed by a processor, implements the steps of the image decoding method according to the embodiments of the method, for example, including:
the first processor acquires image data of an image to be decoded, wherein the image data comprises file header data;
the first processor executes analysis operation on the file header data to obtain analysis data and store the analysis data;
the first processor sending the parsed data and the image data to the second processor;
the second processor receiving the parsed data and image data;
the second processor decodes the image data according to the analysis data to obtain decoded data;
the second processor sending the decoded data to the first processor;
the first processor receiving the decoded data;
the first processor generates a decoded image using the decoded data.
Fig. 11 is a schematic structural diagram of an electronic device according to another embodiment of the present invention. The electronic devices include mobile terminals such as mobile phones, tablet computers, notebook computers, palm computers, Personal Digital Assistants (PDAs), and the like, and fixed terminals such as Digital TVs, desktop computers, and the like. The electronic device 1100 shown in fig. 11 includes: at least one processor 1101, memory 1102, at least one network interface 1104, and other user interfaces 1103. The various components in the electronic device 1100 are coupled together by a bus system 1105. It is understood that the bus system 1105 is used to enable communications among the components. The bus system 1105 includes a power bus, a control bus, and a status signal bus in addition to a data bus. For clarity of illustration, however, the various buses are labeled in fig. 11 as the bus system 1105.
The user interface 1103 may include, among other things, a display, a keyboard, or a pointing device (e.g., a mouse, trackball, touch pad, or touch screen, among others.
It is to be understood that the memory 1102 in embodiments of the present invention can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. The non-volatile memory may be a Read-only memory (ROM), a programmable Read-only memory (PROM), an erasable programmable Read-only memory (erasabprom, EPROM), an electrically erasable programmable Read-only memory (EEPROM), or a flash memory. The volatile memory may be a Random Access Memory (RAM) which functions as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (staticiram, SRAM), dynamic random access memory (dynamic RAM, DRAM), synchronous dynamic random access memory (syncronous DRAM, SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), Enhanced synchronous SDRAM (ESDRAM), synchronous link SDRAM (SLDRAM), and direct memory bus SDRAM (DRRAM). The memory 1102 described herein is intended to comprise, without being limited to, these and any other suitable types of memory.
In some embodiments, memory 1102 stores elements, executable units or data structures, or a subset thereof, or an expanded set thereof as follows: an operating system 11021 and application programs 11022.
The operating system 11021 includes various system programs, such as a framework layer, a core library layer, a driver layer, and the like, for implementing various basic services and processing hardware-based tasks. The application 11022 contains various applications such as a media player (MediaPlayer), a Browser (Browser), and the like for implementing various application services. Programs that implement methods in accordance with embodiments of the invention may be included in application 11022.
In the embodiment of the present invention, by calling a program or an instruction stored in the memory 1102, specifically, a program or an instruction stored in the application 11022, the processor 1101 is configured to execute the method steps provided by the method embodiments, for example, including:
acquiring image data of an image to be decoded, wherein the image data comprises file header data;
executing analysis operation on the file header data to obtain analysis data and storing the analysis data;
transmitting the analysis data and the image data;
receiving decoded data corresponding to the image data;
and generating a decoded image by using the decoded data.
In the embodiment of the present invention, by calling a program or an instruction stored in the memory 1102, specifically, a program or an instruction stored in the application 11022, the processor 1101 is configured to execute the method steps provided by the method embodiments, for example, including:
receiving analysis data and image data of file header data of an image to be decoded;
decoding the image data according to the analysis data to obtain decoded data;
and transmitting the decoded data.
The methods disclosed in the embodiments of the present invention described above may be implemented in the processor 1101 or by the processor 1101. The processor 1101 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by instructions in the form of hardware, integrated logic circuits, or software in the processor 1101. The processor 1101 may be a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic device, or discrete hardware components. The various methods, steps and logic blocks disclosed in the embodiments of the present invention may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present invention may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software elements in the decoding processor. The software elements may be located in ram, flash, rom, prom, or eprom, registers, among other storage media that are well known in the art. The storage medium is located in the memory 1102, and the processor 1101 reads the information in the memory 1102 and completes the steps of the above method in combination with the hardware thereof.
It is to be understood that the embodiments described herein may be implemented in hardware, software, firmware, middleware, microcode, or any combination thereof. For a hardware implementation, the processing units may be implemented within one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), general purpose processors, controllers, micro-controllers, microprocessors, other electronic units configured to perform the functions described herein, or a combination thereof.
For a software implementation, the techniques described herein may be implemented by means of units performing the functions described herein. The software codes may be stored in a memory and executed by a processor. The memory may be implemented within the processor or external to the processor.
For convenience of description, the above devices are described as being divided into various units by function, and are described separately. Of course, the functions of the units may be implemented in the same software and/or hardware or in a plurality of software and/or hardware when implementing the invention.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for apparatus or system embodiments, since they are substantially similar to method embodiments, they are described in relative terms, as long as they are described in partial descriptions of method embodiments. The above-described embodiments of the apparatus and system are merely illustrative, and the units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The foregoing are merely exemplary embodiments of the present invention, which enable those skilled in the art to understand or practice the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (12)

1. An image decoding method, performed on a first processor, comprising:
acquiring image data of an image to be decoded, wherein the image data comprises file header data;
executing analysis operation on the file header data to obtain analysis data and storing the analysis data;
transmitting the analysis data and the image data;
receiving decoded data corresponding to the image data;
and generating a decoded image by using the decoded data.
2. The method of claim 1, wherein prior to generating a decoded image using the decoded data, the method further comprises:
acquiring pixel format data of the decoded data;
performing pixel format conversion on the pixel format data according to components to obtain a plurality of pixel format component data;
and splicing and combining the plurality of pixel format component data to obtain target pixel format data.
3. The method of claim 2, wherein said pixel-format converting said pixel-format data in components comprises:
reading the pixel format data in components from the corresponding read addresses;
and storing the read data to the target write address.
4. An image decoding method, performed on a second processor, comprising:
receiving analysis data and image data of file header data of an image to be decoded;
decoding the image data according to the analysis data to obtain decoded data;
and transmitting the decoded data.
5. The method of claim 4, wherein decoding the image data according to the parsed data to obtain decoded data comprises:
performing Huffman decoding on the image data to obtain Huffman decoding data;
performing stroke decoding on the Huffman decoding data to obtain stroke decoding data;
carrying out inverse quantization on the stroke decoding data to obtain inverse quantization data; and
and performing inverse discrete cosine transform on the inverse quantization data to obtain decoded data.
6. The method of claim 5, wherein prior to transmitting the decoded data, the method further comprises:
converting the decoded data from YC by color space conversion formulaBCRThe format is converted to RGB format.
7. An image decoding method, implemented in an electronic device having a first processor and a second processor disposed therein, the method comprising:
the first processor acquires image data of an image to be decoded, wherein the image data comprises file header data;
the first processor executes analysis operation on the file header data to obtain analysis data and store the analysis data;
the first processor sending the parsed data and the image data to the second processor;
the second processor receiving the parsed data and image data;
the second processor decodes the image data according to the analysis data to obtain decoded data;
the second processor sending the decoded data to the first processor;
the first processor receiving the decoded data;
the first processor generates a decoded image using the decoded data.
8. An image decoding apparatus, characterized in that the apparatus comprises:
the device comprises an acquisition unit, a decoding unit and a decoding unit, wherein the acquisition unit is used for acquiring image data of an image to be decoded, and the image data comprises file header data;
the analysis unit is used for executing analysis operation on the file header data to obtain analysis data and storing the analysis data;
a data transmitting unit configured to transmit the analysis data and the image data;
a data receiving unit for receiving decoded data corresponding to the image data;
and an image generation unit configured to generate a decoded image using the decoded data.
9. An image decoding apparatus, characterized in that the apparatus comprises:
the data receiving unit is used for receiving the analysis data of the file header data of the image to be decoded and the image data;
a decoding unit, configured to decode the image data according to the analysis data to obtain decoded data;
and a decoded data transmitting unit for transmitting the decoded data.
10. An image decoding apparatus, characterized in that the apparatus comprises:
the device comprises a first processor, a second processor and a third processor, wherein the first processor is used for acquiring image data of an image to be decoded, and the image data comprises file header data; executing analysis operation on the file header data to obtain analysis data and storing the analysis data; transmitting the analysis data and the image data; receiving the decoded data; generating a decoded image using the decoded data;
a second processor for receiving the parsed data and image data; decoding the image data according to the analysis data to obtain decoded data; and transmitting the decoded data.
11. An electronic device, characterized in that the electronic device comprises: at least one processor, memory, at least one network interface, and a user interface;
the at least one processor, memory, at least one network interface, and user interface are coupled together by a bus system;
the processor is configured to execute the steps of the image decoding method according to any one of claims 1 to 3, or claims 4 to 6, or claim 7 by calling a program or instructions stored in the memory.
12. A computer-readable storage medium, characterized in that an image decoding program is stored thereon, which when executed by a processor implements the steps of the image decoding method of any one of claims 1 to 3, or claims 4 to 6, or claim 7.
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