CN111314576B

CN111314576B - Analog video processing method

Info

Publication number: CN111314576B
Application number: CN201911192454.2A
Authority: CN
Inventors: 苗蔚; 常晨晨; 黄琴; 于小燕; 杨聚朋
Original assignee: Suzhou Changfeng Aviation Electronics Co Ltd
Current assignee: Suzhou Changfeng Aviation Electronics Co Ltd
Priority date: 2019-11-28
Filing date: 2019-11-28
Publication date: 2023-01-13
Anticipated expiration: 2039-11-28
Also published as: CN111314576A

Abstract

The invention discloses an analog video processing method, which adopts a decoding mode of a separating device to carry out processing such as clamping, filtering amplification, synchronous separation, phase-locked clock, A/D conversion and the like on an analog video signal, and converts the analog video signal into a digital signal with standard time sequence. An input PAL or NTSC standard video signal is automatically decoded into an RGB signal, and an enable signal DE, a line synchronization Hsync, a field synchronization Vsync signal and a pixel clock signal. The pixel clock signal is used as a time reference signal and is obtained from a composite synchronous signal of an input video through a phase-locked loop circuit in a phase-locked mode. The invention adopts the independent phase-locked loop circuit to adjust the frequency parameters according to the requirements of different vibration environments, thereby avoiding the clock jitter caused by resonance, improving the stability of the output clock phase of the voltage-controlled oscillator and avoiding the burrs of the image display.

Description

Analog video processing method

Technical Field

The invention relates to an analog video processing method, and belongs to the technical field of analog video processing methods in an airborne vibration environment.

Background

PAL and NTSC analog videos only need three signal lines of R, G and B to occupy smaller bandwidth, so that the PAL and NTSC analog videos have wide application in the field of onboard video transmission and are mainly used for transmitting pictures generated in real time such as cameras, aerial pictures and the like. The terminal receiving display device generally separates the synchronous and clock signals from the video for the analysis mode, samples and converts the analog RGB into digital signals by the separated clock, and then processes the digital signals for the post-stage circuit.

At present, a common method is to adopt special ICs such as ADV7403 and AD9985 to directly convert input analog video signals into digital RGB signals, but because the chip integrates the functions of A \ D sampling, synchronization, clock separation and the like, an internal configuration circuit is fixed and cannot be changed, when the digital RGB signals are used in a vibration environment such as take-off and landing of an aircraft, the vibration frequency is close to the frequency of an internal phase-locked loop of the chip, resonance can occur, the analyzed digital RGB signals can shake along with the shaking of the clock, and the phenomenon of boundary dynamic burrs can be shown on a picture to influence the observation. Therefore, an analog video processing circuit which can be adjusted in a vibration environment and avoid resonance with a phase-locked loop is needed to realize conversion from analog video to digital RGB so as to meet the use requirement in an airborne environment.

Disclosure of Invention

The invention aims to solve the defects of the prior art and provides an analog video processing method aiming at the problem that burrs exist on a display picture due to the fact that a traditional chip is fixed in an internal circuit and easy to resonate with a vibration environment.

In order to achieve the purpose, the technical scheme adopted by the invention is as follows:

an analog video processing method divides input RGB signals into two paths,

one path sends G video signals containing synchronous information to a synchronous separation circuit to separate field line synchronous signals of external video, the separated line synchronous signals generate pixel clock signals of the video signals through a phase-locked loop circuit, a control logic circuit obtains the required line synchronous signals, field synchronous signals and pixel clock signals,

the other path of RGB video signal is DC restored through a clamping circuit, and then amplified to a standard amplitude value through a filter amplifying circuit, the amplified video signal is input to a high-speed A/D converting circuit for analog-to-digital conversion, the input RGB analog signal is converted into each 8-bit digital signal of RGB, the digital signals are stored in a video memory under the control of a control logic circuit, and are uniformly converted into a display mode of 50HZ progressive scanning according to the standard time sequence output by the control logic circuit,

the phase-locked loop circuit is provided with an adjusting module for adjusting the stability of the output voltage of the phase discriminator in the phase-locked loop under different vibration frequencies.

Preferably, the adjusting module includes a capacitor and a resistor for filtering an input controlled oscillator voltage in the phase-locked loop circuit.

The method can adjust the configuration parameters of the phase-locked loop through the adjusting module so as to adapt to the stable display requirement of the analog video in the vibration environment, does not use a special integrated decoder, and adopts the decoding mode of a separating device to carry out clamping, filtering amplification, synchronous separation, phase-locked clock, A/D conversion and other processing on the analog video signal so as to convert the analog video signal into a digital signal with standard time sequence.

The analog video signal decoding circuit may automatically decode an input PAL or NTSC standard video signal into an RGB signal as well as an enable signal (DE), a line synchronization (Hsync) and field synchronization (Vsync) signal, and a pixel clock signal.

The pixel clock signal is used as a time reference signal and is obtained from a composite synchronous signal of an input video through a phase-locked loop circuit in a phase-locked mode. The signal has great influence on the video display quality, if the clock signal is jittered, the phenomenon of burr on the picture display can be caused, and the frequency parameter can be adjusted by adopting an independent phase-locked loop circuit according to the requirements of different vibration environments, so that the clock jitter caused by resonance is avoided.

The invention has the following beneficial effects:

the input voltage filter capacitor of the voltage-controlled oscillator inside the phase-locked loop chip can be debugged according to the environmental vibration frequency, the influence of vibration on the output voltage of the phase discriminator inside the phase-locked loop is reduced, the stability of the output clock phase of the voltage-controlled oscillator is improved, and burrs in picture display are avoided.

Drawings

FIG. 1 is a schematic block diagram of an analog video processing method of the present invention.

Fig. 2 is a circuit diagram of a phase-locked loop circuit in the present invention.

Detailed Description

The invention provides an analog video processing method. The technical solution of the present invention is described in detail below with reference to the accompanying drawings so that it can be more easily understood and appreciated.

In this embodiment, a standard 3-line PAL signal is used as a collection object and converted into a progressive signal that can be displayed on a liquid crystal display module.

Specifically, as shown in fig. 1, the input RGB signals are divided into two paths, the video signals in the main loop are subjected to dc restoration by a clamping circuit, the input video signals are uniformly clamped at a blanking level, filtered by an active filter composed of an operational amplifier after clamping, amplified to a standard amplitude by an amplifying circuit, and input to a high-speed a/D conversion circuit for analog-to-digital conversion, the input RGB analog signals are converted to 8-bit digital signals of RGB, and stored in a video memory under the control of a control logic circuit, and uniformly converted to a 50HZ progressive scanning display mode according to a standard timing sequence output by the logic circuit.

And the other video sends the G video signal containing the synchronous information to a synchronous separation circuit to separate a field line synchronous signal of the external video, and the separated line synchronous signal generates a pixel clock of the video signal through a phase-locked loop (DLL). Thus, the most basic line synchronizing signal, field synchronizing signal and pixel clock signal required by the sequential logic circuit can be generated based on the synchronizing information in the PAL video signal.

The above discussion has been directed to processing analog PAL video, a/D converted to digital RGB signals, while generating the necessary timing control and pixel clock signals to store the video data in a video memory for further processing by the graphics generation system.

As shown in fig. 2, the pll circuit mainly includes a pll chip CD74HC4046, a peripheral configuration resistor, and a capacitor, where a C38 capacitor is provided between

pins

6 and 7 of the pll chip, and a resistor is provided at pin 11, where the capacitor and the resistor can adjust the stability of output voltage of the phase discriminator inside the pll at different vibration frequencies, and perform a filtering function on the input voltage of the oscillator, and the capacitance and the resistance can be selected according to different output pixel clock frequencies, and the PAL video generally selects the capacitor 50pf and the resistor 4.2K Ω, and then can locally adjust the capacitance according to the external vibration environment, generally from 30pf to 100pf, so as to achieve the best video display effect.

Through the description, the analog video processing method can debug the input voltage filter capacitor of the voltage-controlled oscillator in the phase-locked loop chip according to the environmental vibration frequency, reduce the influence of vibration on the output voltage of the phase discriminator in the phase-locked loop, improve the stability of the output clock phase of the voltage-controlled oscillator and avoid the burr of image display.

The technical solutions of the present invention are fully described above, it should be noted that the specific embodiments of the present invention are not limited by the above description, and all technical solutions formed by equivalent or equivalent changes in structure, method, or function according to the spirit of the present invention by those skilled in the art are within the scope of the present invention.

Claims

1. An analog video processing method, characterized by:

the input RGB signal is divided into two paths,

the other path of RGB video signal is carried out DC restoration by a clamping circuit, the input video signal is uniformly clamped on a blanking level, after clamping, the input video signal is filtered by an active filter composed of an operational amplifier, then the video signal is amplified to a standard amplitude value by a filter amplifying circuit, the amplified video signal is input to a high-speed A/D conversion circuit for analog-to-digital conversion, the input RGB analog signal is converted into 8-bit digital signals of RGB, the digital signals are stored in a video memory under the control of a control logic circuit, and the digital signals are uniformly converted into a display mode of 50HZ progressive scanning according to a standard time sequence output by the control logic circuit,

the phase-locked loop circuit is provided with an adjusting module for adjusting the stability of the output voltage of the phase discriminator in the phase-locked loop under different vibration frequencies;

the adjusting module comprises a capacitor and a resistor which are used for filtering the voltage of an input controlled oscillator in the phase-locked loop circuit.