CN111313666B - High-reliability control device and system of high-power output channel - Google Patents
High-reliability control device and system of high-power output channel Download PDFInfo
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Abstract
The invention provides a high-reliability control device and a high-reliability control system of a high-power output channel, which comprise an FPGA controller, wherein the FPGA controller is connected with a bridge circuit, a Nios soft core and an IP core are embedded in the FPGA controller, and the Nios soft core and the IP core exchange information through an Avalon bus; the IP core comprises a PWM driving IP core, a fault processing IP core, a DA communication IP core and an AD communication IP core; the PWM drives the IP core and the fault processing IP core to be in communication connection; and the PWM driving IP core, the fault processing IP core, the DA communication IP core and the AD communication IP core exchange information with the Nios soft core through an Avalon bus respectively. The fault processing and monitoring circuit is connected with the FPGA controller and is used for processing the monitoring signal of the high-power output loop and then outputting a control signal to control and drive the high-power output loop through the bridge circuit.
Description
Technical Field
The invention relates to the technical field of control design of a high-power output channel, in particular to a high-reliability control device and system of the high-power output channel.
Background
With the development of embedded technology, the system integration level is increasingly improved, the function development is deepened continuously, the embedded type integrated. Especially in the power system automation industry, controlled terminals are mostly high-voltage heavy-current power switches (such as high-power electromagnetic relays, electromagnetic valves, IGBTs, MOSFETs, thyristors and the like), and once terminal equipment is out of control, faults such as short circuit, overcurrent and the like occur, current up to thousands of amperes can be generated instantly, the equipment is damaged, and the life safety of operators is endangered. Therefore, the reliability of the high power output channel is an indispensable part of the embedded system design.
The core chip of the traditional control system still adopts a singlechip, the working principle of the traditional control system is that an internal timer/counter is used for generating a required control signal, and the traditional control system has the defects of low frequency, poor adjustment precision of a duty ratio, easy generation of jitter of a phase position and the like. When multi-channel PWM output signals are needed, a plurality of single-chip microcomputers are needed, and the cost and complexity of the system are increased. The single chip microcomputer is in a serial working mode, namely only one operation can be executed at any time, and interrupt processing is needed when faults such as overcurrent and short circuit occur in the system. This approach appears to implement multitasking "parallel processing," which in fact increases program development difficulty and hides potential safety hazards:
(1) the circular query of the interrupt flag bit is completed by the main program of the single chip microcomputer, in order to shorten the flag query interval, the main program is required to be not too long, and designers need to consider how to optimize the program framework. The division of priority and interrupt nesting for multiple interrupts is also a troublesome problem in program development.
(2) The interrupt process is divided into three stages of interrupt response, interrupt processing and interrupt return. Complicated interrupt processing consumes a long time, and a main program in a serial working mode cannot be continuously executed downwards, so that functions of system communication, monitoring and the like are invalid, and a program is in a false dead state.
(3) The program is inevitably BUG and runs, and the control core is out of control at the moment and cannot judge and respond to the fault signal.
Disclosure of Invention
The invention provides a high-reliability control device and system of a high-power output channel based on an FPGA (field programmable gate array), aiming at the problems that a core chip of a traditional control system adopts a singlechip, and interrupt processing is required to be adopted when faults such as overcurrent and short circuit occur in the system, so that the program development difficulty is increased and potential safety hazards are hidden.
The technical scheme of the invention is as follows:
on one hand, the technical scheme of the invention provides a high-reliability control device of a high-power output channel, which comprises an FPGA controller, wherein the FPGA controller is connected with a bridge circuit and is used for controlling and driving a high-power output loop through the bridge circuit;
the device also comprises a fault processing and monitoring circuit, wherein the fault processing and monitoring circuit is connected with the FPGA controller and is used for processing the monitoring signal of the high-power output loop and then outputting a control signal to control and drive the high-power output loop through the bridge circuit.
Preferably, the bridge circuit comprises a PWM signal level conversion circuit, a VL reset signal level conversion circuit, and an IGBT driver board;
the FPGA controller is connected with the IGBT drive board through the PWM signal level conversion circuit and the VL reset signal level conversion circuit respectively and is used for converting the voltage output by the FPGA controller into an IGBT drive board input signal, and the IGBT drive board is used for receiving a control signal and driving and controlling a high-power output loop;
the IGBT drive board is connected with the FPGA controller and used for outputting a signal to the FPGA controller when a fault occurs so that the FPGA controller outputs a control signal to control the drive of the high-power output loop.
Preferably, the fault processing and monitoring circuit comprises a fault alarm circuit, a DA conversion module and an AD conversion module; the AD conversion module is connected with the FPGA controller and is used for receiving a monitoring signal of the high-power output loop, converting the monitoring signal into a digital quantity and inputting the digital quantity to the FPGA controller for algorithm processing and data output;
the DA conversion module and the fault alarm circuit are respectively connected with the FPGA controller and used for setting a monitored protection threshold value through the DA conversion module, and the fault alarm circuit receives a monitoring signal of the high-power output circuit and compares the monitoring signal with the protection threshold value set by the DA conversion module to output a signal to the FPGA controller.
Preferably, the apparatus further comprises a first power supply, a second power supply and a third power supply;
the PWM signal level conversion circuit comprises a first reset module and a first comparator; the first reset module is connected with the non-inverting input end of the first comparator; the output signal of the FPGA is connected with the non-inverting input end of a first comparator, the inverting input end of the first comparator is connected to a third power supply, the non-inverting input end of the first comparator is connected with the output end through a feedback resistor, and the output end of the first comparator is connected to the input end of an IGBT drive plate; the output end of the first comparator is connected with the anode of a diode D1, and the cathode of a diode D1 is connected with a delay circuit consisting of a resistor R1 and a capacitor C1; the second power supply is grounded via a resistor R1 and a capacitor C1 connected in series in this order, and the cathode of the diode D1 is connected to the connection point of the resistor R1 and the capacitor C1.
Preferably, the VL reset signal level conversion circuit includes a second reset module and an amplifying circuit; the second reset module is connected with the amplifying circuit;
the amplifying circuit is connected with the FPGA controller; the output end of the amplifying circuit is connected to the input end of the IGBT driving board.
Preferably, the fault alarm circuit comprises a second comparator, a non-inverting input end of the second comparator is connected to the DA conversion module, an inverting input end of the second comparator is used for connecting a monitoring signal of the high-power output loop, and an output end of the second comparator is connected to the FPGA controller.
The non-inverting input end of the second comparator is connected to the DA conversion module through a resistor R16, and the inverting input end of the second comparator is connected with a resistor R17 and used for connecting a monitoring signal of a high-power output loop; the output end of the second comparator is connected to the FPGA controller through a resistor R14; the first power supply is connected to the connection point of the resistor R14 and the FPGA controller through a resistor R13, and the non-inverting input end of the second comparator is connected to the output end of the second comparator through a resistor R15.
Preferably, a Nios soft core and an IP core are embedded in the FPGA controller, and the Nios soft core and the IP core exchange information through an Avalon bus;
the IP core comprises a PWM driving IP core, a fault processing IP core, a DA communication IP core and an AD communication IP core;
the PWM drives the IP core and the fault processing IP core to be in communication connection; and the PWM driving IP core, the fault processing IP core, the DA communication IP core and the AD communication IP core exchange information with the Nios soft core through an Avalon bus respectively.
Preferably, the device also comprises a CPLD chip, wherein the CPLD chip is connected with the FPGA controller and is used for carrying out logic conversion on the signals output by the FPGA;
the PWM drives the IP core to output a control signal to the PWM signal level conversion circuit through the CPLD chip;
the fault processing IP core outputs a control signal to the VL reset signal level conversion circuit through the CPLD chip; the IGBT drive board is connected with the fault processing IP core;
the fault processing IP core is connected with the fault alarm circuit; the fault alarm circuit is connected with the DA conversion module;
the DA conversion module is connected with the DA communication IP core;
the AD conversion module is connected with the AD communication IP core.
On the other hand, the technical scheme of the invention also provides a high-reliability control system of the high-power output channel, which comprises a main loop and a control device, wherein the control device is connected with the main loop; the main loop comprises a main control circuit and a monitoring module, and the monitoring module is arranged on the main control circuit; the monitoring module and the main control circuit are respectively connected with the control device; the control device is the high-reliability control device of the high-power output channel of the first aspect.
Preferably, the monitoring module comprises a voltage transformer and a current transformer which are arranged on the main control circuit;
the output signals of the voltage transformer and the current transformer are connected to the control device.
According to the technical scheme, the invention has the following advantages: the method has the advantages that the strict time sequence logic relation among driving signals is realized, the accurate timing of clock pulses of hundreds of megabytes is achieved, the dead time can be accurately adjusted within tens of nanoseconds, the direct connection fault of an H bridge is avoided, the multi-path fault processing IP core can immediately close the PWM driving IP core when monitoring the falling edge of various fault signals, and then fault information is latched and uploaded to an Avalon bus to carry out information interaction with Nios. The whole process takes tens of microseconds, and high-speed response of the fault signal is achieved. The reliability of the control system is comprehensively improved, and the product competitiveness is improved.
In addition, the invention has reliable design principle, simple structure and very wide application prospect.
Therefore, compared with the prior art, the invention has prominent substantive features and remarkable progress, and the beneficial effects of the implementation are also obvious.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
Fig. 1 is a connection block diagram of a high-reliability control device of a high-power output channel according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a master control loop according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of a PWM signal level conversion circuit.
Fig. 4 is a schematic diagram of VL reset signal level conversion circuit connection.
Fig. 5 is a schematic diagram of a fault alarm circuit connection.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As known to those skilled in the art, the FPGA/CPLD is in a parallel working mode, can realize real multitask operation through interconnection of internal logic gate circuits, and can simultaneously respond at high speed aiming at multiple fault signals. The FPGA/CPLD generates trigger pulses after receiving fault signals, a sequential logic circuit executes fault processing operation at high speed, simultaneously latches and uploads the fault signals to the MCU, the fault is subjected to primary processing (such as forced closing of a driving signal, emergency shutdown of a system and the like) by the FPGA/CPLD before the MCU enters interruption, and after the MCU collects fault information of each path and performs comprehensive analysis, a fault analysis report is uploaded and more complex fault processing operation is performed.
Example one
As shown in fig. 1, the technical solution of the present invention provides a high reliability control device of a high power output channel, which includes an FPGA controller, wherein the FPGA controller is connected to a bridge circuit for controlling and driving a high power output loop through the bridge circuit;
the device also comprises a fault processing and monitoring circuit, wherein the fault processing and monitoring circuit is connected with the FPGA controller and is used for processing the monitoring signal of the high-power output loop and then outputting a control signal to control and drive the high-power output loop through the bridge circuit. The FPGA is embedded with Nios soft cores and has a large amount of programmable logic resources. Nios is responsible for a system scheduling control algorithm, programmable logic is responsible for sequential logic control of multi-channel output and high-speed processing of fault signals, and the SOPC system architecture is similar to a collaborative design scheme of an MCU (microprogrammed control Unit) and an FPGA (field programmable gate array)/CPLD (complex programmable logic device). However, FPGA resource configuration is more flexible, and a simpler system architecture can be designed by freely customized IP core modular design. A Nios soft core and an IP core are embedded in the FPGA controller, and the Nios soft core and the IP core exchange information through an Avalon bus; the IP core comprises a PWM driving IP core, a fault processing IP core, a DA communication IP core and an AD communication IP core; the PWM drives the IP core and the fault processing IP core to be in communication connection; and the PWM driving IP core, the fault processing IP core, the DA communication IP core and the AD communication IP core exchange information with the Nios soft core through an Avalon bus respectively.
The bridge circuit comprises a PWM signal level switching circuit, a VL reset signal level switching circuit and an IGBT drive board;
the FPGA controller is connected with the IGBT drive board through a PWM signal level conversion circuit and a VL reset signal level conversion circuit respectively, the level conversion circuit lifts the +3.3V level of the FPGA output port to +15V as an IGBT drive board input signal, and the IGBT drive board is used for receiving a control signal and driving and controlling a high-power output loop;
the IGBT drive board is connected with the FPGA controller and used for outputting a signal to the FPGA controller when a fault occurs so that the FPGA controller outputs a control signal to control the drive of the high-power output loop.
The fault processing and monitoring circuit comprises a fault alarm circuit, a DA conversion module and an AD conversion module; the AD conversion module is connected with the FPGA controller and is used for receiving a monitoring signal of the high-power output loop, converting the monitoring signal into a digital quantity and inputting the digital quantity to the FPGA controller for algorithm processing and data output;
the DA conversion module and the fault alarm circuit are respectively connected with the FPGA controller and used for setting a monitored protection threshold Vref through the DA conversion module, and the fault alarm circuit receives a monitoring signal of the high-power output circuit and compares the monitoring signal with the protection threshold Vref set by the DA conversion module to output a signal to the FPGA controller. The device also comprises a CPLD chip which is connected with the FPGA controller and used for carrying out logic conversion on the signals output by the FPGA; the PWM drives the IP core to output a control signal to the PWM signal level conversion circuit through the CPLD chip; the fault processing IP core outputs a control signal to the VL reset signal level conversion circuit through the CPLD chip; the IGBT drive board is connected with the fault processing IP core; the fault processing IP core is connected with the fault alarm circuit; the fault alarm circuit is connected with the DA conversion module; the DA conversion module is connected with the DA communication IP core; the AD conversion module is connected with the AD communication IP core. PWM drives the IP core: 4 paths of PWM signals are output, interlocking logic is realized among the 4 paths of PWM signals, and the H bridge is prevented from being directly connected to cause IGBT breakdown. And (3) fault processing IP core: overcurrent, overvoltage and undervoltage protection functions are realized through the current and voltage sensors, and the state of the IGBT can be monitored and protected through the fault monitoring chip of the IGBT board. DA communication IP core: and D, digitally converting the analog IP core to realize a communication protocol of the FPGA and the DA conversion module. AD communication IP core: and the analog-to-digital IP core realizes a communication protocol between the FPGA and the AD conversion module.
The apparatus further comprises a first power supply, a second power supply, and a third power supply; in this embodiment, the fourth power output is +3.3 v; the second power output is +15 v; the third power output is +2.5 v.
As shown in fig. 3, the PWM signal level conversion circuit includes a reset module and a first comparator 101; the reset module is connected with the non-inverting input end of the first comparator 101 through a resistor R3; the FPGA output signal PWM1-4 is connected with the non-inverting input end of the first comparator 101, the inverting input end of the first comparator 101 is connected to +2.5v through a resistor R4, and the inverting input end of the first comparator 101 is grounded through a capacitor C2; the non-inverting input end of the first comparator 101 is connected with the output end through a feedback resistor R5; the output end of the first comparator 101 is connected to the input end of the IGBT driving board through a resistor R6; the output end of the first comparator 101 is connected with the anode of a diode D1, and the cathode of a diode D1 is connected with a delay circuit consisting of a resistor R1 and a capacitor C1; +15v is grounded through the resistor R1 and the capacitor C1 connected in series in sequence, and the anode of the diode D1 is grounded through the capacitor C3; the cathode of the diode D1 is connected to the junction of the resistor R1 and the capacitor C1. In this embodiment, the reset module includes a reset chip 103, the reset chip 103 is connected to a cathode of a diode D2, an anode of a diode D2 is connected to a non-inverting input terminal of the comparator through a resistor R3, and a cathode of a diode D2 is further grounded through a resistor R2; the reset chip 103 is also connected to +3.3 v.
As shown in fig. 4, the VL reset signal level conversion circuit includes a reset module and an amplifying circuit; the reset module is connected with the amplifying circuit;
the amplifying circuit is connected with the FPGA controller; the output end of the amplifying circuit is connected to the input end of the IGBT driving board. The amplifying circuit comprises a transistor T1 and a transistor T2; the base electrode of the triode T1 is connected to the output end of the FPGA controller through a resistor R8, the emitter electrode of the triode T1 is grounded, and the base electrode of the triode T1 is grounded through a resistor R9; the collector of the triode T1 is connected to the base of the triode T2 through a resistor R12, the base of the triode T2 is also connected to +15v through a resistor R11, the +15v is also connected to the emitter of the triode T2, and the collector of the triode T2 is connected to the input end of the IGBT drive board; the collector of the triode T2 is also grounded through a resistor R10; the reset module is connected to the base of the transistor T1;
the reset module comprises a reset chip 104, the reset chip 104 is connected with the cathode of a diode D3, the anode of a diode D3 is connected to the base of a triode T1, and the cathode of a diode D3 is also grounded through a resistor R7; the reset chip 104 is also connected to 3.3 v.
As shown in fig. 5, the fault alarm circuit includes a second comparator 102, a non-inverting input terminal of the second comparator 102 is connected to the DA conversion module through a resistor R16, and an inverting input terminal of the second comparator 102 is connected to a resistor R17, which is used for connecting a monitoring signal of the high-power output loop; the output end of the second comparator 102 is connected to the FPGA controller through a resistor R14; +3.3v is connected to the connection point of the resistor R14 and the FPGA controller through a resistor R13, and the non-inverting input terminal of the second comparator 102 is connected to the output terminal of the second comparator 102 through a resistor R15.
Example two
The technical scheme of the invention also provides a high-reliability control system of the high-power output channel, which comprises a main loop and a control device, wherein the control device is connected with the main loop; the main loop comprises a main control circuit and a monitoring module, and the monitoring module is arranged on the main control circuit; the monitoring module and the main control circuit are respectively connected with the control device; the control device is the high-reliability control device of the high-power output channel in the first embodiment.
The monitoring module comprises a voltage transformer and a current transformer which are arranged on the main control circuit; the output signals of the voltage transformer and the current transformer are connected to the control device.
As shown in figure 2, 2000V/400Hz alternating current is input into the main control circuit, and is converted into high-voltage direct current of about 2400V after being rectified by a diode and filtered by a capacitor, and is converted into alternating square wave with peak value of 4800V/2KHz through an H bridge inverter circuit formed by IGBTs, and the alternating square wave with frequency of 2KHz and different amplitudes is output according to different transformation ratios of transformers. The current transformers I1-I3 and the voltage transformers U1-U3 are used for monitoring the current and the voltage on the main loop. According to the master control circuit, the PWM signal level conversion circuit in the embodiment has 4 paths; the VL reset signal level conversion circuit is 2 paths; the corresponding IGBT drive board comprises a drive board I and a drive board II; the INA1-2 end of the driving board I is respectively connected with a PWM signal level conversion circuit; the INA3-4 end of the driving board II is respectively connected with a PWM signal level conversion circuit; the VL1 end of the driving plate I is connected with a VL reset signal level conversion circuit; the VL2 end of the driving plate II is connected with the other VL reset signal level conversion circuit; and the two-way output end PWM1 and PWM2 of the drive plate I and the two-way output end PWM3 and PWM4 of the drive plate II are respectively connected to the PWM1-4 end of the master control circuit. PWM drives the IP core: 4 paths of PWM signals are output, interlocking logic is realized among the 4 paths of PWM signals, and the H bridge is prevented from being directly connected to cause IGBT breakdown. And (3) fault processing IP core: overcurrent, overvoltage and undervoltage protection functions are realized through the current and voltage sensors, and the state of the IGBT can be monitored and protected through the fault monitoring chip of the IGBT board. DA communication IP core: and D, digitally converting the analog IP core to realize a communication protocol of the FPGA and the DA conversion module. AD communication IP core: and the analog-to-digital IP core realizes a communication protocol between the FPGA and the AD conversion module.
System power-on and low-voltage droop protection
The reset chip realizes power-on reset of the system and drive signal reset in low voltage drop, and the RC time delay circuit realizes power-on reset.
In this embodiment, taking the PWM signal level conversion circuit as an example:
when the system is powered on, the R1C1 forms a power-on delay circuit which can temporarily pull down the four paths of PWM signals INA 1-4, and the maintaining time is related to the R1C1 parameter selection.
The reset chip adopts MAX809, which is an effective reset chip with low level. The output RESET signal remains low for 140ms after the supply voltage rises to + 3.3V. Because the CPLD _ PWMs 1-4 and the RESET signal form an AND logic through a diode, when the RESET signal is at a low level, the input of the same-phase end of the comparator is about 0.3V (considering the conduction voltage drop of the diode), the reference voltage is less than +2.5V, the output of the comparator is 0V, and the output signals of the four-path PWM are pulled down.
Because the range of the power supply voltage of the MAX809 is similar to that of the FPGA, the same power supply can be adopted for supplying power. Taking the FPGA of Cyclone IV series as an example, when the core voltage VCCINT drops below 1.4V, the function of the FPGA cannot be guaranteed. MAX809SN232 with a threshold value of 2.32V can be selected as a RESET chip, when VCCINT is reduced to be lower than 2.32V, a RESET signal RESET is pulled down to 0V within 10us, and an output channel is locked before the FPGA is out of control. The existence of the pull-down resistor of the RESET pin ensures that the RESET signal can still be reliably pulled down even if VCCINT drops to 0V.
Multiple output channel strict time sequence logic implementation
The 4-path PWM drives the IP core to realize strict time sequence logic relation among driving signals, and the clock pulse of hundreds of megabytes can be accurately timed, so that dead time can be accurately adjusted within tens of nanoseconds, and the direct connection fault of an H bridge is avoided.
High speed response of fault signals
The IGBT drive board has short circuit and overcurrent monitoring functions, and Fault signals of the IGBT drive board are connected to the FPGA; after the IGBT driving board is in Fault, the Fault signal is pulled down to 0V within 1 us. The mutual inductor monitoring signal is compared with a protection threshold value set by the DA conversion module, and once the safety threshold value is exceeded, the LM293 of the comparator is pulled down to 0V within 1.3 us.
And when the fault processing IP core monitors the falling edge of each fault signal, the PWM driving IP core is immediately closed, and then fault information is latched and uploaded to an Avalon bus to carry out information interaction with Nios. The whole process takes tens of microseconds, and high-speed response of the fault signal is achieved.
Although the present invention has been described in detail by referring to the drawings in connection with the preferred embodiments, the present invention is not limited thereto. Various equivalent modifications or substitutions can be made on the embodiments of the present invention by those skilled in the art without departing from the spirit and scope of the present invention, and these modifications or substitutions are within the scope of the present invention/any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (9)
1. The high-reliability control device of the high-power output channel is characterized by comprising an FPGA controller, wherein the FPGA controller is connected with a bridge circuit and is used for controlling and driving a high-power output loop through the bridge circuit;
the device also comprises a fault processing and monitoring circuit, wherein the fault processing and monitoring circuit is connected with the FPGA controller and is used for processing the monitoring signal of the high-power output loop and then outputting a control signal to control and drive the high-power output loop through the bridge circuit;
the bridge circuit comprises a PWM signal level conversion circuit, a VL reset signal level conversion circuit and an IGBT drive board;
the FPGA controller is connected with the IGBT drive board through the PWM signal level conversion circuit and the VL reset signal level conversion circuit respectively and used for converting the voltage output by the FPGA controller into an IGBT drive board input signal, and the IGBT drive board is used for receiving a control signal and driving and controlling a high-power output loop;
the IGBT drive board is connected with the FPGA controller and is used for outputting a signal to the FPGA controller when a fault occurs so that the FPGA controller outputs a control signal to control the high-power output loop;
the device also comprises a CPLD chip which is connected with the FPGA controller and used for carrying out logic conversion on the signals output by the FPGA and outputting control signals to the PWM signal level conversion circuit and the VL reset signal level conversion circuit.
2. The high-reliability control device of a high-power output channel according to claim 1, wherein the fault processing and monitoring circuit comprises a fault alarm circuit, a DA conversion module and an AD conversion module; the AD conversion module is connected with the FPGA controller and is used for receiving a monitoring signal of the high-power output loop, converting the monitoring signal into a digital quantity and inputting the digital quantity to the FPGA controller for algorithm processing and data output;
the DA conversion module and the fault alarm circuit are respectively connected with the FPGA controller and used for setting a monitored protection threshold value through the DA conversion module, and the fault alarm circuit receives a monitoring signal of the high-power output circuit and compares the monitoring signal with the protection threshold value set by the DA conversion module to output a signal to the FPGA controller.
3. The high reliability control device of a high power output channel according to claim 1, further comprising a first power supply, a second power supply and a third power supply;
the PWM signal level conversion circuit comprises a first reset module and a first comparator; the first reset module is connected with the non-inverting input end of the first comparator; an output signal of the FPGA controller is connected with a non-inverting input end of a first comparator, an inverting input end of the first comparator is connected to a third power supply, the non-inverting input end of the first comparator is connected with an output end of the first comparator through a feedback resistor, and an output end of the first comparator is connected to an input end of an IGBT drive board; the output end of the first comparator is connected with the anode of a diode D1, and the cathode of a diode D1 is connected with a delay circuit consisting of a resistor R1 and a capacitor C1; the second power supply is grounded via a resistor R1 and a capacitor C1 connected in series in this order, and the cathode of the diode D1 is connected to the connection point of the resistor R1 and the capacitor C1.
4. The apparatus as claimed in claim 3, wherein the VL reset signal level converting circuit includes a second reset block and an amplifying circuit; the second reset module is connected with the amplifying circuit; the amplifying circuit is connected with the FPGA controller; the output end of the amplifying circuit is connected to the input end of the IGBT driving board.
5. The high reliability control device of a high power output channel as claimed in claim 2, wherein the fault alarm circuit comprises a second comparator, the non-inverting input terminal of the second comparator is connected to the DA conversion module, the inverting input terminal of the second comparator receives the monitoring signal of the high power output loop, and the output terminal of the second comparator is connected to the FPGA controller.
6. The high-reliability control device of a high-power output channel according to claim 2, characterized in that a Nios soft core and an IP core are embedded in the FPGA controller, and the Nios soft core and the IP core exchange information through an Avalon bus;
the IP core comprises a PWM driving IP core, a fault processing IP core, a DA communication IP core and an AD communication IP core;
the PWM drives the IP core and the fault processing IP core to be in communication connection; and the PWM driving IP core, the fault processing IP core, the DA communication IP core and the AD communication IP core exchange information with the Nios soft core through an Avalon bus respectively.
7. The high reliability control device of a high power output channel according to claim 6, wherein the PWM driving IP core outputs the control signal to the PWM signal level conversion circuit through the CPLD chip;
the fault processing IP core outputs a control signal to the VL reset signal level conversion circuit through the CPLD chip; the IGBT drive board is connected with the fault processing IP core;
the fault processing IP core is connected with the fault alarm circuit; the fault alarm circuit is connected with the DA conversion module;
the DA conversion module is connected with the DA communication IP core;
the AD conversion module is connected with the AD communication IP core.
8. A high-reliability control system of a high-power output channel is characterized by comprising a main loop and a control device, wherein the control device is connected with the main loop; the main loop comprises a main control circuit and a monitoring module, and the monitoring module is arranged on the main control circuit; the monitoring module and the main control circuit are respectively connected with the control device; the control device is a high-reliability control device of a high-power output channel in any one of claims 1 to 7.
9. The high reliability control system of a high power output channel of claim 8, wherein the monitoring module comprises a voltage transformer and a current transformer arranged on the main control circuit;
the output signals of the voltage transformer and the current transformer are connected to the control device.
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