CN111308933A - Internet of things data acquisition system based on FPGA - Google Patents
Internet of things data acquisition system based on FPGA Download PDFInfo
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Abstract
The invention discloses an FPGA-based data acquisition system of the Internet of things, which comprises an FPGA processing module, a CAN bus interface module, a USB bus interface module, a serial interface module, an Ethernet bus interface module and a power supply module; the FPGA processing module is respectively connected with the CAN bus interface module, the USB bus interface module, the serial interface module, the Ethernet bus interface module and the power supply module; according to the technical scheme, the data acquisition system is improved, and the data acquisition efficiency of the system is improved.
Description
Technical Field
The invention relates to the technical field of industrial field data acquisition, in particular to an Internet of things data acquisition system based on an FPGA.
Background
In the field of industrial control, in order to realize information interaction between control layer software and industrial field device hardware, data acquisition modes of the existing industrial control system are more and more diversified.
However, the data acquired by the existing data acquisition system of the internet of things is relatively single, and usually only ethernet interface data and an RS232 interface protocol can be acquired, and the data acquisition efficiency is low, and meanwhile, the existing data acquisition system of the internet of things adopts a CPU processor, so that the system can process the data of the next interface module only after the data corresponding to the interface module is processed at the same time, and the system has poor real-time performance, long data processing time and low efficiency.
Disclosure of Invention
The embodiment of the invention provides an FPGA-based data acquisition system of the Internet of things, which aims to solve the technical problem of single data acquisition mode of the existing Internet of things.
In order to solve the technical problem, an embodiment of the present invention provides an internet of things data acquisition system based on an FPGA, including:
the system comprises an FPGA processing module, a CAN bus interface module, a USB bus interface module, a serial interface module, an Ethernet bus interface module and a power supply module; the FPGA processing module is respectively connected with the CAN bus interface module, the USB bus interface module, the serial interface module, the Ethernet bus interface module and the power supply module.
As a preferred scheme, the FPGA processing module comprises an FPGA circuit and a debugging circuit;
the FPGA circuit is respectively connected with the debugging circuit, the CAN bus interface module, the USB bus interface module, the serial port interface module, the Ethernet bus interface module and the power supply module.
As a preferred scheme, the serial port interface module includes an RS422 circuit, wherein the RS422 circuit includes an RS422 chip, a first transient diode, a second transient diode, a third transient diode, a fourth transient diode, and a first connector;
the second end of the RS422 chip and the third end of the RS422 chip are respectively connected with the FPGA circuit;
a fifth end of the RS422 chip is connected to the first end of the fourth transient diode and the fourth end of the first connector, respectively; a sixth end of the RS422 chip is connected to the first end of the third transient diode and the third end of the first connector, respectively;
a seventh end of the RS422 chip is respectively connected with a first end of the second transient diode and a second end of the first connector; the eighth end of the RS422 chip is respectively connected with the first end of the first transient diode and the first end of the first connector;
the second terminal of the first transient diode, the second terminal of the second transient diode, the second terminal of the third transient diode, and the second terminal of the fourth transient diode are respectively grounded.
As a preferred scheme, the serial interface module comprises an RS485 circuit, wherein the RS485 circuit comprises an RS485 chip, a fifth transient diode, a sixth transient diode, a seventh transient diode, and a second connector;
the first end of the RS485 chip, the second end of the RS485 chip, the third end of the RS485 chip and the fourth end of the RS485 chip are respectively connected with the FPGA circuit;
a sixth end of the RS485 chip is connected to the first end of the fifth transient diode, the first end of the seventh transient diode, and the first end of the second connector, respectively;
a seventh end of the RS485 chip is connected to the second end of the fifth transient diode, the first end of the sixth transient diode, and the second end of the second connector, respectively;
a second terminal of the sixth transient diode and a second terminal of the seventh transient diode are respectively grounded.
As a preferred scheme, the serial port interface module includes an RS232 circuit, where the RS232 circuit includes an RS232 chip, an eighth transient diode, a ninth transient diode, a tenth transient diode, an eleventh transient diode, a third connector, and a fourth connector;
a seventh end of the RS232 chip is connected to the first end of the ninth transient diode and the third end of the fourth connector, respectively; an eighth end of the RS232 chip is connected to the first end of the eighth transient diode and the second end of the fourth connector, respectively;
a thirteenth end of the RS232 chip is connected to the first end of the tenth transient diode and the third end of the third connector respectively; a fourteenth end of the RS232 chip is connected to the first end of the eleventh transient diode and the second end connected to the third connector, respectively;
the ninth end of the RS232 chip, the tenth end of the RS232 chip and the twelfth end of the RS232 chip are respectively connected with the FPGA circuit;
a second terminal of the eighth transient diode, a second terminal of the ninth transient diode, a second terminal of the tenth transient diode, and a second terminal of the eleventh transient diode are respectively grounded.
As a preferred scheme, the CAN bus interface module includes a CAN bus chip, a common-mode inductor, a first chip inductor, a second chip inductor, a first general diode, a second general diode, a third general diode, a fourth general diode, a fifth general diode, a sixth general diode, a twelfth transient diode, a first discharge tube, a second discharge tube, a first resistor, a first capacitor, and a fifth connector;
the fourth end of the CAN bus chip and the fifth end of the CAN bus chip are respectively connected with the FPGA circuit; a fifteenth end of the CAN bus chip is connected with the second end of the common-mode inductor; the seventeenth end of the CAN bus chip is connected with the first end of the common-mode inductor;
the third end of the common-mode inductor is connected with the first end of the third general diode, the first end of the fourth general diode, the first end of the second discharge tube and the second end of the fifth connector through the second patch inductor respectively;
a fourth end of the common mode inductor is connected with a first end of the first general diode, a first end of the second general diode, a first end of the first discharge tube and a first end of the fifth connector through the first patch inductor;
a second end of the first universal diode is connected with a first end of the fifth universal diode, a first end of the twelfth transient diode and a second end of the third universal diode respectively;
a second end of the second general diode is connected with a first end of the sixth general diode, a second end of the twelfth transient diode and a second end of the fourth general diode respectively;
the second end of the first discharge tube is respectively connected with the second end of the second discharge tube, the first end of the first resistor, the first end of the first capacitor and the third end of the fifth connector;
a second end of the fifth general diode, a second end of the sixth general diode, a second end of the first resistor, and a second end of the first capacitor are grounded, respectively.
Preferably, the USB bus interface module includes a USB chip and a sixth connector;
the first end of the USB chip and the third end of the USB chip are respectively connected with the sixth connector; and the fourth end of the USB chip and the sixth end of the USB chip are respectively connected with the FPGA circuit.
As a preferred scheme, the ethernet bus interface module includes an ethernet communication chip, an ethernet transformer, and a first storage chip;
the third end of the Ethernet communication chip, the fourth end of the Ethernet communication chip, the sixth end of the Ethernet communication chip and the seventh end of the Ethernet communication chip are respectively connected with the Ethernet transformer;
a tenth end of the ethernet communication chip, a twelfth end of the ethernet communication chip, and a thirteenth end of the ethernet communication chip are respectively connected to the first memory chip;
and a seventeenth end of the Ethernet communication chip, an eighteenth end of the Ethernet communication chip, a nineteenth end of the Ethernet communication chip, a twentieth end of the Ethernet communication chip, a twenty-fourth end of the Ethernet communication chip and a twenty-seventh end of the Ethernet communication chip are respectively connected with the FPGA circuit.
As a preferred scheme, the data acquisition system of the internet of things based on the FPGA further comprises a storage module, wherein the storage module comprises an SD card seat;
the first end of the SD card seat, the second end of the SD card seat, the fifth end of the SD card seat and the seventh end of the SD card seat are respectively connected with the FPGA circuit.
As a preferred scheme, the data acquisition system of the internet of things based on the FPGA further comprises an expansion RAM module, and the RAM module comprises a second storage chip in circuit connection with the FPGA.
The embodiment of the invention has the following beneficial effects:
the FPGA-based data acquisition system of the Internet of things comprises an FPGA processing module, a CAN bus interface module, a USB bus interface module, a serial interface module, an Ethernet bus interface module and a power supply module; the FPGA processing module is respectively connected with the CAN bus interface module, the USB bus interface module, the serial interface module, the Ethernet bus interface module and the power supply module. Compared with the prior art that the CPU processing module is adopted to process the data of the Internet of things, the technical scheme of the invention CAN collect the TCP/IP protocol, the CAN protocol, the USB network protocol and the serial port communication protocol, has high data collection efficiency, and simultaneously the Ethernet bus interface module, the CAN bus interface module, the USB bus interface module and the serial port interface module are all connected with the FPGA processing module, thereby being beneficial to realizing the sharing of information of each module and improving the transmission efficiency of the information.
Drawings
Fig. 1 is a schematic structural diagram of a first embodiment of an FPGA-based data acquisition system of the internet of things provided by the present invention;
FIG. 2 is a schematic structural diagram of an FPGA module provided by the present invention;
FIG. 3 is a schematic diagram of a RS422 circuit provided by the present invention;
FIG. 4 is a schematic structural diagram of an RS485 circuit provided by the invention;
FIG. 5 is a schematic diagram of an RS232 circuit provided by the present invention;
FIG. 6 is a schematic structural diagram of a CAN bus interface module provided by the present invention;
FIG. 7 is a schematic structural diagram of a USB bus interface module according to the present invention;
FIG. 8 is a schematic structural diagram of an Ethernet bus interface module provided by the present invention;
FIG. 9 is a schematic structural diagram of a memory module provided by the present invention;
FIG. 10 is a schematic structural diagram of an extended RAM module provided in the present invention;
fig. 11 is a schematic structural diagram of a power supply module provided by the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The first embodiment:
fig. 1 is a schematic structural diagram of an embodiment of the data acquisition system of the internet of things based on the FPGA according to the present invention. The system method comprises the following steps: the system comprises an FPGA processing module 1, a CAN bus interface module 2, a USB bus interface module 3, a serial interface module 4, an Ethernet bus interface module 5 and a power supply module 6; the FPGA processing module 1 is respectively connected with the CAN bus interface module 2, the USB bus interface module 3, the serial interface module 4, the Ethernet bus interface module 5 and the power supply module 6.
In this embodiment, the CAN bus interface module 2 is configured to receive a CAN protocol of ISO 15765; the USB bus interface module 3 is used for receiving a USB network protocol; the serial port interface module 4 is used for receiving a serial port communication protocol; the Ethernet bus interface module 5 is used for receiving a TCP/IP protocol; the FPGA processing module 1 is used for summarizing the received communication protocols, converting the summarized communication protocols into OPC UA protocols, and directly uploading the OPC UA protocols to a local server or a cloud server through an Ethernet port so as to realize the same management of various equipment data; the FPGA processing module 1 is also used for converting an OPC UA protocol into a target protocol and transmitting the target protocol to equipment from a related port, so that information sharing among the equipment is realized, and further, the integration of industrial field data is realized; the FPGA processing module 1 can also control the equipment connected with the interface module by controlling the related interface module, thereby realizing the unified control and management of the industrial field equipment.
As CAN be seen from the above, the system for acquiring data of the internet of things based on the FPGA provided by the embodiment of the invention comprises an FPGA processing module 1, a CAN bus interface module 2, a USB bus interface module 3, a serial interface module 4, an ethernet bus interface module 5 and a power supply module 6; the FPGA processing module 1 is respectively connected with the CAN bus interface module 2, the USB bus interface module 3, the serial interface module 4, the Ethernet bus interface module 5 and the power supply module 6. Compared with the prior art that the CPU processing module is adopted to process the data of the Internet of things, the technical scheme of the invention CAN collect the TCP/IP protocol, the CAN protocol, the USB network protocol and the serial port communication protocol, has high data collection efficiency, and simultaneously the Ethernet bus interface module 5, the CAN bus interface module 2, the USB bus interface module 3 and the serial port interface module 4 are all connected with the FPGA processing module 1, thereby being beneficial to realizing the sharing of all information and improving the transmission efficiency of the information.
In one of the preferred embodiments, referring to fig. 2, the FPGA processing module 1 includes an FPGA circuit and a debugging circuit; the FPGA circuit is respectively connected with the debugging circuit, the CAN bus interface module 2, the USB bus interface module 3, the serial interface module 4, the Ethernet bus interface module 5 and the power supply module 6. It should be noted that, in fig. 2, the first FPGA chip U5A, the second FPGA chip U5B, the third FPGA chip U5C, the fourth FPGA chip U5D, the fifth FPGA chip U5E, the sixth FPGA chip U5F, the seventh FPGA chip U5G, the eighth FPGA chip U5H, the ninth FPGA chip U5I, and the tenth FPGA chip U5J are all the same FPGA chip, and are divided into several parts for convenience of understanding.
In this embodiment, each power pin of the FPGA chip has a decoupling capacitor (a 0.1uF ceramic patch capacitor in fig. 2) for improving the stability and the anti-interference capability of the chip. The debugging circuit is a J-Link circuit and is used for debugging programs in the system and inputting the programs into the FPGA chip.
In this embodiment, the FPGA chip may convert the received communication protocol into an OPC UA protocol and directly upload the OPC UA protocol to the local server or the cloud server through the ethernet port, and the FPGA chip may further convert the received communication protocol into the OPC UA protocol and then convert the OPC UA protocol into other target protocols, and send the target protocols from other ports, for example, when a first device connected to the USB bus interface module 3 wants to acquire data of a second device connected to the CAN bus interface module 2, the FPGA chip converts the CAN protocol of ISO15765 sent by the second device into the OPC UA protocol, the FPGA chip converts the OPC UA protocol into the USB network protocol, and sends the USB network protocol to the first device through the USB bus interface module 3, thereby implementing information sharing.
In one preferred embodiment, please refer to fig. 3, the serial interface module 4 includes an RS422 circuit for receiving a communication protocol of the RS 422; the RS422 circuit comprises an RS422 chip U1, a first transient diode D1, a second transient diode D2, a third transient diode D3, a fourth transient diode D4 and a first connector P1;
the second end of the RS422 chip U1 and the third end of the RS422 chip U1 are respectively connected with the FPGA circuit; a fifth terminal of the RS422 chip U1 is connected to the first terminal of the fourth transient diode D4 and the fourth terminal of the first connector P1, respectively; the sixth terminal of the RS422 chip U1 is connected to the first terminal of the third transient diode D3 and the third terminal of the first connector P1, respectively; the seventh terminal of the RS422 chip U1 is connected to the first terminal of the second transient diode D2 and the second terminal of the first connector P1, respectively; the eighth terminal of the RS422 chip U1 is connected to the first terminal of the first transient diode D1 and the first terminal of the first connector P1, respectively; the second terminal of the first transient diode D1, the second terminal of the second transient diode D2, the second terminal of the third transient diode D3, and the second terminal of the fourth transient diode D4 are respectively grounded.
In this embodiment, four transient diodes, i.e., a first transient diode D1, a second transient diode D2, a third transient diode D3, and a fourth transient diode D4, are added to the RS422 circuit, so that the interference rejection capability of the bus is improved.
In one preferred embodiment, please refer to fig. 4, the serial interface module 4 includes an RS485 circuit for receiving a communication protocol of RS485, wherein the RS485 circuit includes an RS485 chip U2, a fifth transient diode D5, a sixth transient diode D6, a seventh transient diode D7, and a second connector P2;
the first end of the RS485 chip U2, the second end of the RS485 chip U2, the third end of the RS485 chip U2 and the fourth end of the RS485 chip U2 are respectively connected with an FPGA circuit; a sixth terminal of the RS485 chip U2 is connected to the first terminal of the fifth transient diode D5, the first terminal of the seventh transient diode D7, and the first terminal of the second connector P2, respectively; a seventh terminal of the RS485 chip U2 is connected to the second terminal of the fifth transient diode D5, the first terminal of the sixth transient diode D6, and the second terminal of the second connector P2, respectively; the second terminals of the sixth transient diode D6 and the seventh transient diode D7 are grounded, respectively.
In this embodiment, a fifth transient diode D5, a sixth transient diode D6, and a seventh transient diode D7 are added to the RS485 circuit, and these three transient diodes improve the interference rejection capability of the bus.
In one preferred embodiment, please refer to fig. 5, the serial interface module 4 includes an RS232 circuit for receiving a communication protocol of RS 232; the RS232 circuit comprises an RS232 chip U3, an eighth transient diode D8, a ninth transient diode D9, a tenth transient diode D10, an eleventh transient diode D11, a third connector P3 and a fourth connector P4;
the seventh end of the RS232 chip U3 is connected to the first end of the ninth transient diode D9 and the third end of the fourth connector P4, respectively; the eighth end of the RS232 chip U3 is connected to the first end of the eighth transient diode D8 and the second end of the fourth connector P4, respectively; the thirteenth terminal of the RS232 chip U3 is connected to the first terminal of the tenth transient diode D10 and the third terminal of the third connector P3, respectively; a fourteenth end of the RS232 chip U3 is connected to the first end of the eleventh transient diode D11 and the second end of the third connector P3, respectively; the ninth end of the RS232 chip U3, the tenth end of the RS232 chip U3, the tenth end of the RS232 chip U3 and the twelfth end of the RS232 chip U3 are respectively connected with the FPGA circuit, and the second end of the eighth transient diode D8, the second end of the ninth transient diode D9, the second end of the tenth transient diode D10 and the second end of the eleventh transient diode D11 are grounded.
In this embodiment, four transient diodes, i.e., an eighth transient diode D8, a ninth transient diode D9, a tenth transient diode D10, and an eleventh transient diode D11, are added to the RS232 circuit, so that the interference rejection capability of the bus is improved.
In one preferred embodiment, referring to fig. 6, the CAN bus interface module 2 includes a CAN bus chip U4, a common mode inductor LC1, a first chip inductor L1, a second chip inductor L2, a first general diode D1, a second general diode D2, a third general diode D3, a fourth general diode D4, a fifth general diode D5, a sixth general diode D6, a twelfth transient diode D12, a first discharge tube G1, a second discharge tube G2, a first resistor R41, a first capacitor C58, and a fifth connector P5;
the fourth end of the CAN bus chip U4 and the fifth end of the CAN bus chip U4 are respectively connected with the FPGA circuit; the fifteenth end of the CAN bus chip U4 is connected with the second end of the common-mode inductor LC 1; the seventeenth end of the CAN bus chip U4 is connected with the first end of the common-mode inductor LC 1; a third end of the common mode inductor LC1 is connected to a first end of a third pass diode d3, a first end of a fourth pass diode d4, a first end of a second discharge tube G2, and a second end of a fifth connector P5 through a second chip inductor L2; a fourth end of the common mode inductor LC1 is connected to a first end of the first general diode d1, a first end of the second general diode d2, a first end of the first discharge tube G1 and a first end of the fifth connector P5 through the first chip inductor L1; a second terminal of the first general diode D1 is connected to a first terminal of a fifth general diode D5, a first terminal of a twelfth transient diode D12, and a second terminal of a third general diode D3, respectively; a second terminal of the second universal diode D2 is connected to a first terminal of a sixth universal diode D6, a second terminal of a twelfth transient diode D12, and a second terminal of a fourth universal diode D4, respectively; the second end of the first discharge tube G1 is respectively connected with the second end of the second discharge tube G2, the first end of the first resistor R41, the first end of the first capacitor C58 and the third end of the fifth connector P5; a second terminal of the fifth general diode d5, a second terminal of the sixth general diode d6, a second terminal of the first resistor R41, and a second terminal of the first capacitor C58 are grounded.
In this embodiment, a first universal diode D1, a second universal diode D2, a third universal diode D3, a fourth universal diode D4, a fifth universal diode D5, a sixth universal diode D6, a twelfth transient diode D12, a first discharge tube G1, a second discharge tube G2, a first resistor R41 and a first capacitor C58 are added to the CAN bus interface module 2, so as to protect the circuit and improve the anti-interference capability of the bus.
In one preferred embodiment, please refer to fig. 7, the USB bus interface module 3 includes a USB chip U5, a sixth connector P6; the first end of the USB chip U5 and the third end of the USB chip U5 are respectively connected with the sixth connector P6; the fourth end of the USB chip U5 and the sixth end of the USB chip U5 are respectively connected with the FPGA circuit. It should be noted that the USB chip U5 adopts a USB lc6 chip, which is a combination chip of transient diodes, and the anti-interference capability of the bus can be effectively improved by the chip.
In one preferred embodiment, referring to fig. 8, the ethernet bus interface module 5 includes an ethernet communication chip U6, an ethernet transformer U7, and a first memory chip U8;
the third end of the Ethernet communication chip U6, the fourth end of the Ethernet communication chip U6, the sixth end of the Ethernet communication chip U6 and the seventh end of the Ethernet communication chip U6 are respectively connected with an Ethernet transformer U7; the tenth end of the ethernet communication chip U6, the twelfth end of the ethernet communication chip U6, and the thirteenth end of the ethernet communication chip U6 are connected to the first memory chip U8, respectively; the seventeenth end of the ethernet communication chip U6, the eighteenth end of the ethernet communication chip U6, the nineteenth end of the ethernet communication chip U6, the twentieth end of the ethernet communication chip U6, the twenty-fourth end of the ethernet communication chip U6, and the twenty-seventh end of the ethernet communication chip U6 are respectively connected to the FPGA circuit.
In this embodiment, the anti-interference capability of the bus is improved by the ethernet communication chip U6, the ethernet transformer U7, the first memory chip U8, 8 0.1uF ceramic chip capacitors, 1 25MHz crystal oscillator, 2 47uF tantalum capacitors for filtering, 2 20pF crystal oscillator oscillation starting capacitors, 7 4.7K ohm chip resistors, 3 510 ohm resistors, 4 49.9 ohm chip resistors, 1 10K ohm chip resistors, and 1 6.8K ohm chip resistors.
In one preferred embodiment, please refer to fig. 9, the data acquisition system of the internet of things based on the FPGA further includes a storage module, configured to store configuration parameters of the system and the user, and configured to save the configuration parameters in case of power failure and read the configuration parameters in case of power failure; the storage module comprises an SD card socket U9; the first end of the SD card socket U9, the second end of the SD card socket U9, the fifth end of the SD card socket U9 and the seventh end of the SD card socket U9 are respectively connected with an FPGA circuit.
In one preferred embodiment, please refer to fig. 10, the data acquisition system of the internet of things based on the FPGA further includes an extended RAM module, and the extended RAM module is used for storing real-time operation data of the system, so as to improve the operation efficiency of the system. The RAM module comprises a second memory chip U10 connected with the FPGA circuit. It should be noted that, in fig. 10, 7 decoupling capacitors are used to improve the stability and the anti-interference capability of the chip.
In one preferred embodiment, referring to fig. 11, the power supply module 6 includes a first power circuit, a second power circuit, and a third power circuit; the first power supply circuit comprises a first power conversion chip U11, a light emitting diode LED2, a fourteenth capacitor C14, a fifteenth capacitor C15, a twentieth capacitor C20, a twenty-first capacitor C21 and a twenty-second capacitor C22;
a first end of the first power conversion chip U11 is connected to a first power supply, a first end of the light emitting diode LED2, a first end of the fourteenth capacitor C14, and a first end of the fifteenth capacitor C15, respectively; the second end of the first power supply chip is respectively connected with the second end of the fourteenth capacitor C14 and the second end of the fifteenth capacitor C15; a fourth end of the first power conversion chip U11 is connected to a first end of a twenty-first capacitor C21, a first end of a twenty-second capacitor C22 and a ground line through a twentieth capacitor C20; a fifth end of the first power conversion chip U11 is connected to the second power supply, a second end of the twenty-first capacitor C21, and a second end of the twenty-second capacitor C22, respectively;
the second terminal of the LED2 is grounded through a twentieth resistor, and it should be noted that the second power circuit and the third power circuit have substantially the same structure as the first power circuit, except that the power conversion chips of the second power circuit and the third power circuit do not need to be connected to the LED 2.
In this embodiment, the power supply module 6 is connected to the FPGA processing module 1, specifically, the first power supply 5.0V, the second power supply 3.3V, the third power supply 2.5V, the fourth power supply 1.2V is respectively connected to the FPGA processing module 1, the power supply module 6 supplies power to the FPGA processing module 1, the CAN bus interface module 2, the USB bus interface module 3, the serial interface module 4, the ethernet bus interface module 5, the storage module, and the extended RAM module through the FPGA processing module 1.
As CAN be seen from the above, the system for acquiring data of the internet of things based on the FPGA provided by the embodiment of the invention comprises an FPGA processing module 1, a CAN bus interface module 2, a USB bus interface module 3, an RS422 circuit, an RS485 circuit, an RS232 circuit, an ethernet bus interface module 5, a power supply module 6, a storage module and an extended RAM module; the FPGA processing module 1 is respectively connected with the CAN bus interface module 2, the USB bus interface module 3, the RS422 circuit, the RS485 circuit, the RS232 circuit, the Ethernet bus interface module 5, the power supply module 6, the storage module and the expansion RAM module. Compared with the existing data acquisition monitoring system of the Internet of things, the data acquisition monitoring system has the advantages that the anti-interference capability among the data acquisition modules is strong, the modules are not interfered with one another, and the data acquisition efficiency of the system is further improved.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.
Claims (10)
1. The utility model provides a thing networking data acquisition system based on FPGA which characterized in that includes: the system comprises an FPGA processing module, a CAN bus interface module, a USB bus interface module, a serial interface module, an Ethernet bus interface module and a power supply module; the FPGA processing module is respectively connected with the CAN bus interface module, the USB bus interface module, the serial interface module, the Ethernet bus interface module and the power supply module.
2. The FPGA-based data acquisition system of the Internet of things of claim 1, wherein the FPGA processing module comprises an FPGA circuit and a debugging circuit;
the FPGA circuit is respectively connected with the debugging circuit, the CAN bus interface module, the USB bus interface module, the serial port interface module, the Ethernet bus interface module and the power supply module.
3. The FPGA-based data acquisition system of the Internet of things as claimed in claim 2, wherein the serial port interface module comprises an RS422 circuit, wherein the RS422 circuit comprises an RS422 chip, a first transient diode, a second transient diode, a third transient diode, a fourth transient diode and a first connector;
the second end of the RS422 chip and the third end of the RS422 chip are respectively connected with the FPGA circuit;
a fifth end of the RS422 chip is connected to the first end of the fourth transient diode and the fourth end of the first connector, respectively; a sixth end of the RS422 chip is connected to the first end of the third transient diode and the third end of the first connector, respectively;
a seventh end of the RS422 chip is respectively connected with a first end of the second transient diode and a second end of the first connector; the eighth end of the RS422 chip is respectively connected with the first end of the first transient diode and the first end of the first connector;
the second terminal of the first transient diode, the second terminal of the second transient diode, the second terminal of the third transient diode, and the second terminal of the fourth transient diode are respectively grounded.
4. The FPGA-based data acquisition system of the Internet of things as claimed in claim 2, wherein the serial port interface module comprises an RS485 circuit, wherein the RS485 circuit comprises an RS485 chip, a fifth transient diode, a sixth transient diode, a seventh transient diode and a second connector;
the first end of the RS485 chip, the second end of the RS485 chip, the third end of the RS485 chip and the fourth end of the RS485 chip are respectively connected with the FPGA circuit;
a sixth end of the RS485 chip is connected to the first end of the fifth transient diode, the first end of the seventh transient diode, and the first end of the second connector, respectively;
a seventh end of the RS485 chip is connected to the second end of the fifth transient diode, the first end of the sixth transient diode, and the second end of the second connector, respectively;
a second terminal of the sixth transient diode and a second terminal of the seventh transient diode are respectively grounded.
5. The FPGA-based data acquisition system of the Internet of things of claim 1, wherein the serial port interface module comprises an RS232 circuit, wherein the RS232 circuit comprises an RS232 chip, an eighth transient diode, a ninth transient diode, a tenth transient diode, an eleventh transient diode, a third connector, and a fourth connector;
a seventh end of the RS232 chip is connected to the first end of the ninth transient diode and the third end of the fourth connector, respectively; an eighth end of the RS232 chip is connected to the first end of the eighth transient diode and the second end of the fourth connector, respectively;
a thirteenth end of the RS232 chip is connected to the first end of the tenth transient diode and the third end of the third connector respectively; a fourteenth end of the RS232 chip is connected to the first end of the eleventh transient diode and the second end connected to the third connector, respectively;
the ninth end of the RS232 chip, the tenth end of the RS232 chip and the twelfth end of the RS232 chip are respectively connected with the FPGA circuit;
a second terminal of the eighth transient diode, a second terminal of the ninth transient diode, a second terminal of the tenth transient diode, and a second terminal of the eleventh transient diode are respectively grounded.
6. The FPGA-based data acquisition system of the Internet of things of claim 1, wherein the CAN bus interface module comprises a CAN bus chip, a common mode inductor, a first patch inductor, a second patch inductor, a first universal diode, a second universal diode, a third universal diode, a fourth universal diode, a fifth universal diode, a sixth universal diode, a twelfth transient diode, a first discharge tube, a second discharge tube, a first resistor, a first capacitor, and a fifth connector;
the fourth end of the CAN bus chip and the fifth end of the CAN bus chip are respectively connected with the FPGA circuit; a fifteenth end of the CAN bus chip is connected with the second end of the common-mode inductor; the seventeenth end of the CAN bus chip is connected with the first end of the common-mode inductor;
the third end of the common-mode inductor is connected with the first end of the third general diode, the first end of the fourth general diode, the first end of the second discharge tube and the second end of the fifth connector through the second patch inductor respectively;
a fourth end of the common mode inductor is connected with a first end of the first general diode, a first end of the second general diode, a first end of the first discharge tube and a first end of the fifth connector through the first patch inductor;
a second end of the first universal diode is connected with a first end of the fifth universal diode, a first end of the twelfth transient diode and a second end of the third universal diode respectively;
a second end of the second general diode is connected with a first end of the sixth general diode, a second end of the twelfth transient diode and a second end of the fourth general diode respectively;
the second end of the first discharge tube is respectively connected with the second end of the second discharge tube, the first end of the first resistor, the first end of the first capacitor and the third end of the fifth connector;
a second end of the fifth general diode, a second end of the sixth general diode, a second end of the first resistor, and a second end of the first capacitor are grounded, respectively.
7. The FPGA-based data acquisition system of the Internet of things as claimed in claim 2, wherein the USB bus interface module comprises a USB chip and a sixth connector;
the first end of the USB chip and the third end of the USB chip are respectively connected with the sixth connector; and the fourth end of the USB chip and the sixth end of the USB chip are respectively connected with the FPGA circuit.
8. The FPGA-based data acquisition system of the Internet of things of claim 2, wherein the Ethernet bus interface module comprises an Ethernet communication chip, an Ethernet transformer, a first memory chip;
the third end of the Ethernet communication chip, the fourth end of the Ethernet communication chip, the sixth end of the Ethernet communication chip and the seventh end of the Ethernet communication chip are respectively connected with the Ethernet transformer;
a tenth end of the ethernet communication chip, a twelfth end of the ethernet communication chip, and a thirteenth end of the ethernet communication chip are respectively connected to the first memory chip;
and a seventeenth end of the Ethernet communication chip, an eighteenth end of the Ethernet communication chip, a nineteenth end of the Ethernet communication chip, a twentieth end of the Ethernet communication chip, a twenty-fourth end of the Ethernet communication chip and a twenty-seventh end of the Ethernet communication chip are respectively connected with the FPGA circuit.
9. The FPGA-based IOT data acquisition system of any one of claims 2 to 8 further comprising a storage module, wherein the storage module comprises an SD card socket;
the first end of the SD card seat, the second end of the SD card seat, the fifth end of the SD card seat and the seventh end of the SD card seat are respectively connected with the FPGA circuit.
10. The FPGA-based IOT data acquisition system of any one of claims 2 to 8 further comprising an extended RAM module including a second memory chip in circuit connection with the FPGA.
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Citations (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100289653A1 (en) * | 2008-02-07 | 2010-11-18 | Rosario Sam Calio | Air sampling system |
| CN202205078U (en) * | 2011-05-30 | 2012-04-25 | 上海聚美物联网科技有限公司 | Multi-channel data acquisition equipment |
| CN102930742A (en) * | 2012-11-01 | 2013-02-13 | 江苏大为科技股份有限公司 | Circuit structure of ultrasonic parking place detector |
| CN103257624A (en) * | 2013-03-03 | 2013-08-21 | 侯志伟 | Multichannel high-speed data acquisition system of internet of things |
| CN103389670A (en) * | 2013-07-31 | 2013-11-13 | 成都电业局双流供电局 | Data acquisition and power monitoring device for transformer station |
| CN103647801A (en) * | 2013-11-18 | 2014-03-19 | 东莞理工学院 | Data collector applied to real-time quality monitoring at traditional industrial site |
| CN203951178U (en) * | 2014-07-02 | 2014-11-19 | 乐星产电(无锡)有限公司 | There is the touch-screen of the USB port technology of ESD safeguard function |
| CN104166038A (en) * | 2014-07-07 | 2014-11-26 | 李辉 | Self-monitoring device used for railway choke transformer |
| CN204046638U (en) * | 2014-08-19 | 2014-12-24 | 成都熊谷加世电器有限公司 | For the CAN communication circuit of welding equipment |
| CN204406848U (en) * | 2015-02-12 | 2015-06-17 | 山东华翼微电子技术股份有限公司 | Based on the checking development board of double FPGA chip |
| CN204498143U (en) * | 2015-02-15 | 2015-07-22 | 北京工业大学 | A kind of FPGA module of bus Internet of Things peace control terminal |
| CN105046902A (en) * | 2014-11-17 | 2015-11-11 | 中环天仪股份有限公司 | Remote calorimeter concentrator having multiple communication modes |
| CN205195750U (en) * | 2015-12-20 | 2016-04-27 | 天津市南开太阳高技术发展有限公司 | Charge hardware circuit of a controller of motor vehicle |
| CN105759664A (en) * | 2014-12-17 | 2016-07-13 | 陕西培元电子科技有限公司 | GPS monitoring terminal based on FPGA |
| US20160286286A1 (en) * | 2015-03-23 | 2016-09-29 | SmarTower Systems, LLC | Remote tower monitoring |
| CN106057695A (en) * | 2016-06-14 | 2016-10-26 | 苏州微控智芯半导体科技有限公司 | Wafer test system and test method |
| CN206332623U (en) * | 2016-11-16 | 2017-07-14 | 广东省智能制造研究所 | A kind of matrix rectification circuit |
| CN207460215U (en) * | 2017-11-22 | 2018-06-05 | 深圳市昊岳科技有限公司 | One kind is based on automotive electronics CAN network anti-jamming circuit |
| CN108279601A (en) * | 2018-01-26 | 2018-07-13 | 武汉理工大学 | A kind of multi-channel digital TT＆C system based on I2C+CAN buses |
| CN207965557U (en) * | 2018-01-25 | 2018-10-12 | 北京智行鸿远汽车有限公司 | A kind of CAN interface circuit that interference rejection ability is strong |
| CN208015747U (en) * | 2018-02-26 | 2018-10-26 | 中车青岛四方机车车辆股份有限公司 | Non-intervention type multiprotocol network data acquisition device |
| CN109194679A (en) * | 2018-09-25 | 2019-01-11 | 北京航空航天大学 | A kind of multi-protocol interface data acquisition device and acquisition method based on SpaceFibre interface |
| CN208423874U (en) * | 2018-07-19 | 2019-01-22 | 广州市少创信息科技有限公司 | A kind of usb circuit of educational robot |
| CN208723891U (en) * | 2018-09-13 | 2019-04-09 | 广州朔月电子科技有限公司 | Things-internet gateway |
| CN110428600A (en) * | 2019-08-12 | 2019-11-08 | 湘潭大学 | A kind of gas sensor data acquisition and wireless system for transmitting data based on FPGA |
| CN209710114U (en) * | 2019-07-08 | 2019-11-29 | 成都艾普特云物联网科技有限公司 | A kind of industry intelligent networking gateway device |
| CN210019379U (en) * | 2019-03-22 | 2020-02-07 | 成都开图医疗系统科技有限公司 | Medical X-ray machine framework based on CAN OPEN bus modularization |
-
2020
- 2020-02-25 CN CN202010116184.3A patent/CN111308933B/en active Active
Patent Citations (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100289653A1 (en) * | 2008-02-07 | 2010-11-18 | Rosario Sam Calio | Air sampling system |
| CN202205078U (en) * | 2011-05-30 | 2012-04-25 | 上海聚美物联网科技有限公司 | Multi-channel data acquisition equipment |
| CN102930742A (en) * | 2012-11-01 | 2013-02-13 | 江苏大为科技股份有限公司 | Circuit structure of ultrasonic parking place detector |
| CN103257624A (en) * | 2013-03-03 | 2013-08-21 | 侯志伟 | Multichannel high-speed data acquisition system of internet of things |
| CN103389670A (en) * | 2013-07-31 | 2013-11-13 | 成都电业局双流供电局 | Data acquisition and power monitoring device for transformer station |
| CN103647801A (en) * | 2013-11-18 | 2014-03-19 | 东莞理工学院 | Data collector applied to real-time quality monitoring at traditional industrial site |
| CN203951178U (en) * | 2014-07-02 | 2014-11-19 | 乐星产电(无锡)有限公司 | There is the touch-screen of the USB port technology of ESD safeguard function |
| CN104166038A (en) * | 2014-07-07 | 2014-11-26 | 李辉 | Self-monitoring device used for railway choke transformer |
| CN204046638U (en) * | 2014-08-19 | 2014-12-24 | 成都熊谷加世电器有限公司 | For the CAN communication circuit of welding equipment |
| CN105046902A (en) * | 2014-11-17 | 2015-11-11 | 中环天仪股份有限公司 | Remote calorimeter concentrator having multiple communication modes |
| CN105759664A (en) * | 2014-12-17 | 2016-07-13 | 陕西培元电子科技有限公司 | GPS monitoring terminal based on FPGA |
| CN204406848U (en) * | 2015-02-12 | 2015-06-17 | 山东华翼微电子技术股份有限公司 | Based on the checking development board of double FPGA chip |
| CN204498143U (en) * | 2015-02-15 | 2015-07-22 | 北京工业大学 | A kind of FPGA module of bus Internet of Things peace control terminal |
| US20160286286A1 (en) * | 2015-03-23 | 2016-09-29 | SmarTower Systems, LLC | Remote tower monitoring |
| CN205195750U (en) * | 2015-12-20 | 2016-04-27 | 天津市南开太阳高技术发展有限公司 | Charge hardware circuit of a controller of motor vehicle |
| CN106057695A (en) * | 2016-06-14 | 2016-10-26 | 苏州微控智芯半导体科技有限公司 | Wafer test system and test method |
| CN206332623U (en) * | 2016-11-16 | 2017-07-14 | 广东省智能制造研究所 | A kind of matrix rectification circuit |
| CN207460215U (en) * | 2017-11-22 | 2018-06-05 | 深圳市昊岳科技有限公司 | One kind is based on automotive electronics CAN network anti-jamming circuit |
| CN207965557U (en) * | 2018-01-25 | 2018-10-12 | 北京智行鸿远汽车有限公司 | A kind of CAN interface circuit that interference rejection ability is strong |
| CN108279601A (en) * | 2018-01-26 | 2018-07-13 | 武汉理工大学 | A kind of multi-channel digital TT＆C system based on I2C+CAN buses |
| CN208015747U (en) * | 2018-02-26 | 2018-10-26 | 中车青岛四方机车车辆股份有限公司 | Non-intervention type multiprotocol network data acquisition device |
| CN208423874U (en) * | 2018-07-19 | 2019-01-22 | 广州市少创信息科技有限公司 | A kind of usb circuit of educational robot |
| CN208723891U (en) * | 2018-09-13 | 2019-04-09 | 广州朔月电子科技有限公司 | Things-internet gateway |
| CN109194679A (en) * | 2018-09-25 | 2019-01-11 | 北京航空航天大学 | A kind of multi-protocol interface data acquisition device and acquisition method based on SpaceFibre interface |
| CN210019379U (en) * | 2019-03-22 | 2020-02-07 | 成都开图医疗系统科技有限公司 | Medical X-ray machine framework based on CAN OPEN bus modularization |
| CN209710114U (en) * | 2019-07-08 | 2019-11-29 | 成都艾普特云物联网科技有限公司 | A kind of industry intelligent networking gateway device |
| CN110428600A (en) * | 2019-08-12 | 2019-11-08 | 湘潭大学 | A kind of gas sensor data acquisition and wireless system for transmitting data based on FPGA |
Non-Patent Citations (5)
| Title |
|---|
| 《世界电子元器件》: "CAN采用了隔离依旧通讯异常怎么办?", 《世界电子元器件》 * |
| FLY_CORE: "DM9051参考电路图", 《HTTPS://WENKU.BAIDU.COM/VIEW/BCC2AA41F02D2AF90242A8956BEC0975F465A4DD.HTML》 * |
| LIUJJ05: "MAX3232E电路中存在上拉电阻和稳压二极管，作用是什么？", 《HTTP://BBS.EEWORLD.COM.CN/THREAD-457980-1-1.HTML》 * |
| 张家顺子: "RS422-485接口电路设计要点", 《HTTPS://BLOG.CSDN.NET/ZHANGSHUN5233/ARTICLE/DETAILS/90112690》 * |
| 玩转单片机: "RS485收发的3种常用典型电路图文解析", 《HTTP://WWW.ELECFANS.COM/D/853959.HTML》 * |
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