CN111294040B - Reconfigurable combinational logic unit based on static circuit - Google Patents
Reconfigurable combinational logic unit based on static circuit Download PDFInfo
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- CN111294040B CN111294040B CN202010084822.8A CN202010084822A CN111294040B CN 111294040 B CN111294040 B CN 111294040B CN 202010084822 A CN202010084822 A CN 202010084822A CN 111294040 B CN111294040 B CN 111294040B
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
Abstract
The reconfigurable logic unit based on the static circuit comprises a control transistor and a logic transistor, wherein the grid electrode of the control transistor is an input end of a control signal, the on-off state of different control transistors can be changed by adjusting the control signal, so that the topology structure of a pull-up network or a pull-down network is changed to realize different logic functions, the grid electrode of the logic transistor is an input end of data, the input signal is kept unchanged under different logic functions, and the control complexity of the logic unit is reduced to the greatest extent. By inputting the specific control signal to the unit, the invention realizes the selection of different logic functions and the multiplexing of hardware resources in time, thereby increasing the utilization efficiency of hardware and reducing the hardware cost.
Description
Technical Field
The present invention relates to digital integrated circuits, and more particularly to a reconfigurable combinational logic cell based on static circuits.
Background
In front-end design of digital integrated circuits, replacement of standard cells is performed on the design at stage ECO (Engineering Changing Order) using spare standard cells (spares). In general, a standard cell can only realize one logic function, and has insufficient flexibility in modification, and in this context, a standard cell capable of realizing multiple logic functions can provide more flexible functions;
meanwhile, in recent years, the security of digital chips is becoming a focus of industry attention, and hardware attack and hacking based on layout analysis make the functions of circuits easy to be revealed, so that intellectual property rights of designers are infringed. The design adopts the design thought of hardware confusion (hardware camouflage) and can realize function confusion on the layout level, so that the design is difficult to analyze specific functions from the layout level.
Disclosure of Invention
The invention mainly aims to provide a reconfigurable combinational logic unit which can resist hardware attacks based on layout analysis.
In order to achieve the above purpose, the technical solution of the present invention is as follows:
a reconfigurable combination logic unit consists of a plurality of control transistors and a plurality of logic transistors, wherein the grid electrodes of the control transistors are input ends of control signals, and the on-off states of different control transistors can be changed by adjusting the control signals, so that the topology structure of a pull-up network or a pull-down network is changed to realize different logic functions. The grid electrode of the logic transistor is a data input end, and under different logic functions, input signals are kept unchanged, so that the control complexity of the logic unit is reduced to the greatest extent.
The logic circuit comprises a control transistor and a logic transistor;
the logic transistor includes: the first P-type logic transistor, the second P-type logic transistor, the third P-type logic transistor, the fourth P-type logic transistor, the fifth P-type logic transistor, the sixth P-type logic transistor, the seventh P-type logic transistor, the eighth P-type logic transistor, the first N-type logic transistor, the second N-type logic transistor, the third N-type logic transistor, the fourth N-type logic transistor, the fifth N-type logic transistor, the sixth N-type logic transistor, the seventh N-type logic transistor and the eighth N-type logic transistor;
the drain electrode of the first P-type logic transistor is connected with the source electrode of the second P-type logic transistor, and the drain electrode of the first P-type logic transistor is connected with the power supply in series to form a first pull-up network; the drain electrode of the third P-type logic transistor is connected with the source electrode of the fourth P-type logic transistor, and the drain electrode of the third P-type logic transistor is connected with the power supply in series to form a second pull-up network; the drain electrode of the fifth P-type logic transistor is connected with the source electrode of the sixth P-type logic transistor, a third pull-up network is formed by connecting the drain electrode of the fifth P-type logic transistor with the source electrode of the sixth P-type logic transistor in series, and the source electrode of the fifth P-type logic transistor is connected with the power supply; the drain electrode of the seventh P-type logic transistor is connected with the source electrode of the eighth P-type logic transistor, and the drain electrode of the seventh P-type logic transistor is connected with the power supply in series to form a fourth pull-up network;
the drain electrode of the second N-type logic transistor is connected with the source electrode of the first N-type logic transistor in series to form a first pull-down network, and the drain electrode of the second N-type logic transistor is connected with the ground; the drain electrode of the fourth N-type logic transistor is connected with the source electrode of the third N-type logic transistor in series to form a second pull-down network, and the drain electrode of the fourth N-type logic transistor is connected with the ground; the drain electrode of the sixth N-type logic transistor is connected with the source electrode of the fifth N-type logic transistor in series to form a third pull-down network, and the drain electrode of the sixth N-type logic transistor is connected with the ground; the drain electrode of the eighth N-type logic transistor is connected with the source electrode of the seventh N-type logic transistor, and the drain electrode of the eighth N-type logic transistor is connected with the ground in series to form a fourth pull-down network;
the control transistor includes: the first P-type control transistor, the second P-type control transistor, the third P-type control transistor, the fourth P-type control transistor, the first N-type control transistor, the second N-type control transistor, the third N-type control transistor and the fourth N-type control transistor;
the first P-type control transistor controls the on-off of a first pull-up network formed by a first P-type logic transistor and a second P-type logic transistor, and when the first P-type control transistor is turned on, an output end Q is connected with a power supply through the first pull-up network;
the first N-type control transistor controls the on-off of a first pull-down network consisting of a first N-type logic transistor and a second N-type logic transistor, and when the first N-type control transistor is turned on, an output end Q is connected with the ground through the first pull-down network;
the second P-type control transistor controls the on-off of a second pull-up network consisting of a third P-type logic transistor and a fourth P-type logic transistor, and when the second P-type control transistor is turned on, an output end Q is connected with a power supply through the second pull-up network;
the second N-type control transistor controls the on-off of a second pull-down network consisting of a third N-type logic transistor and a fourth N-type logic transistor, and when the second N-type control transistor is turned on, the output end Q is connected with the ground through the second pull-down network;
the third P-type control transistor controls the on-off of a third pull-up network consisting of a fifth P-type logic transistor and a sixth P-type logic transistor, and when the third P-type control transistor is turned on, an output end Q is connected with a power supply through the third pull-up network;
the third N-type control transistor controls the on-off of a third pull-down network consisting of a fifth N-type logic transistor and a sixth N-type logic transistor, and when the third N-type control transistor is turned on, the output end Q is connected with the ground through the third pull-down network;
the fourth P-type control transistor controls the on-off of a fourth pull-up network of a pull-up network formed by a seventh P-type logic transistor and an eighth P-type logic transistor, and when the fourth P-type control transistor is turned on, an output end Q is connected with a power supply through the fourth pull-up network of the pull-up network;
the fourth N-type control transistor controls the on-off of a fourth pull-down network composed of a seventh N-type logic transistor and an eighth N-type logic transistor, and when the fourth N-type control transistor is turned on, the output end Q is connected with the ground through the fourth pull-down network.
The symmetry of the metal layer is utilized to ensure that the metal layer is immune to hardware cracking or attack based on layout analysis. In the layout layer, aiming at hardware attack and cracking, the layout of the proposed logic unit is optimized, the metal layer is highly symmetrical in the layout, and the functions of the logic unit are difficult to distinguish by means of photography and the like. And because the reconfigurable unit can realize multiple logic functions, a plurality of logic modules realizing different functions also have the same layout design, and the safety of the design has great improvement and advantage compared with the safety of the traditional standard unit.
Compared with the prior art, the invention has the following beneficial effects:
after the reconfigurable logic unit provided by the invention is inserted in the rear end design stage of the digital integrated circuit, when engineering modification occurs, different logic function selections can be realized by inputting a specific control signal into the unit, and compared with the traditional standby standard unit, the reconfigurable logic unit has greater flexibility.
In the front-end design of the digital integrated circuit, the reconfigurable logic unit can be used, and the function switching of the logic unit is realized when the chip runs through the configuration of control signals on time sequence, so that the multiplexing of hardware resources in time is realized, the utilization efficiency of hardware is increased, and the hardware cost is reduced.
The reconfigurable logic unit is specially optimized on the layout level, so that an attacker is difficult to acquire the function of the reconfigurable logic unit by analyzing the layout, and the hardware safety is protected.
Drawings
The invention is further illustrated by the following examples in conjunction with the accompanying drawings:
FIG. 1 is a circuit diagram of an embodiment of a static circuit based reconfigurable cell of the present invention;
FIG. 2 is an equivalent circuit of the static logic unit according to the present invention when configured as exclusive OR logic;
FIG. 3 is an equivalent circuit of the static logic unit according to the present invention when configured as an OR logic;
FIG. 4 is an equivalent circuit of a static logic cell according to the present invention configured as NAND logic;
FIG. 5 is an equivalent circuit of a static logic cell according to the present invention when configured as NOR logic;
FIG. 6 is an equivalent circuit of a static logic cell according to the present invention when configured as AND logic;
FIG. 7 is an equivalent circuit of a static logic cell according to the present invention when configured as OR logic;
FIG. 8 is a metal layer of a static circuit based reconfigurable cell layout of the present invention;
Detailed Description
Referring to fig. 1, fig. 1 is a circuit diagram of an embodiment of a reconfigurable unit based on a static circuit according to the present invention, and the reconfigurable unit based on a static circuit according to the present invention includes a first P-type control transistor 103, a first N-type control transistor 104, a second P-type control transistor 109, a second N-type control transistor 110, a third P-type control transistor 115, a third N-type control transistor 116, a fourth P-type control transistor 121, and a fourth N-type control transistor 122 as control transistors, wherein the transistor 101, the second P-type logic transistor 102, the first N-type logic transistor 105, the second N-type logic transistor 106, the third P-type logic transistor 107, the fourth P-type logic transistor 108, the third N-type logic transistor 111, the fourth N-type logic transistor 112, the fifth P-type logic transistor 113, the sixth P-type logic transistor 114, the fifth N-type logic transistor 117, the sixth N-type logic transistor 118, the seventh P-type logic transistor 119, and the eighth N-type logic transistor 120. The gate of the control transistor is the input end of the control signal, and the gate of the logic transistor is the input end of the operation data.
The whole reconfigurable logic unit has four groups of pull-up networks, numbered as a first pull-up network 125, a second pull-up network 127, a third pull-up network 129, and a fourth pull-up network 131, respectively, and four groups of pull-down networks, numbered as a first pull-down network 126, a second pull-down network 128, a third pull-down network 130, and a fourth pull-down network 132, respectively. Depending on the input control signals, different pull-up and pull-down networks may be gated to implement different logic functions.
When the logic values of the control signals C0-C3 are 1, 0, and 1, respectively, the first P-type control transistor 103, the second N-type control transistor 110, the third N-type control transistor 116, and the fourth P-type control transistor 121 are turned off, and the first N-type control transistor 104, the second P-type control transistor 109, the third P-type control transistor 115, and the fourth N-type control transistor 122 are turned on, the second pull-up network 127 and the third pull-up network 129, and the first pull-down network 126 and the fourth pull-down network 132 of the pull-up network are gated, and the equivalent circuit is configured as exclusive-or (XOR), and the logic value of the output terminal Q is the result of the exclusive-or logic operation of the input data a and B.
When the logic values of the control signals C0-C3 are 0, 1, and 0, respectively, the first N-type control transistor 104, the second P-type control transistor 109, the third P-type control transistor 115, and the fourth N-type control transistor 122 are turned off, and the first P-type control transistor 103, the second N-type control transistor 110, the third N-type control transistor 116, and the fourth P-type control transistor 121 are turned on, the first pull-up network 125 and the fourth pull-up network 131, and the second pull-down network 128 and the third pull-down network 130 are gated, and the equivalent circuit is configured as an exclusive nor (XNOR), and the logic value of the output Q is the exclusive nor result of the input data a and B.
When the logic values of the control signals C0-C3 are 0, and 1, respectively, the first N-type control transistor 104, the second N-type control transistor 110, the third N-type control transistor 116, and the fourth P-type control transistor 121 are turned off, and the first P-type control transistor 103, the second P-type control transistor 109, the third P-type control transistor 115, and the fourth N-type control transistor 122 are turned on, the first pull-up network 125, the second pull-up network 127, the third pull-up network 129, and the fourth pull-down network 132 of the pull-down network are turned on, and the equivalent circuit is configured as NAND (NAND), and the logic value of the output terminal Q is the result of the NAND logic operation of the input data a and B.
When the logic values of the control signals C0-C3 are 0, 1, and 1, respectively, the first N-type control transistor 104, the second P-type control transistor 109, the third P-type control transistor 115, and the fourth P-type control transistor (121) are turned off, and the first P-type control transistor 103, the second N-type control transistor 110, the third N-type control transistor 116, and the fourth N-type control transistor 122 are turned on, the first pull-up network 125, the second pull-down network 128, the third pull-down network 130, and the fourth pull-down network 132 are gated, and the equivalent circuit is shown in fig. 5, the logic function of the logic unit is configured as NOR (NOR), and the logic value of the output terminal Q is the NOR result of the input data a and B.
When the logic values of the control signals C0-C3 are 1, AND 0, respectively, the first P-type control transistor 103, the second P-type control transistor 109, the third P-type control transistor 115, AND the fourth N-type control transistor 122 are turned off, AND the first N-type control transistor 104, the second N-type control transistor 110, the third N-type control transistor 116, AND the fourth P-type control transistor 121 are turned on, the fourth pull-up network 131 AND the first pull-down network 126 of the pull-down network, the second pull-down network 128, AND the third pull-down network 130 of the pull-up network are gated, AND the logic function of the logic unit is configured as AND (AND), AND the logic value of the output Q will be the result of the AND logic operation of the input data a AND B, as shown in fig. 6.
When the logic values of the control signals C0-C3 are 1, 0 and 0, respectively, the first P-type control transistor 103, the second N-type control transistor 110, the third N-type control transistor 116 and the fourth N-type control transistor 122 are turned off, and the first N-type control transistor 104, the second P-type control transistor 109, the third P-type control transistor 115 and the fourth P-type control transistor 121 are turned on, the second pull-up network 127, the third pull-up network 129, the fourth pull-up network 131 and the first pull-down network 126 of the pull-down network are turned on, and the equivalent circuit is shown in fig. 7, the logic function of the logic unit is configured as OR (OR), and the logic value of the output terminal Q is the result of the OR logic operation of the input data a and B.
In the metal layer of the layout of the static circuit-based reconfigurable logic cell shown in fig. 8, it is difficult to analyze the circuit function from the layout level due to the symmetry of the layout and the reconfigurable characteristics of the logic function thereof.
Finally, it should be noted that: although the present invention is disclosed above, the present invention is not limited thereto, and those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the embodiments of the invention, and the scope of the invention is defined by the appended claims.
Claims (1)
1. A reconfigurable logic unit based on a static circuit is characterized by comprising a control transistor and a logic transistor;
the logic transistor includes: a first P-type logic transistor (101), a second P-type logic transistor (102), a third P-type logic transistor (107), a fourth P-type logic transistor (108), a fifth P-type logic transistor (113), a sixth P-type logic transistor (114), a seventh P-type logic transistor (119), an eighth P-type logic transistor (120), a first N-type logic transistor (105), a second N-type logic transistor (106), a third N-type logic transistor (111), a fourth N-type logic transistor (112), a fifth N-type logic transistor (117), a sixth N-type logic transistor (118), a seventh N-type logic transistor (123), an eighth N-type logic transistor (124);
the drain electrode of the first P-type logic transistor (101) is connected with the source electrode of the second P-type logic transistor (102) in series to form a first pull-up network (125), and the source electrode of the first P-type logic transistor (101) is connected with a power supply; the drain electrode of the third P-type logic transistor (107) is connected with the source electrode of the fourth P-type logic transistor (108) in series to form a second pull-up network (127), and the source electrode of the third P-type logic transistor (107) is connected with the power supply; the drain electrode of the fifth P-type logic transistor (113) is connected with the source electrode of the sixth P-type logic transistor (114) in series to form a third pull-up network (129), and the source electrode of the fifth P-type logic transistor (113) is connected with the power supply; the drain electrode of the seventh P-type logic transistor (119) is connected with the source electrode of the eighth P-type logic transistor (120) in series to form a fourth pull-up network (131), and the source electrode of the seventh P-type logic transistor (119) is connected with the power supply;
the drain electrode of the second N-type logic transistor (106) is connected with the source electrode of the first N-type logic transistor (105) in series to form a first pull-down network (126), and the source electrode of the second N-type logic transistor (106) is connected with the ground; the drain electrode of the fourth N-type logic transistor (112) is connected with the source electrode of the third N-type logic transistor (111) in series to form a second pull-down network (128), and the source electrode of the fourth N-type logic transistor (112) is connected with the ground; the drain electrode of the sixth N-type logic transistor (118) is connected with the source electrode of the fifth N-type logic transistor (117) in series to form a third pull-down network (130), and the source electrode of the sixth N-type logic transistor (118) is connected with the ground; the drain electrode of the eighth N-type logic transistor (124) is connected with the source electrode of the seventh N-type logic transistor (123), and the drain electrode of the eighth N-type logic transistor (124) is connected with the ground in series to form a fourth pull-down network (132);
the control transistor includes: a first P-type control transistor (103), a second P-type control transistor (109), a third P-type control transistor (115), a fourth P-type control transistor (121), a first N-type control transistor (104), a second N-type control transistor (110), a third N-type control transistor (116), and a fourth N-type control transistor (122);
when the first P-type control transistor (103) is turned on, the output end Q is connected with a power supply through a first pull-up network (125);
when the first N-type control transistor (104) is turned on, the output end Q is connected with the ground through a first pull-down network (126);
when the second P-type control transistor (109) is turned on, the output end Q is connected with a power supply through a second pull-up network (127);
when the second N-type control transistor (110) is turned on, the output end Q is connected with the ground through a second pull-down network (128);
when the third P-type control transistor (115) is turned on, the output end Q is connected with a power supply through a third pull-up network (129);
when the third N-type control transistor (116) is turned on, the output end Q is connected with the ground through a third pull-down network (130);
when the fourth P-type control transistor (121) is turned on, the output end Q is connected with a power supply through a fourth pull-up network (131);
when the fourth N-type control transistor (122) is turned on, the output Q is connected to ground through a fourth pull-down network (132).
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| CN101312342A (en) * | 2007-05-23 | 2008-11-26 | 中芯国际集成电路制造(上海)有限公司 | Level switching circuit |
| CN105610428A (en) * | 2015-12-24 | 2016-05-25 | 中国科学院电子学研究所 | Configurable logic element based on NANDOR structure |
| CN107666313A (en) * | 2017-08-16 | 2018-02-06 | 宁波大学 | A kind of method that specified logic function is realized with cmos circuit |
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| US7397271B2 (en) * | 2005-08-19 | 2008-07-08 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device |
| US8324932B2 (en) * | 2010-11-23 | 2012-12-04 | Oracle International Corporation | High-speed static XOR circuit |
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| CN101312342A (en) * | 2007-05-23 | 2008-11-26 | 中芯国际集成电路制造(上海)有限公司 | Level switching circuit |
| CN105610428A (en) * | 2015-12-24 | 2016-05-25 | 中国科学院电子学研究所 | Configurable logic element based on NANDOR structure |
| CN107666313A (en) * | 2017-08-16 | 2018-02-06 | 宁波大学 | A kind of method that specified logic function is realized with cmos circuit |
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