CN111293178A - Thin film transistor and preparation method thereof - Google Patents
Thin film transistor and preparation method thereof Download PDFInfo
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- CN111293178A CN111293178A CN202010107377.2A CN202010107377A CN111293178A CN 111293178 A CN111293178 A CN 111293178A CN 202010107377 A CN202010107377 A CN 202010107377A CN 111293178 A CN111293178 A CN 111293178A
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- 239000010409 thin film Substances 0.000 title claims abstract description 26
- 238000002360 preparation method Methods 0.000 title abstract description 5
- 229910052751 metal Inorganic materials 0.000 claims abstract description 38
- 239000002184 metal Substances 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000012782 phase change material Substances 0.000 claims abstract description 14
- 239000004020 conductor Substances 0.000 claims abstract description 7
- 239000012212 insulator Substances 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 claims description 128
- 238000000034 method Methods 0.000 claims description 18
- 239000011229 interlayer Substances 0.000 claims description 16
- 239000010408 film Substances 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 12
- 230000008569 process Effects 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 4
- 238000005265 energy consumption Methods 0.000 abstract description 3
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000004134 energy conservation Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- GRUMUEUJTSXQOI-UHFFFAOYSA-N vanadium dioxide Chemical compound O=[V]=O GRUMUEUJTSXQOI-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910021542 Vanadium(IV) oxide Inorganic materials 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 230000005525 hole transport Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- TYHJXGDMRRJCRY-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) tin(4+) Chemical compound [O-2].[Zn+2].[Sn+4].[In+3] TYHJXGDMRRJCRY-UHFFFAOYSA-N 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention relates to the field of liquid crystal display, and discloses a thin film transistor and a preparation method thereof, wherein the thin film transistor comprises: a substrate; the metal shielding layer, the buffer layer, the active layer, the gate insulating layer and the gate electrode layer are sequentially stacked on the substrate; a connector is formed between the metal shielding layer and the gate layer through a thermal phase change material, and the connector can be changed into a conductor from an insulator after absorbing heat; here, by sequentially stacking a metal shielding layer, a buffer layer, an active layer, a gate insulating layer, and a gate electrode layer provided on a substrate; and a connector is formed between the metal shielding layer and the grid layer through a thermal phase-change material, and the thermal phase-change material is converted into a conductor from an insulating state after absorbing heat generated in work, so that the structure of the double-gate thin film transistor is realized, the energy consumption of the thin film transistor in work is reduced, and the energy-saving and emission-reducing effects are achieved by utilizing the heat generated in the work of a product.
Description
Technical Field
The invention relates to the technical field of liquid crystal display, in particular to a thin film transistor and a preparation method thereof.
Background
An OLED (organic light-Emitting Diode), also called an organic electroluminescent Display, an organic light-Emitting semiconductor (OLED). The OLED is a current-type organic light emitting device, and emits light by injection and recombination of carriers, and the intensity of light emission is proportional to the injected current. Under the action of an electric field, holes generated by an anode and electrons generated by a cathode move, are respectively injected into a hole transport layer and an electron transport layer, and migrate to a light emitting layer. When the two meet at the light emitting layer, energy excitons are generated, thereby exciting the light emitting molecules to finally generate visible light.
The existing large-size OLED display device generates more heat in the working process, generally wastes more heat generated in the working process and is not beneficial to use.
Disclosure of Invention
The invention discloses a thin film transistor and a preparation method thereof, which are used for reasonably utilizing heat generated by a large-size OLED display device in working and realizing the effects of energy conservation and emission reduction.
In order to achieve the purpose, the invention provides the following technical scheme:
in a first aspect, the present invention provides a thin film transistor, including: a substrate;
the metal shielding layer, the buffer layer, the active layer, the gate insulating layer and the gate electrode layer are sequentially stacked on the substrate;
and a connector is formed between the metal shielding layer and the gate electrode layer through a thermal phase change material, and the connector can be changed into a conductor from an insulator after absorbing heat.
Because a large-size OLED product can generate a lot of heat in the working process, the thin film transistor prepared by the prior art can not utilize the heat generated in the working process, and a metal shielding layer, a buffer layer, an active layer, a gate insulating layer and a gate electrode layer which are sequentially arranged on a substrate in a stacking mode are adopted; and a connector is formed between the metal shielding layer and the grid layer through a thermal phase-change material, and the thermal phase-change material is converted into a conductor from an insulating state after absorbing heat generated in work, so that the structure of the double-gate thin film transistor is realized, the energy consumption of the thin film transistor in work is reduced, and the energy-saving and emission-reducing effects are achieved by utilizing the heat generated in the work of a product.
Further, the thin film transistor includes: a filling hole for filling the connecting body;
the filling hole penetrates through the gate insulating layer and the buffer layer so that the metal shielding layer is communicated with the gate electrode layer.
Further, an interlayer dielectric sublayer is arranged on one side, away from the substrate, of the gate layer.
Further, a source drain electrode is formed on the interlayer dielectric sublayer.
In a second aspect, the present invention provides a method for manufacturing a thin film transistor, including:
depositing a metal film pattern on the substrate to form a metal shielding layer;
depositing a buffer layer on the metal shielding layer;
depositing an active layer on the buffer layer;
depositing a gate insulating layer on the active layer;
forming a filling hole in the buffer layer and the gate insulating layer, and filling a thermal phase change material in the filling hole to form a connector;
and forming a gate layer on the gate insulating layer, and forming a gate layer pattern through a patterning process, wherein the gate layer is connected with the metal shielding layer through the connecting body.
Further, a partial region of the gate insulating layer is patterned.
Further, a partial region of the active layer is made conductive.
Further, an insulating film is deposited on the gate layer as an interlayer dielectric sublayer.
Further, the interlayer dielectric sub-layer is patterned, and a metal film is deposited on the patterned interlayer dielectric sub-layer and is patterned to serve as a source drain electrode.
Drawings
Fig. 1-8 are schematic diagrams illustrating a process for manufacturing a thin film transistor according to an embodiment of the present invention;
fig. 9 is a cross-sectional view of fig. 8 provided in accordance with an embodiment of the present invention.
Icon: 100-a substrate; 200-a metal shielding layer; 300-a buffer layer; 400-an active layer; 500-a gate insulating layer; 600-gate layer; 700-a linker; 800-filling the hole; 900-an interlayer dielectric sublayer; 1000-source drain electrode.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1 to 9, an embodiment of the present invention provides a thin film transistor, including: a substrate 100;
a metal shielding layer 200, a buffer layer 300, an active layer 400, a gate insulating layer 500, and a gate electrode layer 600 sequentially stacked on the substrate 100;
the connector 700 is formed between the metal shielding layer 200 and the gate layer 600 through a thermal phase change material, and the connector 700 can be changed from an insulator to a conductor after absorbing heat.
It should be noted that, because a large-sized OLED product generates much heat during operation, the thin film transistor manufactured by the prior art cannot utilize the heat generated during operation, and here, the metal shielding layer 200, the buffer layer 300, the active layer 400, the gate insulating layer 500 and the gate electrode layer 600 are sequentially stacked on the substrate 100; and the connecting body 700 is formed between the metal shielding layer 200 and the gate layer 600 through a thermal phase-change material, and the thermal phase-change material is converted into a conductor from an insulating state after absorbing heat generated in work, so that the structure of the double-gate thin film transistor is realized, the energy consumption of the thin film transistor in work is reduced at the moment, and the effects of energy conservation and emission reduction are achieved by using the heat generated in the work of a product.
Also, the thin film transistor includes: a filling hole 800 for filling the connection body 700;
the filling hole 800 penetrates the gate insulating layer 500 and the buffer layer 300 to communicate the metal blocking layer 200 and the gate layer 600.
The gate insulating layer 500 and the buffer layer 300 are communicated through the filling hole 800, thereby achieving communication between the metal blocking layer 200 and the gate electrode layer 600.
And an interlayer dielectric sublayer 900 is provided on the gate layer 600 on the side facing away from the substrate 100, and then the source and drain electrodes 1000 are formed on the interlayer dielectric sublayer 900.
In a second aspect, a method for manufacturing a thin film transistor provided in an embodiment of the present invention includes:
s100: depositing a metal film on the substrate 100 to form a metal shielding layer 200 in a patterned manner; with particular reference to fig. 1, a coating apparatus is used to deposit a metal film on a substrate 100, for example: molybdenum Mo, aluminum Al, and the like; and the deposited metal film is patterned to form the metal shielding layer 200 by using a half-tone process.
S200: depositing a buffer layer 300 on the metal blocking layer 200; with particular reference to fig. 2, a plasma enhanced chemical vapor deposition of an insulating film, such as: silicon oxide, silicon nitride, or the like, as the buffer layer 300.
S300: depositing an active layer 400 on the buffer layer 300; referring specifically to fig. 3, an oxide semiconductor thin film, such as Indium Gallium Zinc Oxide (IGZO), Indium Tin Zinc Oxide (ITZO), or the like, is deposited on the buffer layer 300 as an active layer 400, and the active layer 400 is patterned.
S400: depositing a gate insulating layer 500 on the active layer 400; referring specifically to fig. 4, an insulating film is vapor-deposited on the active layer 400 using plasma enhanced chemistry, such as: silicon oxide, silicon nitride, or the like, as the gate insulating layer 500.
S500: forming a filling hole 800 in the openings of the buffer layer 300 and the gate insulating layer 500, and filling a thermal phase change material in the filling hole 800 to form a connector 700; referring to fig. 5 and 6 in particular, the buffer layer 300 and the gate insulating layer 500 are opened by using a halftone dry etching technique, and the filling hole 800 is filled with a thermal phase change material, for example: vanadium dioxide VO2。
S600: a gate layer 600 is formed on the gate insulating layer 500, and the gate layer 600 is patterned through a patterning process, wherein the gate layer 600 is connected to the metal shielding layer 200 through the connector body 700. Referring specifically to fig. 7, a metal film is deposited on the gate insulating layer 500 using a coating apparatus, for example: copper Cu, aluminum Al, etc., and patterned as the gate layer 600.
S700: a partial region of the gate insulating layer 500 is patterned using a dry etching process, and then a partial region of the active layer 400 is conducted.
S800: referring to fig. 8, an insulating film is deposited as an interlayer dielectric sublayer 900 on a gate layer 600 using a vapor phase of plasma enhanced chemistry. The deposited insulating film may be: for example: silicon oxide, silicon nitride, and the like.
S900: referring to fig. 9, the interlayer dielectric layer 900 is patterned, and then a metal thin film is deposited on the patterned interlayer dielectric sublayer 900 by a magnetron sputtering apparatus, and patterned as a source-drain electrode 1000.
It will be apparent to those skilled in the art that various changes and modifications may be made in the embodiments of the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (9)
1. A thin film transistor, comprising: a substrate;
the metal shielding layer, the buffer layer, the active layer, the gate insulating layer and the gate electrode layer are sequentially stacked on the substrate;
and a connector is formed between the metal shielding layer and the gate electrode layer through a thermal phase change material, and the connector can be changed into a conductor from an insulator after absorbing heat.
2. The thin film transistor according to claim 1, wherein the thin film transistor comprises: a filling hole for filling the connecting body;
the filling hole penetrates through the gate insulating layer and the buffer layer so that the metal shielding layer is communicated with the gate electrode layer.
3. A thin film transistor according to claim 1, characterized in that the side of the gate layer facing away from the substrate is provided with an interlayer dielectric sublayer.
4. The thin film transistor according to claim 3, wherein a source drain electrode is formed on the interlayer dielectric sublayer.
5. A method for manufacturing a thin film transistor includes:
depositing a metal film pattern on the substrate to form a metal shielding layer;
depositing a buffer layer on the metal shielding layer;
depositing an active layer on the buffer layer;
depositing a gate insulating layer on the active layer;
forming a filling hole in the buffer layer and the gate insulating layer, and filling a thermal phase change material in the filling hole to form a connector;
and forming a gate layer on the gate insulating layer, and forming a gate layer pattern through a patterning process, wherein the gate layer is connected with the metal shielding layer through the connecting body.
6. The method of claim 5, wherein a partial region of the gate insulating layer is patterned.
7. The method of claim 6, wherein a portion of the active layer is conductively formed.
8. The method of claim 7, wherein an insulating film is deposited on the gate layer as an interlayer dielectric sublayer.
9. The method of claim 8, wherein the interlayer dielectric sublayer is patterned, a metal film is deposited on the patterned interlayer dielectric sublayer and patterned as a source and drain electrode.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010107377.2A CN111293178A (en) | 2020-02-21 | 2020-02-21 | Thin film transistor and preparation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010107377.2A CN111293178A (en) | 2020-02-21 | 2020-02-21 | Thin film transistor and preparation method thereof |
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| CN111293178A true CN111293178A (en) | 2020-06-16 |
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| CN202010107377.2A Pending CN111293178A (en) | 2020-02-21 | 2020-02-21 | Thin film transistor and preparation method thereof |
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090057766A1 (en) * | 2007-08-31 | 2009-03-05 | Donghui Lu | Integration of silicon boron nitride in high voltage and small pitch semiconductors |
| CN102054773A (en) * | 2009-10-29 | 2011-05-11 | 华映视讯（吴江）有限公司 | Transflective thin film transistor panel and manufacturing method thereof |
| US20160155859A1 (en) * | 2009-09-04 | 2016-06-02 | Semiconductor Energy Laboratory Co., Ltd. | Display device and electronic device |
| CN107706154A (en) * | 2017-09-28 | 2018-02-16 | 京东方科技集团股份有限公司 | A kind of memory element, storage device, preparation method and driving method |
| WO2018211351A1 (en) * | 2017-05-19 | 2018-11-22 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, display device, and method for manufacturing semiconductor device |
| CN109560141A (en) * | 2018-12-13 | 2019-04-02 | 合肥鑫晟光电科技有限公司 | Thin film transistor (TFT), light emitting device and its manufacturing method |
| CN110518072A (en) * | 2019-08-29 | 2019-11-29 | 合肥鑫晟光电科技有限公司 | Thin film transistor (TFT) and preparation method thereof and display device |
| CN110660846A (en) * | 2019-09-30 | 2020-01-07 | 合肥鑫晟光电科技有限公司 | Thin film transistor, manufacturing method and light-emitting device |
-
2020
- 2020-02-21 CN CN202010107377.2A patent/CN111293178A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090057766A1 (en) * | 2007-08-31 | 2009-03-05 | Donghui Lu | Integration of silicon boron nitride in high voltage and small pitch semiconductors |
| US20160155859A1 (en) * | 2009-09-04 | 2016-06-02 | Semiconductor Energy Laboratory Co., Ltd. | Display device and electronic device |
| CN102054773A (en) * | 2009-10-29 | 2011-05-11 | 华映视讯（吴江）有限公司 | Transflective thin film transistor panel and manufacturing method thereof |
| WO2018211351A1 (en) * | 2017-05-19 | 2018-11-22 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, display device, and method for manufacturing semiconductor device |
| CN107706154A (en) * | 2017-09-28 | 2018-02-16 | 京东方科技集团股份有限公司 | A kind of memory element, storage device, preparation method and driving method |
| CN109560141A (en) * | 2018-12-13 | 2019-04-02 | 合肥鑫晟光电科技有限公司 | Thin film transistor (TFT), light emitting device and its manufacturing method |
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