CN111274186B

CN111274186B - Singlechip for improving execution efficiency of central processing unit

Info

Publication number: CN111274186B
Application number: CN202010059657.0A
Authority: CN
Inventors: 李振华
Original assignee: Beijing Zhongweicheng Microelectronics Technology Co ltd
Current assignee: Beijing Zhongweicheng Microelectronics Technology Co ltd
Priority date: 2020-01-19
Filing date: 2020-01-19
Publication date: 2022-06-24
Anticipated expiration: 2040-01-19
Also published as: CN111274186A

Abstract

The invention provides a single chip microcomputer for improving the execution efficiency of a central processing unit, which comprises an on-chip module and an off-chip module; the on-chip module at least comprises a communication interface, a central processing unit and a static random access memory; the on-chip module does not include a non-volatile memory; the off-chip module at least comprises a communication interface and a first nonvolatile memory; when the system starts to work, firstly, the codes of the first nonvolatile memory are transmitted to the static random access memory through the communication interfaces of the on-chip module and the off-chip module, and are executed by the central processing unit. The access speed of the on-chip SRAM is higher, so that the execution efficiency of the CPU is improved. Meanwhile, the nonvolatile memory is removed, the wafer cost is reduced during sealing, the single chip microcomputer is divided into an on-chip module and an off-chip module, the content of the on-chip module is relatively fixed, the off-chip module can be freely selected and matched, and the overall manufacturing cost of the single chip microcomputer is further reduced.

Description

Singlechip for improving execution efficiency of central processing unit

Technical Field

The invention relates to the technical field of single-chip microcomputers, in particular to a single-chip microcomputer for improving the execution efficiency of a central processing unit.

Background

Program codes in the existing single chip microcomputer product are usually stored in a non-volatile memory in a chip, but the access speed of the non-volatile memory is limited, so that the speed of reading instructions from the non-volatile memory by a central processing unit is restricted, and the execution efficiency of the central processing unit is influenced. To improve this efficiency, it is common practice to read the program code of the non-volatile memory into an on-chip sram, and then read and execute the instructions from the sram by the cpu. The capacity of the static random access memory in the existing single chip microcomputer product is usually smaller than that of the nonvolatile memory, and the program codes in the nonvolatile memory can only be partially transmitted to the static random access memory step by step, so the size of the on-chip static random access memory becomes a bottleneck for improving the execution efficiency of the central processing unit. In addition, the existing single chip microcomputer product is high in cost and easy to waste because the capacity of the in-chip nonvolatile memory cannot be changed, and the single chip microcomputer product is usually manufactured in a high-capacity direction.

Disclosure of Invention

The invention aims to provide a method for improving the execution efficiency of a central processing unit and a single chip microcomputer.

In order to achieve the purpose, the invention adopts the technical scheme that: a single chip for improving the execution efficiency of a Central Processing Unit (CPU) comprises an on-chip module, an off-chip module and a control system, wherein the on-chip module comprises the CPU, a Static Random Access Memory (SRAM) and a serial interface; the capacity of the on-chip static random access memory is larger than or equal to the capacity of the off-chip nonvolatile memory. When the system starts to work, all codes of the off-chip nonvolatile memory are integrally transmitted to the on-chip static random access memory through the serial interface, and then the central processing unit executes the program codes from the on-chip static random access memory. The access speed of the on-chip static random access memory is higher, so that the execution efficiency of the program code is greatly improved.

The single chip microcomputer is packaged by adopting a sealing technology, so that the using amount of wafers is reduced, the cost of the wafers is reduced, the interfaces of the nonvolatile memory and the bus are reduced, the cost of the interfaces is reduced, and the production process is simplified.

The beneficial technical effects of the invention are as follows: in the technical scheme of the invention, because the sum of the capacities of the on-chip static random access memories is greater than or equal to the capacity of the off-chip nonvolatile memory, all program codes in the off-chip nonvolatile memory can be directly transmitted to the on-chip static random access memory during working, and the central processing unit can directly access the program codes from the on-chip static random access memory. Meanwhile, the single chip microcomputer is split into the chip internal module and the chip external module, the content of the chip internal module is relatively fixed, the chip external module can be freely selected and matched, and the manufacturing cost of the whole single chip microcomputer is reduced.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.

FIG. 1 is a prior art single chip architecture;

FIG. 2 is a single chip microcomputer configuration of the present invention;

FIG. 3 case of physical isolation;

FIG. 4 a logically isolated case;

fig. 5 shows a wafer seal monolithic computer in the prior art.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.

Referring to fig. 1, a conventional single chip microcomputer architecture in the art is shown, and an internal memory is divided into a data memory and a program memory. Taking the commercially available AT89C51 as an example, there are 128 bytes of random access memory, also called data storage, and 4 kbytes of read only memory, also called program memory. 4K bytes of program memory or read-only memory, the program is compiled into machine code by a compiler and all exists in the area, so the area is called as the program memory; however, when the single chip microcomputer is powered on and executed, data in the area can only be read but cannot be written. The 128-byte random access memory or data memory is called random access memory or data memory, and some intermediate variables are stored in the place during the program operation process, and values needing to be operated can be obtained from the place.

It can be seen from the above prior art that the capacity of the sram in the existing single chip microcomputer product is smaller than that of the non-volatile memory, and the program code in the non-volatile memory can only be partially transmitted to the sram step by step, and at the same time, the execution efficiency of the CPU is not high because the read/write speed of the non-volatile memory is much slower than that of the sram.

As shown in fig. 2, in order to solve the above technical problem, the single chip microcomputer is composed of an on-chip module and an off-chip module. The on-chip module at least comprises a central processing unit, a static random access memory and a communication interface. The off-chip module at least comprises a nonvolatile memory, a control system thereof and a communication interface. The capacity of the on-chip static random access memory is larger than or equal to the capacity of the off-chip nonvolatile memory.

When the system starts to work, all codes of the off-chip nonvolatile memory are integrally transmitted to the on-chip static random access memory through the communication interface, and then the central processing unit executes the program codes from the on-chip static random access memory. The access speed of the on-chip static random access memory is higher, so that the execution efficiency of the program code is greatly improved.

In one embodiment, the communication interface is a serial interface.

Fig. 3 shows another embodiment of the present invention. The static random access memory in the on-chip module is composed of a first sub-block and a second sub-block, and the first sub-block and the second sub-block are isolated in a physical mode, namely the first sub-block and the second sub-block are physically composed of two static random access memories. The function of the first sub-block is similar to that of a static random access memory of a traditional single chip microcomputer, and in the program running process, some intermediate variables are stored in the place and values needing to be calculated can be obtained from the place. When the system starts to work, all codes of the off-chip nonvolatile memory are integrally transmitted to the second sub-block in the chip through the serial interface, and then the central processing unit executes the program codes from the first sub-block.

In one embodiment, the size of the second sub-block is not smaller than the capacity of the off-chip non-volatile memory.

Fig. 4 shows another embodiment of the present invention. The static random access memory in the on-chip module consists of a third sub-block and a fourth sub-block, and the third sub-block and the fourth sub-block are isolated in a logic mode, namely the two sub-blocks are physically integrated and are divided into the third sub-block and the fourth sub-block in a logic mode. The function of the third sub-block is similar to that of a static random access memory of a traditional single chip microcomputer, and in the program running process, some intermediate variables are stored in the place and values needing to be calculated can be obtained from the place.

When the system starts to work, all codes of the off-chip nonvolatile memory are integrally transmitted to a fourth sub-block on the chip through the serial interface, and then the central processing unit executes the program codes from the third sub-block.

In one embodiment, the size of the fourth sub-block is not smaller than the capacity of the off-chip non-volatile memory.

In one embodiment, the above-mentioned isolation is performed by using an addressing space, for example, a size of 128 bytes is divided into the addressing space as a third sub-block, and a size of 4 kbytes is divided into the addressing space as the third sub-block. The sub-block sizes are examples, and do not represent that the sub-blocks can be divided according to the sizes, and the sizes can be selected according to actual needs when the invention is implemented.

In one embodiment, the single chip microcomputer is sealed by using a sealing technology. As shown in fig. 5, a wafer-sealed single chip in the prior art is disclosed, wherein 13 layers of wafers are required for the eFlash module, i.e. the nonvolatile memory portion, and the current wafers are mainly charged by the number of layers, so that a large part of the cost is occupied by the 13 layers of wafers during production.

In the invention, the nonvolatile memory is eliminated, and the influence of the increase of the capacity of the random access memory on the number of wafer layers is not great, so the cost of the wafer layers of the nonvolatile memory can be saved.

On the other hand, because the nonvolatile memory is not used, the interfaces of a part of nonvolatile memory and the bus can be reduced, the interface cost is reduced, and meanwhile, because the number of the interfaces is reduced during the laminated production, the production process is simpler, the yield is improved, and the production cost is further reduced.

In summary, although increasing the capacity of the ram brings about a certain cost increase, the total cost of the single chip microcomputer is not significantly increased due to the reduction of the wafer cost, the interface cost and the production cost brought by the removal of the volatile memory.

In one embodiment, the on-chip module and the off-chip module are combined into one chip and packaged together, that is, after leaving the factory, the chip is always operated as one chip, and a user cannot detach the chip by himself or herself. That is, the matching of the inner part and the outer part of the chip is fixed and matched when leaving the factory and can not be changed.

In one embodiment, the on-chip module and the off-chip module are separately packaged during production, and after receiving a user order, the on-chip module and the off-chip module are combined according to the requirement of the user order and packaged. Since the chip is packaged separately, the order can be implemented to adjust the size of the chip memory and the chip memory, which is helpful to further reduce the production cost.

In one embodiment, the on-chip module and the off-chip module are separately packaged during production and delivered separately, and at the same time, an on-chip and off-chip communication interface is reserved and is selected by a user for packaging.

The present invention has been described in detail with reference to the specific embodiments and examples, but these are not intended to limit the present invention. Numerous variations and modifications and combinations will occur to those skilled in the art without departing from the principles of the invention and these are to be considered within the scope of the invention.

Claims

1. The utility model provides an improve singlechip of central processing unit execution efficiency which characterized in that:

the single chip microcomputer comprises an inner module and an outer module;

the on-chip module at least comprises a communication interface, a central processing unit and a static random access memory;

the on-chip module does not include a non-volatile memory;

the off-chip module at least comprises a communication interface and a first nonvolatile memory;

when the system starts to work, all codes of the first nonvolatile memory are integrally transmitted to the static random access memory through the communication interfaces of the on-chip module and the off-chip module and are executed by the central processing unit;

the single chip microcomputer is packaged by using a sealing technology;

the static random access memory in the on-chip module consists of a first sub-block and a second sub-block, wherein the first sub-block and the second sub-block are isolated in a physical mode or in a logical mode;

the code is transmitted to the second sub-block, the size of the second sub-block being no less than the size of the first non-volatile memory.

2. The single chip microcomputer for improving the execution efficiency of the central processing unit according to claim 1, wherein: the communication interface is a serial interface.

3. The single-chip microcomputer for improving the execution efficiency of a central processing unit according to claim 1, wherein the isolation by means of logic is isolation by using an addressing space.

4. The single chip microcomputer for improving the execution efficiency of a central processing unit according to any one of claims 1 to 2, wherein the on-chip module and the off-chip module are combined into one chip and packaged together, and always operate as one chip.

5. The single chip microcomputer for improving the execution efficiency of a central processing unit according to any one of claims 1 to 2, wherein the on-chip module and the off-chip module are respectively and independently packaged.