CN111274099A - Indicator lamp control method, system, equipment and medium of switch system - Google Patents
Indicator lamp control method, system, equipment and medium of switch system Download PDFInfo
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Abstract
The invention discloses an indicator light control method of a switch system, which comprises the following steps based on a CPLD/FPGA: obtaining an effective control signal sent by the BMC and the CPU; responding to that effective control signals sent by the BMC and the CPU are low-level signals, and acquiring in-place state information of a plurality of pieces of hardware; respectively sending corresponding control signals to indicator lamps corresponding to the hardware according to the in-place state information of the hardware; continuously acquiring effective control signals sent by the BMC and the CPU; reading information of a first register controlled by the BMC in response to the fact that an effective control signal sent by the BMC is a high-level signal; and sending corresponding control signals to indicator lamps corresponding to a plurality of pieces of hardware in the plurality of pieces of hardware according to the information of the first register. The invention also discloses a system, a computer device and a readable storage medium. The scheme provided by the invention can realize the control of the indicator light at different stages of the system.
Description
Technical Field
The invention relates to the field of switches, in particular to an indicator light control method, an indicator light control system, indicator light control equipment and a storage medium of a switch system.
Background
In the switch system, the CPLD/FPGA chip can be used for controlling the power-on and power-off sequence control, the communication control, the key detection, the fan rotating speed control, the SFP lighting control and serial port switching, the double BIOS switching, the I2C multi-master and multi-slave communication and the like of the whole switch, the CPLD/FPGA is a semi-customized special integrated circuit, has the series advantages of flexible programming, quick response, high integration level and the like, and is more and more widely applied in the field of development, verification and control application in the prior period.
The lamp panel design is the important content of switch system design, can the visual display current switch main part state and whole switch state. In the existing product, a BMC (baseboard management controller) is not added in a switch system, only the control of an indicator light is realized based on a CPU (central processing unit), and if the system is abnormal or crashed, the light cannot be indicated, namely, a client cannot be prompted; in addition, if the BMC control is added, the BMC and the CPU are controlled simultaneously, and the priority problem needs to be processed; finally, the BMC indicator light is not usually added to the indicator panel, which does not obtain the BMC operation status.
Disclosure of Invention
In view of the above, in order to overcome at least one aspect of the above problems, an embodiment of the present invention provides an indicator light control method for an exchange system, including performing the following steps based on a CPLD/FPGA:
obtaining an effective control signal sent by the BMC and the CPU;
responding to that the effective control signals sent by the BMC and the CPU are low-level signals, and acquiring in-place state information of a plurality of pieces of hardware;
respectively sending corresponding control signals to indicator lights corresponding to the plurality of hardware according to the in-place state information of the plurality of hardware;
continuously acquiring effective control signals sent by the BMC and the CPU;
reading information of a first register controlled by the BMC in response to an effective control signal sent by the BMC being a high level signal;
and sending corresponding control signals to indicator lamps corresponding to a plurality of pieces of hardware in the plurality of pieces of hardware according to the information of the first register.
In some embodiments, further comprising:
continuously acquiring effective control signals sent by the BMC and the CPU;
reading information of a second register controlled by the CPU in response to the fact that an effective control signal sent by the CPU is a high-level signal;
and sending corresponding control signals to indicator lamps corresponding to a plurality of pieces of hardware in the plurality of pieces of hardware according to the information of the second register.
In some embodiments, further comprising:
and responding to the fact that indicator lights corresponding to a plurality of pieces of hardware in the plurality of pieces of hardware are controlled by the BMC and the CPU at the same time, and sending corresponding control signals according to information with high priority in the information of the first register and the information of the second register.
In some embodiments, further comprising:
acquiring a watchdog signal sent by the BMC;
judging the working state of the BMC according to the watchdog signal;
and responding to the BMC exception, and sending a corresponding control signal according to the in-place state information of the hardware or the information of the second register.
In some embodiments, further comprising:
acquiring a watchdog signal sent by a CPU;
judging the working state of the CPU according to the watchdog signal;
responding to the CPU abnormity, and sending a corresponding control signal according to the in-place state information of the hardware or the information of the first register.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a system for controlling an indicator light of a switch system, comprising:
the working state detection function module is configured to acquire an effective control signal sent by the BMC and the CPU;
the indicator light function module is configured to respond to that the effective control signals sent by the BMC and the CPU are low-level signals, and acquire on-site state information of a plurality of pieces of hardware; respectively sending corresponding control signals to indicator lights corresponding to the plurality of hardware according to the in-place state information of the plurality of hardware;
the working state detection function module is further configured to continuously acquire an effective control signal sent by the BMC and the CPU;
the indicator light functional module is also configured to read information of a first register controlled by the BMC in response to an active control signal sent by the BMC being a high level signal; and sending corresponding control signals to indicator lights corresponding to a plurality of pieces of hardware in the plurality of pieces of hardware according to the information of the first register.
In some embodiments, the operating state detection function module is further configured to continue to acquire valid control signals sent by the BMC and the CPU;
the indicator light functional module is also configured to respond to the fact that an effective control signal sent by the CPU is a high-level signal, and read information of a second register controlled by the CPU; and sending corresponding control signals to indicator lights corresponding to a plurality of pieces of hardware in the plurality of pieces of hardware according to the information of the second register.
In some embodiments, the indicator light function module is further configured to send a corresponding control signal according to information with a higher priority in the information of the first register and the information of the second register in response to the indicator lights corresponding to several pieces of the plurality of pieces of hardware being simultaneously controlled by the BMC and the CPU.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a computer apparatus, including:
at least one processor; and
a memory storing a computer program operable on the processor, wherein the processor executes the program to perform the steps of any of the indicator light control methods of the switch system as described above.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a computer-readable storage medium storing a computer program which, when executed by a processor, performs the steps of the indicator light control method of any one of the switch systems as described above.
The invention has one of the following beneficial technical effects: according to the scheme provided by the invention, the corresponding control signal is sent according to the acquired in-place state of the hardware in the system power-on stage, and the corresponding control signal is sent according to the acquired information of the register controlled by the BMC after the BMC is started, so that the control of the indicator lamp can be realized in different stages of the system.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
Fig. 1 is a schematic flow chart of an indicator light control method of an exchange system according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a system for controlling indicator lights of a switch system according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a computer device provided in an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a computer-readable storage medium according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
According to an aspect of the present invention, an embodiment of the present invention provides an indicator light control method of an exchange system, as shown in fig. 1, including performing the following steps based on a CPLD/FPGA: s1, acquiring effective control signals sent by the BMC and the CPU; s2, responding to that the effective control signals sent by the BMC and the CPU are low level signals, and acquiring in-place state information of a plurality of hardware; s3, respectively sending corresponding control signals to the indicator lights corresponding to the plurality of hardware according to the in-place state information of the plurality of hardware; s4, continuously acquiring effective control signals sent by the BMC and the CPU; s5, reading the information of the first register controlled by the BMC in response to the fact that the effective control signal sent by the BMC is a high-level signal; and S6, sending corresponding control signals to indicator lights corresponding to a plurality of pieces of hardware in the plurality of pieces of hardware according to the information of the first register.
According to the scheme provided by the invention, the corresponding control signal is sent according to the acquired in-place state of the hardware in the system power-on stage, and the corresponding control signal is sent according to the acquired information of the register controlled by the BMC after the BMC is started, so that the control of the indicator lamp can be realized in different stages of the system.
In some embodiments, the method further comprises:
continuously acquiring effective control signals sent by the BMC and the CPU;
reading information of a second register controlled by the CPU in response to the fact that an effective control signal sent by the CPU is a high-level signal;
and sending corresponding control signals to indicator lamps corresponding to a plurality of pieces of hardware in the plurality of pieces of hardware according to the information of the second register.
Specifically, the working state of the switch may include a power-on start stage, a BMC valid stage and a CPU valid stage, where the BMC valid stage is earlier than the CPU valid stage, and thus, in the initial power-on start stage, that is, when both valid control signals sent by the BMC and the CPU are low-level signals, a corresponding control signal is sent according to an in-place state of the obtained multiple pieces of hardware, when it is detected that the valid control signal sent by the BMC is a high-level signal, information of a first register controlled by the BMC is obtained, and a corresponding control signal is sent to an indicator lamp corresponding to a plurality of pieces of hardware in the multiple pieces of hardware according to the information of the first register; and when detecting that the effective control signal sent by the CPU is a high-level signal, acquiring information of a second register controlled by the CPU, and sending corresponding control signals to indicator lamps corresponding to a plurality of pieces of hardware in the plurality of pieces of hardware according to the information of the second register.
For example, a particular switch indicator light may include a SYS light, indicating overall switch system status; the LOC lamp can be turned on or off through remote control by a user so as to indicate the position of the machine; a PSU lamp indicating a power state of the switch system; a FAN light to indicate a FAN status of the switch system; and the BMC lamp indicates the working state of the BMC of the switch system. The specific switch operating state includes: a power-on starting stage, wherein the SYS lamp and the BMC lamp are in a green flashing stage, and the PSU lamp and the FAN lamp reflect the actual state of the power supply or the FAN in place at the moment; a BMC valid stage, wherein the BMC is valid earlier than the CPU in a normal starting stage, when the BMC is valid, a BMC _ Control (high-level valid Control signal) signal is sent out, at the moment, the BMC controls an FAN lamp register according to the obtained information, the CPLD/FPGA also switches the FAN lamp lighting information source to the register, meanwhile, the BMC lamp is green and normally on, the SYS lamp is still in a green flashing stage, and the PSU lamp is still lighted according to the actual on-site state condition; when the CPU is effective, the CPU sends an OS _ Control (high-level effective Control signal) signal, at the moment, the CPLD/FPGA realizes the PSU lamp by acquiring a PSU register controlled by the CPU, the BMC lamp is also switched to the Control state of the register, and the SYS lamp can display the state of the whole switch, including the SYS lamp register, the FAN lamp state, the PSU lamp state and the BMC lamp state, and the priority states are a red lamp, a yellow lamp and a green lamp; under normal conditions, both the BMC and the CPU are in an effective state, so that the register information of the BMC lamp and the register information of the SYS lamp are respectively from the BMC and the CPU, and the registers controlled by the BMC and the SYS are respectively located at different positions of the same register or two different registers.
Therefore, whether the BMC or the CPU can control the indicator light of the hardware or not can be determined according to the altitude of the effective control signal. That is, all the indicator lights can be controlled by the BMC or the CPU, or can be controlled by the BMC and the CPU together. When the BMC and the CPU control the indicator lamps together, the indicator lamps controlled by the BMC and the CPU can be the same or different, namely the indicator lamps of a plurality of pieces of hardware can be controlled only by the BMC, the indicator lamps of a plurality of pieces of hardware can be controlled only by the CPU, and the indicator lamps of a plurality of pieces of hardware can be controlled by the BMC and the CPU simultaneously.
In some embodiments, the method further comprises:
and responding to the fact that indicator lights corresponding to a plurality of pieces of hardware in the plurality of pieces of hardware are controlled by the BMC and the CPU at the same time, and sending corresponding control signals according to information with high priority in the information of the first register and the information of the second register.
Specifically, when the indicator lights of a plurality of pieces of hardware are controlled by the BMC and the CPU at the same time, the CPLD/FPGA may compare the register information of the BMC and the CPU and transmit a control signal according to information with high priority, for example, the more serious the state of the hardware corresponding to the register information is, the higher the priority is, and when the register information of the BMC and the CPU is the same, the information of the register controlled by the CPU may be selected to transmit the control signal.
For example, in the switch starting stage, the CPLD/FPGA sends a control signal to each indicator lamp according to the in-place state of a plurality of hardware, specifically, a PSU (power supply) lights up according to the actual number of PSUs in place, and since a general switch system may include two PSUs, a normally green state where both PSUs are in place and a red state where only one PSU is in place may be considered, and a corresponding control signal is sent; the control principle of the FAN (FAN) indicator light is the same, and three severity levels of green, yellow and red are displayed according to the in-place state of the FAN; the BMC and the CPU are still in a starting stage, so that the BMC and the SYS indicator light are in a green flashing state at the moment. When the BMC sends the BMC _ Control, the BMC indicates that the BMC has Control capability at the moment, the signal source of the FAN lamp at the CPLD/FPGA point is switched to a register for reading Control of the BMC, the BMC comprises information such as on-position, rotating speed and power supply state about the signal source of the FAN lamp, wherein the register of the FAN lamp comprises two bits, one bit indicates a green state, the other indicates a red state, and the two bits indicate a yellow state; when the CPU sends an OS _ Control (high-level effective Control signal), the CPU is indicated to have Control capability at the moment, the signal source of the PSU lamp at the CPLD/FPGA point is switched to a register for reading the Control of the CPU, the signal source of the PSU lamp by the CPU comprises information such as on-position, overvoltage, overcurrent, undervoltage, PSU working state, PSU fan and the like, wherein the PSU lamp register comprises two bits, one bit indicates a green state, the other indicates a red state, and the two bits indicate a yellow state; when BMC sends BMC _ Control and CPU sends OS _ Control, BMC and CPU have Control capability, BMC and CPU can Control register of SYS lamp and BMC lamp respectively, CPLD/FPGA lights up according to BMC and CPU register value, SYS lamp has highest authority, BMC, PSU and FAN indicator lamp have yellow lamp or red lamp, system lamp can display yellow lamp or red lamp; when the BMC fails, the BMC displays red, and the FAN lamp displays according to actual conditions; when the SYS fails, the SYS lamp can display red, and the PSU lamp can display according to actual conditions.
In some embodiments, the method further comprises:
acquiring a watchdog signal sent by the BMC;
judging the working state of the BMC according to the watchdog signal;
and responding to the BMC exception, and sending a corresponding control signal according to the in-place state information of the hardware or the information of the second register.
In some embodiments, the method further comprises:
acquiring a watchdog signal sent by a CPU;
judging the working state of the CPU according to the watchdog signal;
responding to the CPU abnormity, and sending a corresponding control signal according to the in-place state information of the hardware or the information of the first register.
Specifically, when the BMC fails, selecting information of a second register controlled by the CPU for control or lighting on in-place state information of hardware; when the CPU fails, selecting a register controlled by the BMC and lighting the lamp under the actual condition; when the BMC and the CPU simultaneously have faults, lighting is selected according to actual conditions. The BMC and the CPU working state are realized by detecting square waves respectively.
For example, when the BMC is abnormal, the BMC lamp may be controlled by the CPU and may light red; when the CPU is abnormal, the SYS lamp can be controlled by the BMC and then can light red; when the BMC and the CPU are abnormal simultaneously, the BMC lamp can be lightened to be red, the SYS lamp can be lightened to be red, the PSU lamp and the FAN lamp are lightened according to actual conditions, wherein whether the BMC works normally is achieved by monitoring square waves sent by the BMC, and whether the SYS works normally is achieved by monitoring the square waves sent by the CPU.
Therefore, the judgment of the BMC and the CPU working state and the conversion of the lighting control right are realized based on the CPLD/FPGA, so that the accurate control and real-time indication of the lamp panel state indicator lamp are realized, and a reminding effect is provided for customers.
The following describes in detail the method for controlling the indicator lights of the switch system according to the present invention with reference to the schematic structural diagram of the system shown in fig. 2.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a CPLD/FPGA for controlling an indicator light of a switch system, including:
the working state detection function module is configured to acquire an effective control signal sent by the BMC and the CPU;
the indicator light function module is configured to respond to that the effective control signals sent by the BMC and the CPU are low-level signals, and acquire on-site state information of a plurality of pieces of hardware; respectively sending corresponding control signals to indicator lights corresponding to the plurality of hardware according to the in-place state information of the plurality of hardware;
the working state detection function module is further configured to continuously acquire an effective control signal sent by the BMC and the CPU;
the indicator light functional module is also configured to read information of a first register controlled by the BMC in response to an active control signal sent by the BMC being a high level signal; and sending corresponding control signals to indicator lights corresponding to a plurality of pieces of hardware in the plurality of pieces of hardware according to the information of the first register.
In some embodiments, the operating state detection function module is further configured to continue to acquire valid control signals sent by the BMC and the CPU;
the indicator light functional module is also configured to respond to the fact that an effective control signal sent by the CPU is a high-level signal, and read information of a second register controlled by the CPU; and sending corresponding control signals to indicator lights corresponding to a plurality of pieces of hardware in the plurality of pieces of hardware according to the information of the second register.
In some embodiments, the indicator light function module is further configured to send a corresponding control signal according to information with a higher priority in the information of the first register and the information of the second register in response to the indicator lights corresponding to several pieces of the plurality of pieces of hardware being simultaneously controlled by the BMC and the CPU.
As shown in fig. 2, the indicator function module may include a BMC lamp function module, a PSU lamp function module, a FAN lamp function module, a LOC lamp function module, and a SYS lamp function module
The design of the lamp panel interface of the switchboard system considers clocks (SYS _ CLK, FourHZ _ CLK) and a reset signal (Res _ n), typical input signals also respectively indicate BMC _ Control of BMC valid state and OS _ Control of CPU valid state, default is low level, valid is high level, namely when high level is output, the BMC or the CPU is ready to Control the state of an indicator light; the BMC _ Watchdog and the CPU _ Watchdog always output square wave signals when the BMC or the CPU works normally; the BMC _ BMC _ LED _ Reg and the CPU _ BMC _ LED _ Reg are registers which are output by the BMC and the CPU and related to the BMC lamp, respectively comprise two bits, the BMC _ LED _ Blue and the BMC _ LED _ Reg which correspond to the two bits are control signals of a BMC Blue lamp and a BMC Red lamp which are output by the CPLD/FPGA, and when the two lamps are simultaneously lightened, a yellow lamp is displayed; PSU _ STATUS is the actual PSU state, PSU _ LED _ Reg is a register related to the PSU lamp, comprises two bits and is only controlled by a CPU, PSU _ LED _ Blue and PSU _ LED _ Reg are control signals of a PSU Blue lamp and a PSU Red lamp output by a CPLD/FPGA, and when the two lamps are simultaneously lightened, a yellow lamp is displayed; FAN _ STATUS is the actual PSU state, FAN _ LED _ Reg is a register related to the PSU lamp, comprises two bits and can be controlled only by BMC, FAN _ LED _ Blue and FAN _ LED _ Reg are control signals of FAN Blue lamp and Red lamp output by CPLD/FPGA, and when the two lamps are simultaneously lighted, a yellow lamp is displayed; LOC _ LED _ Reg is a register of the LOC lamp, comprises one bit, BMC and CPU can control, LOC _ LED is the LOC lamp state output by CPLD/FPGA, and comprises green on and off states; the BMC _ SYS _ LED _ Reg and the CPU _ SYS _ LED _ Reg are registers which are output by the BMC and the CPU and are related to SYS lamps, the registers respectively comprise two bits, the SYS _ LED _ Blue and the SYS _ LED _ Red which correspond to the registers are control signals of a BMC Blue lamp and a Red lamp which are output by the CPLD/FPGA, when the two lamps are simultaneously lightened, a yellow lamp is displayed, particularly, the actual display state of the SYS lamp is related to the display states of the BMC, the PSU and the FAN besides the registers, and the display priority is Red, yellow and green.
The BMC and CPU working state detection function module can detect Control signals (BMC _ Control and OS _ Control) output by the BMC and the CPU to determine whether the BMC and the CPU have Control capability, and if the BMC and the CPU have the Control capability, the CPLD/FPGA can be switched to read a corresponding register; the BMC and CPU working state detection function module can also detect BMC _ Watchdog and CPU _ Watchdog used for indicating the working states of the BMC and the CPU, when the BMC or the CPU works normally, the BMC _ Watchdog and the CPU _ Watchdog are square wave signals, when the BMC or the CPU breaks down, the BMC _ Watchdog and the CPU _ Watchdog are constant levels, if the BMC _ Watchdog does not break down within a period of time, the BMC breaks down, if the CPU _ Watchdog does not break down within a period of time, the CPU breaks down, and the specific time length is related to specific project requirements.
In some embodiments, the BMC is added to the switch system, so that a dual-master design can be realized, and management is more convenient. As shown in fig. 2, in the system according to the embodiment of the present invention, a BMC lamp function module is added, a management control function is added to a BMC management interface, and a BMC indicator is added to a lamp panel indication system. The BMC lamp indicates the BMC running state. In the BMC starting stage, the BMC lamp is in a green flashing state; when the BMC is effective, the BMC lamp is in a green normally-on state; when the CPU is effective, the BMC and the CPU control the state of the BMC lamp through the state of the control register; when the BMC fails, the BMC lamp indicates a corresponding failure state.
In some embodiments, the PSU lamp function module can be used to control the PSU indicator lamp, and in the starting stage, the PSU lamp is lit by the CPLD/FPGA according to the actual situation; when the CPU is started, the CPLD/FPGA controls the register to light up according to the CPU; when the CPU has a fault, the PSU lamp is lighted up by the CPLD/FPGA according to the actual situation.
In some embodiments, the FAN lamp function module can be used for controlling a FAN indicator lamp, and in a starting stage, the FAN lamp is lighted by the CPLD/FPGA according to the actual in-place and power state conditions of the FAN module; when the BMC is started, the CPLD/FPGA controls the register to light up according to the BMC; when the BMC has a fault, the FAN lamp is turned on by the CPLD/FPGA according to the actual in-place and power state conditions of the FAN module.
In some embodiments, the LOC lamp function module may be used to control a LOC indicator lamp, the LOC lamp may be used to indicate location information, and the BMC or CPU may control the status of the lamp after it is active.
In some embodiments, the SYS lamp function may be configured to control a SYS indicator lamp, where the SYS lamp is configured to indicate the system status of the switch, and the SYS lamp is in a green flashing state during a system startup phase, i.e., before the CPU is inactive.
The invention provides a method for realizing double main control and display of a lamp panel indication of a switch system, which comprises a display method of an SYS lamp, a BMC lamp, a PSU lamp, an FAN lamp and an LOC lamp in different stages and different states, wherein a BMC lamp indication is added in an indicator lamp system, a BMC control is added in a register control, and SYS lamp reference information comprises the operation stage and the operation state of the switch system, register information and the display states of the BMC lamp, the PSU lamp and a FAN lamp. The lamp panel indicating system implementation method provided and implemented by the invention provides a new and complete lamp panel indicating system implementation method, which is convenient for users to accurately position fault information and know the running state of the whole switchboard system.
Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 3, an embodiment of the present invention further provides a computer apparatus 501, comprising:
at least one processor 520; and
Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 4, an embodiment of the present invention further provides a computer-readable storage medium 601, where the computer-readable storage medium 601 stores computer program instructions 610, and the computer program instructions 610, when executed by a processor, perform the steps of the indicator light control method of any switch system as above.
Finally, it should be noted that, as will be understood by those skilled in the art, all or part of the processes of the methods of the above embodiments may be implemented by a computer program to instruct related hardware to implement the methods. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.
In addition, the apparatuses, devices, and the like disclosed in the embodiments of the present invention may be various electronic terminal devices, such as a mobile phone, a Personal Digital Assistant (PDA), a tablet computer (PAD), a smart television, and the like, or may be a large terminal device, such as a server, and the like, and therefore the scope of protection disclosed in the embodiments of the present invention should not be limited to a specific type of apparatus, device. The client disclosed by the embodiment of the invention can be applied to any one of the electronic terminal devices in the form of electronic hardware, computer software or a combination of the electronic hardware and the computer software.
Furthermore, the method disclosed according to an embodiment of the present invention may also be implemented as a computer program executed by a CPU, and the computer program may be stored in a computer-readable storage medium. The computer program, when executed by the CPU, performs the above-described functions defined in the method disclosed in the embodiments of the present invention.
Further, the above method steps and system elements may also be implemented using a controller and a computer readable storage medium for storing a computer program for causing the controller to implement the functions of the above steps or elements.
Further, it should be appreciated that the computer-readable storage media (e.g., memory) herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of example, and not limitation, nonvolatile memory can include Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which can act as external cache memory. By way of example and not limitation, RAM is available in a variety of forms such as synchronous RAM (DRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to comprise, without being limited to, these and other suitable types of memory.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.
The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with the following components designed to perform the functions herein: a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and/or any other such configuration.
The steps of a method or algorithm described in connection with the disclosure herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.
In one or more exemplary designs, the functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk, blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps of implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. An indicator light control method of an exchanger system is characterized by comprising the following steps of executing based on a CPLD/FPGA:
obtaining an effective control signal sent by the BMC and the CPU;
responding to that the effective control signals sent by the BMC and the CPU are low-level signals, and acquiring in-place state information of a plurality of pieces of hardware;
respectively sending corresponding control signals to indicator lights corresponding to the plurality of hardware according to the in-place state information of the plurality of hardware;
continuously acquiring effective control signals sent by the BMC and the CPU;
reading information of a first register controlled by the BMC in response to an effective control signal sent by the BMC being a high level signal;
and sending corresponding control signals to indicator lamps corresponding to a plurality of pieces of hardware in the plurality of pieces of hardware according to the information of the first register.
2. The method of claim 1, further comprising:
continuously acquiring effective control signals sent by the BMC and the CPU;
reading information of a second register controlled by the CPU in response to the fact that an effective control signal sent by the CPU is a high-level signal;
and sending corresponding control signals to indicator lamps corresponding to a plurality of pieces of hardware in the plurality of pieces of hardware according to the information of the second register.
3. The method of claim 2, further comprising:
and responding to the fact that indicator lights corresponding to a plurality of pieces of hardware in the plurality of pieces of hardware are controlled by the BMC and the CPU at the same time, and sending corresponding control signals according to information with high priority in the information of the first register and the information of the second register.
4. The method of claim 2, further comprising:
acquiring a watchdog signal sent by the BMC;
judging the working state of the BMC according to the watchdog signal;
and responding to the BMC exception, and sending a corresponding control signal according to the in-place state information of the hardware or the information of the second register.
5. The method of claim 2, further comprising:
acquiring a watchdog signal sent by a CPU;
judging the working state of the CPU according to the watchdog signal;
responding to the CPU abnormity, and sending a corresponding control signal according to the in-place state information of the hardware or the information of the first register.
6. A system for controlling indicator lights of a switch system, comprising:
the working state detection function module is configured to acquire an effective control signal sent by the BMC and the CPU;
the indicator light function module is configured to respond to that the effective control signals sent by the BMC and the CPU are low-level signals, and acquire on-site state information of a plurality of pieces of hardware; respectively sending corresponding control signals to indicator lights corresponding to the plurality of hardware according to the in-place state information of the plurality of hardware;
the working state detection function module is further configured to continuously acquire an effective control signal sent by the BMC and the CPU;
the indicator light functional module is also configured to read information of a first register controlled by the BMC in response to an active control signal sent by the BMC being a high level signal; and sending corresponding control signals to indicator lights corresponding to a plurality of pieces of hardware in the plurality of pieces of hardware according to the information of the first register.
7. The system of claim 6,
the working state detection function module is also configured to continuously acquire effective control signals sent by the BMC and the CPU;
the indicator light functional module is also configured to respond to the fact that an effective control signal sent by the CPU is a high-level signal, and read information of a second register controlled by the CPU; and sending corresponding control signals to indicator lights corresponding to a plurality of pieces of hardware in the plurality of pieces of hardware according to the information of the second register.
8. The system of claim 6, wherein the indicator light function module is further configured to send a corresponding control signal according to a higher priority of the information of the first register and the information of the second register in response to the indicator lights corresponding to several of the plurality of hardware being simultaneously controlled by the BMC and the CPU.
9. A computer device, comprising:
at least one processor; and
memory storing a computer program operable on the processor, characterized in that the processor executes the program to perform the steps of the method according to any of claims 1-5.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, is adapted to carry out the steps of the method according to any one of claims 1-5.
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| CN202010029298.4A CN111274099A (en) | 2020-01-12 | 2020-01-12 | Indicator lamp control method, system, equipment and medium of switch system |
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| CN202010029298.4A CN111274099A (en) | 2020-01-12 | 2020-01-12 | Indicator lamp control method, system, equipment and medium of switch system |
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| CN111274099A true CN111274099A (en) | 2020-06-12 |
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| CN202010029298.4A Withdrawn CN111274099A (en) | 2020-01-12 | 2020-01-12 | Indicator lamp control method, system, equipment and medium of switch system |
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