CN111246211B - Encoding method, decoding method, device, equipment and storage medium - Google Patents
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- H04N19/176—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
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Abstract
The application provides an encoding method, a decoding method, a device, equipment and a storage medium. The encoding method comprises the following steps: acquiring an image to be processed; encoding the image into an image code stream, wherein the image code stream comprises a plurality of macro blocks arranged in the forward direction; all the macroblocks are formed into a plurality of chips, wherein the data length of each chip is the same, each chip comprises at least one macroblock, and the residual data blocks of the truncated macroblock in the previous chip are added to the tail position in the next chip after being reversely arranged; and sending the plurality of chips to a decoding device so that the decoding device decodes each chip through forward decoding and reverse decoding to obtain the image. According to the method and the device, the correctness of data transmission can be ensured without adding the resynchronization signals in the chips, so that redundancy caused by adding the resynchronization signals is avoided, and the utilization rate of transmission bandwidth is improved.
Description
Technical Field
The present application relates to the field of computer technologies, and in particular, to an encoding method, a decoding method, an apparatus, a device, and a storage medium.
Background
During image transmission, images need to be coded, so that the image transmission rate is improved, and the error rate during image transmission is reduced.
Generally, encoding an image mainly includes a variable-length encoding packetization scheme and a fixed-length packetization scheme. In both the packing mode of variable length coding and the packing mode of fixed length, a resynchronization signal is added to each packed chip, so that a decoding device can decode according to the resynchronization signal, the robustness of image code stream transmission is enhanced, and transmission errors are prevented.
However, since a re-synchronization signal needs to be added to each chip, a large amount of data redundancy is added to transmit each image, which results in a waste of transmission bandwidth.
Disclosure of Invention
The embodiment of the application provides an encoding method, a decoding method, a device, equipment and a storage medium, which aim to solve the problem that a large amount of data redundancy is generated in an image encoding mode to cause transmission bandwidth waste.
In a first aspect, an embodiment of the present application provides an encoding method, including:
acquiring an image to be processed;
encoding the image into an image code stream, wherein the image code stream comprises a plurality of macro blocks arranged in the forward direction;
all the macroblocks are formed into a plurality of chips, wherein the data length of each chip is the same, each chip comprises at least one macroblock, and the residual data blocks of the truncated macroblock in the previous chip are added to the tail position in the next chip after being reversely arranged;
and sending the plurality of chips to a decoding device so that the decoding device decodes each chip through forward decoding and reverse decoding to obtain the image.
In one possible implementation, grouping all macroblocks into a plurality of chips includes:
acquiring residual data blocks of a truncated macro block in a previous chip;
reversely arranging the residual data blocks, and adding the reversely arranged residual data blocks to the tail position of the chip to be processed;
sequentially adding each macro block which does not form the code slice from the initial position in the code slice to be processed until the data length of the code slice to be processed reaches a preset length, or all macro blocks do not have the macro blocks which do not form the code slice;
when all the macroblocks exist macroblocks which do not form the chips, acquiring the residual data blocks of the truncated macroblocks in the chip to be processed, taking the next chip as the code block to be processed, and skipping to the following steps: and reversely arranging the residual data blocks, and adding the reversely arranged residual data blocks to the tail position in the chip to be processed.
In one possible embodiment, acquiring an image to be processed includes:
and acquiring an image acquired by the image sensor.
In a second aspect, an embodiment of the present application provides a decoding method, including:
receiving a plurality of chips of an image transmitted by an encoding device, wherein the data length of each chip is the same, each chip comprises at least one macro block, and the residual data blocks of the macro block which is cut off in the previous chip are added to the tail position in the next chip after being arranged in a reverse direction;
and decoding each chip through forward decoding and backward decoding to obtain the image.
In one possible implementation, decoding each slice by forward decoding and reverse decoding to obtain the image includes:
for each chip, obtaining a first decoding result of the chip through forward decoding, obtaining a second decoding result of the chip through backward decoding, and calculating the first decoding result and the second decoding result according to a preset operation mode to obtain a residual data block of a macro block contained in the chip and/or a truncated macro block in the previous chip; when the chip comprises the residual data block of the macroblock which is cut off in the previous chip, combining the residual data block with the data block of the macroblock which is cut off in the previous chip to generate the macroblock which is cut off in the previous chip;
combining all macroblocks to generate the image.
In one possible embodiment, combining all macroblocks to generate the image comprises:
and performing Inverse Discrete Cosine Transform (IDCT) on all the macro blocks to obtain the image.
In a third aspect, an embodiment of the present application provides an encoding apparatus, including:
the acquisition module is used for acquiring an image to be processed;
the processing module is used for encoding the image into an image code stream, wherein the image code stream comprises a plurality of macro blocks which are arranged in the forward direction;
the processing module is further configured to group all the macroblocks into a plurality of chips, where each chip has the same data length, each chip includes at least one macroblock, and the remaining data blocks of the macroblock that was truncated in the previous chip are added to the end position in the next chip after being arranged in the reverse direction;
and the sending module is used for sending the plurality of code slices to decoding equipment so that the decoding equipment decodes each code slice through forward decoding and reverse decoding to obtain the image.
In a possible implementation manner, the processing module is specifically configured to:
acquiring residual data blocks of a truncated macro block in a previous chip;
reversely arranging the residual data blocks, and adding the reversely arranged residual data blocks to the tail position of the chip to be processed;
sequentially adding each macro block which does not form the code slice from the initial position in the code slice to be processed until the data length of the code slice to be processed reaches a preset length, or all macro blocks do not have the macro blocks which do not form the code slice;
when all the macroblocks exist macroblocks which do not form the chips, acquiring the residual data blocks of the truncated macroblocks in the chip to be processed, taking the next chip as the code block to be processed, and skipping to the following steps: and reversely arranging the residual data blocks, and adding the reversely arranged residual data blocks to the tail position in the chip to be processed.
In a possible implementation manner, the obtaining module is specifically configured to:
and acquiring an image acquired by the image sensor.
In a fourth aspect, an embodiment of the present application provides a decoding apparatus, including:
a receiving module, configured to receive multiple chips of an image sent by an encoding device, where the data length of each chip is the same, each chip includes at least one macroblock, and a remaining data block of a macroblock truncated in a previous chip is added to an end position in a next chip after being arranged in a reverse direction;
and the processing module is used for decoding each code slice through forward decoding and reverse decoding to obtain the image.
In a possible implementation manner, the processing module is specifically configured to:
for each chip, obtaining a first decoding result of the chip through forward decoding, obtaining a second decoding result of the chip through backward decoding, and calculating the first decoding result and the second decoding result according to a preset operation mode to obtain a residual data block of a macro block contained in the chip and/or a truncated macro block in the previous chip; when the chip comprises the residual data block of the macroblock which is cut off in the previous chip, combining the residual data block with the data block of the macroblock which is cut off in the previous chip to generate the macroblock which is cut off in the previous chip;
combining all macroblocks to generate the image.
In a possible implementation manner, the processing module is specifically configured to:
and performing Inverse Discrete Cosine Transform (IDCT) on all the macro blocks to obtain the image.
In a fifth aspect, an embodiment of the present application provides an encoding apparatus, including: at least one processor and memory;
the memory stores computer-executable instructions;
the at least one processor executes the computer-executable instructions stored by the memory, causing the at least one processor to perform the encoding method as described above in the first aspect and various possible implementations of the first aspect.
In a sixth aspect, an embodiment of the present application provides a decoding apparatus, including: at least one processor and memory;
the memory stores computer-executable instructions;
the at least one processor executes computer-executable instructions stored by the memory, causing the at least one processor to perform the decoding method as described above in the first aspect and various possible implementations of the first aspect.
In a seventh aspect, an embodiment of the present application provides a computer-readable storage medium, where a computer executing instruction is stored in the computer-readable storage medium, and when a processor executes the computer executing instruction, the encoding method according to the first aspect and various possible implementation manners of the first aspect is implemented.
In an eighth aspect, an embodiment of the present application provides a computer-readable storage medium, where a computer executing instruction is stored in the computer-readable storage medium, and when a processor executes the computer executing instruction, the decoding method according to the first aspect and various possible implementation manners of the first aspect is implemented.
The encoding method, the decoding method, the device, the equipment and the storage medium provided by the embodiment of the application acquire the image to be processed; encoding an image into an image code stream, wherein the image code stream comprises a plurality of macro blocks which are arranged in the forward direction; all the macroblocks are formed into a plurality of chips, wherein the data length of each chip is the same, each chip comprises at least one macroblock, and the residual data blocks of the truncated macroblock in the previous chip are added to the tail position in the next chip after being reversely arranged; the method comprises the steps of sending a plurality of code slices to a decoding device, enabling the decoding device to decode each code slice through forward decoding and reverse decoding to obtain an image, and enabling the code mode that residual data blocks of a truncated macro block in a previous code slice are added to the tail position of the next code slice after being arranged in a reverse direction and the decoding mode of the forward decoding and the reverse decoding to ensure that data transmission correctness can be guaranteed without adding a resynchronization signal in the code slice, so that redundancy caused by the addition of the resynchronization signal is avoided, and the utilization rate of transmission bandwidth is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.
Fig. 1 is a schematic diagram of an architecture of an image transmission system according to an embodiment of the present application;
fig. 2 is a schematic flowchart of an encoding method according to an embodiment of the present application;
fig. 3 is a schematic flowchart of an encoding method according to another embodiment of the present application;
fig. 4 is a schematic diagram of each chip obtained by image encoding according to an embodiment of the present application;
FIG. 5 is a flowchart illustrating a decoding method according to another embodiment of the present application
Fig. 6 is an interactive signaling diagram of an image transmission method according to still another embodiment of the present application;
fig. 7 is a schematic structural diagram of an encoding apparatus according to an embodiment of the present application;
fig. 8 is a schematic structural diagram of a decoding apparatus according to another embodiment of the present application;
fig. 9 is a schematic hardware structure diagram of an encoding apparatus according to an embodiment of the present application;
fig. 10 is a schematic hardware structure diagram of a decoding device according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Fig. 1 is a schematic diagram of an architecture of an image transmission system according to an embodiment of the present application. As shown in fig. 1, the present embodiment provides an encoding system including an encoding device 11 and a decoding device 12. The encoding device 11 may be a camera, a mobile phone, a vehicle-mounted terminal, a monitoring device, and the like, which is not limited herein. The decoding device 12 may be a mobile phone, a desktop computer, a notebook computer, a vehicle-mounted terminal, a server, etc., and is not limited herein. The encoding device 11 and the decoding device 12 may perform data transmission by a wired communication manner or a wireless communication manner. The encoding device 11 may encode an image to be transmitted to obtain a plurality of chips corresponding to the image, and then transmit the plurality of chips to the decoding device 12, and the decoding device 12 obtains the image by decoding the plurality of chips. The image may be a photo or a video image, which is not limited herein.
In one possible application scenario, the encoding device is a camera deployed in a desert, a tropical rainforest and other areas where people are difficult to reach, and used for acquiring images of landforms, environments and the like. The camera comprises an image sensor, the image sensor is used for collecting images, then the images are coded to obtain code slices corresponding to the images, and the code slices corresponding to the images are sent to the decoding equipment through a wireless network. The decoding device is a user terminal of a worker and is used for decoding to obtain an image and displaying the image to the worker for viewing. Because the coding equipment is deployed in an area with fewer personnel, the power supply is difficult to replace, and the coding equipment generally adopts a processor with low processing capacity and low power consumption to reduce energy consumption and prevent the situation that the power supply is exhausted and cannot be supplemented in time. By adopting the existing coding mode, a resynchronization signal is added to each chip, which causes a great deal of redundancy in image transmission, wastes bandwidth and causes excessive energy consumption of coding equipment due to transmission of excessive redundant data. By adopting the encoding mode provided by the embodiment, the residual data blocks of the truncated macro block in the previous chip can be added to the tail position in the next chip after being arranged in the reverse direction, and the decoding modes of forward decoding and reverse decoding are adopted, so that the correctness of data transmission can be ensured without adding heavy synchronization signals in the chip, the redundancy caused by adding the heavy synchronization signals is avoided, the utilization rate of transmission bandwidth is improved, the low-energy-consumption operation of encoding equipment is further ensured, and the problem of frequent power supply replacement is avoided.
Fig. 2 is a flowchart illustrating an encoding method according to an embodiment of the present application. The execution subject of the method is the encoding device.
As shown in fig. 2, the method includes:
s201, acquiring an image to be processed.
In this embodiment, the image to be processed is an image that the encoding device needs to perform encoding transmission, and the image may be a picture or a video image, which is not limited herein. The encoding device can comprise an image sensor, and an image acquired by the image sensor can be used as an image to be processed; the encoding device may also obtain an image sent by another device or stored in a database as an image to be processed, which is not limited herein.
S202, encoding the image into an image code stream, wherein the image code stream comprises a plurality of macro blocks which are arranged in the forward direction.
In this embodiment, the encoding device may encode the Image to obtain an Image code stream, for example, the Image code stream may be in a JPEG (Joint Photographic Expert Group) Format, a PNG (Portable Network Graphics), an EXIF (EXchangeable Image file Format) Format, and the like, which is not limited herein. A picture may be decomposed into macroblocks, and the data in each macroblock is arranged in the forward direction, i.e. the data in the macroblocks are arranged in sequence from the start position to the end position.
And S203, all the macroblocks are formed into a plurality of chips, wherein the data length of each chip is the same, each chip comprises at least one macroblock, and the residual data blocks of the truncated macroblock in the previous chip are added to the tail position in the next chip after being reversely arranged.
In this embodiment, the encoding apparatus may group all macroblocks of the image into a plurality of slices. This embodiment is a fixed-length packetization, and therefore, the data length of each chip is the same. For example, the image has 29 macroblocks, and the 29 macroblocks may be transmitted in 6 chips, each chip including one or more macroblocks. Due to the fixed-length packing manner, for a certain chip, the last macroblock packed in the chip may be a truncated macroblock, only a part of the truncated macroblock is packed in the chip, and another part of the truncated macroblock needs to be packed in the next chip. The remaining data blocks of the truncated macroblock in the slice are arranged in reverse direction in this embodiment and then added to the end position of the next slice, so that the decoding apparatus can obtain the remaining data blocks of the truncated macroblock by reverse encoding when decoding.
S204, sending the plurality of code slices to decoding equipment so that the decoding equipment decodes each code slice through forward decoding and reverse decoding to obtain the image.
In this embodiment, the encoding apparatus may transmit a plurality of code slices generated from the image to the decoding apparatus. The decoding device decodes each chip by combining forward decoding and backward decoding to obtain the image. Since the chips in this embodiment do not correspond to the resynchronization signal, if the macroblocks in all chips are arranged in the forward direction, if a certain macroblock in a chip has a data transmission error, all macroblocks after the macroblock in the chip cannot be decoded because the start position cannot be determined, thereby causing data loss of multiple macroblocks. In the embodiment, the residual data blocks of the truncated macroblock in the previous chip are arranged in the reverse direction and then added to the tail position of the next chip, and a mode of combining forward decoding and backward decoding is adopted during decoding, if a certain macroblock in a chip has data transmission errors, the macroblock before the macroblock can be obtained through forward decoding, the starting positions of all macroblocks after the macroblock can be obtained through backward decoding, then all macroblocks after the macroblock can be obtained through decoding, other macroblocks except the macroblock can be correctly decoded when the certain macroblock has transmission errors, and the robustness of code stream transmission can be ensured under the condition of no resynchronization signals.
The method comprises the steps of obtaining an image to be processed; encoding an image into an image code stream, wherein the image code stream comprises a plurality of macro blocks which are arranged in the forward direction; all the macroblocks are formed into a plurality of chips, wherein the data length of each chip is the same, each chip comprises at least one macroblock, and the residual data blocks of the truncated macroblock in the previous chip are added to the tail position in the next chip after being reversely arranged; the method comprises the steps of sending a plurality of code slices to a decoding device, enabling the decoding device to decode each code slice through forward decoding and reverse decoding to obtain an image, and enabling the code mode that residual data blocks of a truncated macro block in a previous code slice are added to the tail position of the next code slice after being arranged in a reverse direction and the decoding mode of the forward decoding and the reverse decoding to ensure that data transmission correctness can be guaranteed without adding a resynchronization signal in the code slice, so that redundancy caused by the addition of the resynchronization signal is avoided, and the utilization rate of transmission bandwidth is improved.
Fig. 3 is a flowchart illustrating an encoding method according to another embodiment of the present application. The present embodiment describes a specific implementation process of grouping all macroblocks into a plurality of chips. As shown in fig. 3, S203 may include:
s301, obtaining the residual data block of the truncated macroblock in the previous chip.
S302, the residual data blocks are reversely arranged, and the residual data blocks after reverse arrangement are added to the tail position in the chip to be processed.
And S303, sequentially adding each macro block which does not form the code slice from the initial position in the code slice to be processed until the data length of the code slice to be processed reaches a preset length, or all macro blocks do not have the macro blocks which do not form the code slice.
S304, when all the macro blocks have macro blocks which do not form the code slice, acquiring the residual data block of the intercepted macro block in the code slice to be processed, taking the next code slice as the code block to be processed, and jumping to the following steps: and reversely arranging the residual data blocks, and adding the reversely arranged residual data blocks to the tail position in the chip to be processed.
In this embodiment, the encoding apparatus may sequentially acquire each macroblock of the image, adding each macroblock to the first slice. And stopping when the data length of the first chip reaches a preset length, reversely arranging the residual data blocks of the truncated macro blocks in the first chip, then adding the residual data blocks to the tail position of the second chip, and then sequentially acquiring the rest macro blocks of the image and adding the rest macro blocks to the second chip until the data length of the second chip reaches the preset length. The remaining data blocks of the truncated macroblock in the second chip are arranged in reverse, then added to the end position of the third chip, and the third chip, the fourth chip, etc. are processed in the same way as the second chip is processed as described above until all macroblocks of the picture are added to the chip, and the encoding process is ended.
The following description is given with reference to an embodiment example. Fig. 4 is a schematic diagram of each chip obtained by image encoding according to an embodiment of the present application. Referring to fig. 4, it is assumed that a bitstream of a picture is decomposed into 29 macroblocks, MB1 to MB29, wherein the direction of the arrow indicates the direction of the macroblock data, the direction of the arrow toward the right in this embodiment is a forward direction, and the direction of the arrow toward the left is a reverse direction. MB1 through MB5, and a portion of MB6 are packed into a first slice of fixed length, and the remaining portion of MB6 is first steered (i.e., reversed) and then steered to the end of a second slice. When the second slice is encoded into MB12, the fixed length slice length has been reached, and the remainder of MB12 is then redirected to the end of the third slice. After the fifth slice is performed according to the coding method, the residual code words of the MB27 are reversely put to the end of the MB29, and since the length of the last slice does not exceed the preset limit of the fixed length, the MB29 does not need to be split, and only needs to be coded according to the forward sequence.
Fig. 5 is a flowchart illustrating a decoding method according to another embodiment of the present application. The method is performed by a decoding apparatus. As shown in fig. 5, the method includes:
and S501, receiving a plurality of chips of the image transmitted by the encoding device, wherein the data length of each chip is the same, each chip comprises at least one macro block, and the residual data blocks of the truncated macro blocks in the previous chip are added to the tail position in the next chip after being arranged in a reverse direction.
In this embodiment, the encoding apparatus encodes an image into a plurality of chips and transmits the plurality of chips to the decoding apparatus. A decoding device receives a plurality of chips. The specific implementation manner of the encoding device encoding the image into multiple code slices is similar to the embodiment shown in fig. 2 and fig. 3, and is not described herein again.
S502, decoding each code slice through forward decoding and backward decoding to obtain the image.
In this embodiment, the decoding apparatus obtains an image by performing forward encoding and reverse encoding once for each slice, and then combining the results of the forward encoding and the reverse encoding to obtain macroblocks in the slice. Alternatively, the decoding apparatus may display the image on a screen after decoding the image.
In the embodiment of the application, the decoding device receives a plurality of chips of an image sent by the encoding device, wherein the data length of each chip is the same, each chip comprises at least one macro block, the residual data blocks of the macro block truncated in the previous chip are added to the tail position in the next chip after being arranged in the reverse direction, each chip is decoded through forward decoding and reverse decoding to obtain the image, and the correctness of data transmission can be ensured without adding resynchronization signals in the chips through a coding mode of adding the residual data blocks of the macro block truncated in the previous chip to the tail position in the next chip after being arranged in the reverse direction and a decoding mode of forward decoding and reverse decoding, so that the redundancy caused by adding the resynchronization signals is avoided, and the utilization rate of transmission bandwidth is improved.
Optionally, for each chip, obtaining a first decoding result of the chip by forward decoding, obtaining a second decoding result of the chip by backward decoding, and performing operation on the first decoding result and the second decoding result according to a preset operation manner to obtain a residual data block of a macroblock included in the chip and/or a truncated macroblock in a previous chip; and when the slice comprises the residual data block of the macroblock truncated in the previous slice, combining the residual data block with the data block of the macroblock truncated in the previous slice to generate the macroblock truncated in the previous slice.
The decoding device combines all macroblocks to generate the image. In this embodiment, the decoding apparatus processes each chip in turn. For a chip, the decoding apparatus performs forward decoding from the start position to the end position of the chip in forward order to obtain a first decoding result, and then performs reverse decoding from the end position to the start position of the chip in reverse order, and so on until a second decoding result. And then, operating the first decoding result and the second decoding result according to a preset operation mode to obtain data contained in the chip, wherein the data can comprise the residual data block of the macroblock and/or the truncated macroblock in the previous chip. The predetermined operation manner is not limited herein, and can be set by a person skilled in the art according to actual requirements, for example, the predetermined operation manner includes but is not limited to a combination of at least one or more of and operation, or operation, xor operation, and the like. If the slice contains the remaining data blocks of the macroblock truncated in the previous slice, the decoding apparatus combines the remaining data blocks with the data blocks of the macroblock truncated in the previous slice to generate the macroblock truncated in the previous slice.
Taking the example of fig. 4 as an example, the decoding device decodes the first slice, which may result in a part of data blocks of MB1 to MB5, and MB 6. The decoding device decodes the second slice, which may result in some data blocks of MB7 to MB11, MB12, and remaining data blocks of MB6, and combines the remaining data blocks of MB6 in the second slice with some data blocks of MB6 in the first slice, which may result in MB 6. The rest of the slices are processed in turn in a similar manner until all the slices are processed.
The decoding device may combine all macroblocks to generate an image. Alternatively, all macroblocks are Inverse Discrete Cosine Transformed (IDCT) to obtain an image. Further, other image conversion may be performed, and the present invention is not limited thereto.
In the embodiment, the residual data blocks of the truncated macroblock in the previous chip are arranged in the reverse direction and then added to the tail position of the next chip, and a mode of combining forward decoding and backward decoding is adopted during decoding, if a certain macroblock in a chip has data transmission errors, the macroblock before the macroblock can be obtained through forward decoding, the starting positions of all macroblocks after the macroblock can be obtained through backward decoding, then all macroblocks after the macroblock can be obtained through decoding, other macroblocks except the macroblock can be correctly decoded when the certain macroblock has transmission errors, and the robustness of code stream transmission can be ensured under the condition of no resynchronization signals. Taking the second slice in fig. 4 as an example, assuming that data on a certain data bit in the MB10 is in error, the decoding device may obtain MB7 to MB9 by forward decoding of the second slice, obtain the residual data block of the MB6 and the start positions of the MB11 and the MB12 by reverse decoding of the second slice, and obtain MB11 and MB12 by performing a certain operation on the result of the forward decoding and the result of the reverse decoding, so that the decoding device may still decode the residual data blocks of the MB7 to MB9, MB11, MB12 and MB6 in the second slice when a data error occurs in the MB10, and thus the robustness of the transmitted code stream may be ensured even in the absence of a resynchronization signal.
Fig. 6 is an interaction signaling diagram of an image transmission method according to still another embodiment of the present application. As shown in fig. 6, the method includes:
s601, the encoding device acquires an image to be processed.
S602, the encoding device encodes the image into an image code stream, wherein the image code stream comprises a plurality of macro blocks arranged in the forward direction.
S603, the encoding apparatus groups all the macroblocks into a plurality of chips, wherein each chip has the same data length, each chip includes at least one macroblock, and the remaining data blocks of the macroblock truncated in the previous chip are added to the end position in the next chip after being arranged in reverse.
And S604, the encoding device sends the plurality of chips to the decoding device.
S605, the decoding apparatus receives a plurality of slices of the image transmitted by the encoding apparatus.
And S606, decoding each code slice by the decoding equipment through forward decoding and reverse decoding to obtain the image.
The specific implementation of this embodiment is similar to the embodiment shown in fig. 2 and fig. 5, and is not described herein again.
Fig. 7 is a schematic structural diagram of an encoding apparatus according to an embodiment of the present application. As shown in fig. 7, the encoding device 70 includes: an obtaining module 701, a processing module 702, and a sending module 703.
An obtaining module 701, configured to obtain an image to be processed.
A processing module 702, configured to encode the image into an image code stream, where the image code stream includes a plurality of macro blocks arranged in a forward direction.
The processing module 702 is further configured to group all the macroblocks into a plurality of chips, where each chip has the same data length, each chip includes at least one macroblock, and the remaining data blocks of the macroblock truncated in the previous chip are added to the end position in the next chip after being arranged in the reverse direction.
A sending module 703 is configured to send the multiple code slices to a decoding device, so that the decoding device decodes each code slice through forward decoding and reverse decoding to obtain the image.
Optionally, the processing module 702 is specifically configured to:
acquiring residual data blocks of a truncated macro block in a previous chip;
reversely arranging the residual data blocks, and adding the reversely arranged residual data blocks to the tail position of the chip to be processed;
sequentially adding each macro block which does not form the code slice from the initial position in the code slice to be processed until the data length of the code slice to be processed reaches a preset length, or all macro blocks do not have the macro blocks which do not form the code slice;
when all the macroblocks exist macroblocks which do not form the chips, acquiring the residual data blocks of the truncated macroblocks in the chip to be processed, taking the next chip as the code block to be processed, and skipping to the following steps: and reversely arranging the residual data blocks, and adding the reversely arranged residual data blocks to the tail position in the chip to be processed.
Optionally, the obtaining module 701 is specifically configured to:
and acquiring an image acquired by the image sensor.
The encoding device provided in the embodiment of the present application may be used to implement the above-described encoding method embodiment, and the implementation principle and technical effect are similar, which are not described herein again.
Fig. 8 is a schematic structural diagram of a decoding apparatus according to yet another embodiment of the present application. As shown in fig. 8, the decoding apparatus 80 includes: a receiving module 801 and a processing module 802.
A receiving module 801, configured to receive multiple chips of an image sent by an encoding apparatus, where the data length of each chip is the same, each chip includes at least one macroblock, and a remaining data block of a truncated macroblock in a previous chip is added to an end position in a next chip after being arranged in a reverse direction.
A processing module 802, configured to decode each slice through forward decoding and reverse decoding to obtain the image.
Optionally, the processing module 802 is specifically configured to:
for each chip, obtaining a first decoding result of the chip through forward decoding, obtaining a second decoding result of the chip through backward decoding, and calculating the first decoding result and the second decoding result according to a preset operation mode to obtain a residual data block of a macro block contained in the chip and/or a truncated macro block in the previous chip; when the chip comprises the residual data block of the macroblock which is cut off in the previous chip, combining the residual data block with the data block of the macroblock which is cut off in the previous chip to generate the macroblock which is cut off in the previous chip;
combining all macroblocks to generate the image.
Optionally, the processing module 802 is specifically configured to:
and performing Inverse Discrete Cosine Transform (IDCT) on all the macro blocks to obtain the image.
The decoding apparatus provided in the embodiment of the present application may be configured to execute the foregoing decoding method embodiment, and the implementation principle and the technical effect are similar, which are not described herein again.
Fig. 9 is a schematic hardware structure diagram of an encoding apparatus according to an embodiment of the present application. As shown in fig. 9, the present embodiment provides an encoding apparatus 90 including: at least one processor 901 and memory 902. The encoding device 90 also includes a communication component 903. The processor 901, the memory 902, and the communication section 903 are connected by a bus 904.
In a specific implementation process, the at least one processor 901 executes the computer-executable instructions stored in the memory 902, so that the at least one processor 901 performs the above encoding method.
For a specific implementation process of the processor 901, reference may be made to the above method embodiments, which implement principles and technical effects are similar, and details of this embodiment are not described herein again.
In the embodiment shown in fig. 9, it should be understood that the Processor may be a Central Processing Unit (CPU), other general-purpose processors, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in the incorporated application may be directly implemented by a hardware processor, or may be implemented by a combination of hardware and software modules in the processor.
The memory may comprise high speed RAM memory and may also include non-volatile storage NVM, such as at least one disk memory.
The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, an Extended ISA (EISA) bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, the buses in the figures of the present application are not limited to only one bus or one type of bus.
Fig. 10 is a schematic hardware structure diagram of a decoding device according to an embodiment of the present application. As shown in fig. 10, the decoding apparatus 100 provided in the present embodiment includes: at least one processor 1001 and memory 1002. The decoding apparatus 100 further includes a communication section 1003. The processor 1001, the memory 1002, and the communication unit 1003 are connected by a bus 1004.
In a specific implementation, the at least one processor 1001 executes the computer-executable instructions stored by the memory 1002, so that the at least one processor 1001 executes the decoding method as described above.
For a specific implementation process of the processor 1001, reference may be made to the above method embodiments, which have similar implementation principles and technical effects, and details of this embodiment are not described herein again.
In the embodiment shown in fig. 10, it should be understood that the Processor may be a Central Processing Unit (CPU), other general purpose processors, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in the incorporated application may be directly implemented by a hardware processor, or may be implemented by a combination of hardware and software modules in the processor.
The memory may comprise high speed RAM memory and may also include non-volatile storage NVM, such as at least one disk memory.
The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, an Extended ISA (EISA) bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, the buses in the figures of the present application are not limited to only one bus or one type of bus.
The present application also provides a computer-readable storage medium, in which computer-executable instructions are stored, and when a processor executes the computer-executable instructions, the above encoding method is implemented.
The present application also provides a computer-readable storage medium, in which computer-executable instructions are stored, and when a processor executes the computer-executable instructions, the decoding method as above is implemented.
The readable storage medium may be implemented by any type or combination of volatile or non-volatile memory devices, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disks. Readable storage media can be any available media that can be accessed by a general purpose or special purpose computer.
An exemplary readable storage medium is coupled to the processor such the processor can read information from, and write information to, the readable storage medium. Of course, the readable storage medium may also be an integral part of the processor. The processor and the readable storage medium may reside in an Application Specific Integrated Circuits (ASIC). Of course, the processor and the readable storage medium may also reside as discrete components in the apparatus.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.
Claims (16)
1. A method of encoding, comprising:
acquiring an image to be processed;
encoding the image into an image code stream, wherein the image code stream comprises a plurality of macro blocks arranged in the forward direction;
all the macroblocks are formed into a plurality of chips, wherein the data length of each chip is the same, each chip comprises at least one macroblock, and the residual data blocks of the truncated macroblock in the previous chip are added to the tail position in the next chip after being reversely arranged;
and sending the plurality of chips to a decoding device so that the decoding device decodes each chip through forward decoding and reverse decoding to obtain the image.
2. The method of claim 1, wherein grouping all macroblocks into a plurality of chips comprises:
acquiring residual data blocks of a truncated macro block in a previous chip;
reversely arranging the residual data blocks, and adding the reversely arranged residual data blocks to the tail position of the chip to be processed;
sequentially adding each macro block which does not form the code slice from the initial position in the code slice to be processed until the data length of the code slice to be processed reaches a preset length, or all macro blocks do not have the macro blocks which do not form the code slice;
when all the macroblocks exist macroblocks which do not form the chips, acquiring the residual data blocks of the intercepted macroblocks in the chip to be processed, taking the next chip as the chip to be processed, and jumping to the following steps: and reversely arranging the residual data blocks, and adding the reversely arranged residual data blocks to the tail position in the chip to be processed.
3. The method according to claim 1 or 2, wherein acquiring the image to be processed comprises:
and acquiring an image acquired by the image sensor.
4. A method of decoding, comprising:
receiving a plurality of chips of an image transmitted by an encoding device, wherein the data length of each chip is the same, each chip comprises at least one macro block, and the residual data blocks of the macro block which is cut off in the previous chip are added to the tail position in the next chip after being arranged in a reverse direction;
and decoding each chip through forward decoding and backward decoding to obtain the image.
5. The method of claim 4, wherein decoding each slice by forward decoding and reverse decoding to obtain the image comprises:
for each chip, obtaining a first decoding result of the chip through forward decoding, obtaining a second decoding result of the chip through backward decoding, and calculating the first decoding result and the second decoding result according to a preset operation mode to obtain a residual data block of a macro block contained in the chip and/or a truncated macro block in the previous chip; when the chip comprises the residual data block of the macroblock which is cut off in the previous chip, combining the residual data block with the data block of the macroblock which is cut off in the previous chip to generate the macroblock which is cut off in the previous chip;
combining all macroblocks to generate the image.
6. The method of claim 5, wherein combining all macroblocks to generate the image comprises:
and performing Inverse Discrete Cosine Transform (IDCT) on all the macro blocks to obtain the image.
7. An encoding apparatus, comprising:
the acquisition module is used for acquiring an image to be processed;
the processing module is used for encoding the image into an image code stream, wherein the image code stream comprises a plurality of macro blocks which are arranged in the forward direction;
the processing module is further configured to group all the macroblocks into a plurality of chips, where each chip has the same data length, each chip includes at least one macroblock, and the remaining data blocks of the macroblock that was truncated in the previous chip are added to the end position in the next chip after being arranged in the reverse direction;
and the sending module is used for sending the plurality of code slices to decoding equipment so that the decoding equipment decodes each code slice through forward decoding and reverse decoding to obtain the image.
8. The apparatus of claim 7, wherein the processing module is specifically configured to:
acquiring residual data blocks of a truncated macro block in a previous chip;
reversely arranging the residual data blocks, and adding the reversely arranged residual data blocks to the tail position of the chip to be processed;
sequentially adding each macro block which does not form the code slice from the initial position in the code slice to be processed until the data length of the code slice to be processed reaches a preset length, or all macro blocks do not have the macro blocks which do not form the code slice;
when all the macroblocks exist macroblocks which do not form the chips, acquiring the residual data blocks of the intercepted macroblocks in the chip to be processed, taking the next chip as the chip to be processed, and jumping to the following steps: and reversely arranging the residual data blocks, and adding the reversely arranged residual data blocks to the tail position in the chip to be processed.
9. The apparatus according to claim 7 or 8, wherein the obtaining module is specifically configured to:
and acquiring an image acquired by the image sensor.
10. A decoding apparatus, comprising:
a receiving module, configured to receive multiple chips of an image sent by an encoding device, where the data length of each chip is the same, each chip includes at least one macroblock, and a remaining data block of a macroblock truncated in a previous chip is added to an end position in a next chip after being arranged in a reverse direction;
and the processing module is used for decoding each code slice through forward decoding and reverse decoding to obtain the image.
11. The apparatus of claim 10, wherein the processing module is specifically configured to:
for each chip, obtaining a first decoding result of the chip through forward decoding, obtaining a second decoding result of the chip through backward decoding, and calculating the first decoding result and the second decoding result according to a preset operation mode to obtain a residual data block of a macro block contained in the chip and/or a truncated macro block in the previous chip; when the chip comprises the residual data block of the macroblock which is cut off in the previous chip, combining the residual data block with the data block of the macroblock which is cut off in the previous chip to generate the macroblock which is cut off in the previous chip;
combining all macroblocks to generate the image.
12. The apparatus of claim 11, wherein the processing module is specifically configured to:
and performing Inverse Discrete Cosine Transform (IDCT) on all the macro blocks to obtain the image.
13. An encoding device, characterized by comprising: at least one processor and memory;
the memory stores computer-executable instructions;
the at least one processor executing the computer-executable instructions stored by the memory causes the at least one processor to perform the encoding method of any of claims 1-3.
14. A decoding device, characterized by comprising: at least one processor and memory;
the memory stores computer-executable instructions;
the at least one processor executing the computer-executable instructions stored by the memory causes the at least one processor to perform the decoding method of any of claims 4-6.
15. A computer-readable storage medium having stored thereon computer-executable instructions which, when executed by a processor, implement the encoding method of any one of claims 1-3.
16. A computer-readable storage medium having computer-executable instructions stored therein, which when executed by a processor, implement the decoding method of any one of claims 4-6.
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