CN111241765A

CN111241765A - SRAM type FPGA soft error fault tolerance method based on Boolean satisfiability

Info

Publication number: CN111241765A
Application number: CN202010133353.4A
Authority: CN
Inventors: 孙凌宇; 冷明; 冷子阳
Original assignee: Individual
Current assignee: Individual
Priority date: 2020-03-01
Filing date: 2020-03-01
Publication date: 2020-06-05

Abstract

The invention relates to a Boolean satisfiability-based SRAM type FPGA soft error fault tolerance method, which aims at the characteristics of logic resource irrelevant configuration words, idle configuration words and wiring resource interconnection configuration words of an SRAM type FPGA, utilizes implicit redundancy existing in an FPGA circuit, and tries to adopt the minimum area, power consumption and performance expenditure to slow down the soft errors of the FPGA configuration words and reduce the influence of the soft errors on the functions of an FPGA system while ensuring equivalent logic conversion of the circuit by carrying out logic synthesis on the original circuit again, thereby enhancing the fault tolerance capability of an FPGA chip, reducing the fault tolerance cost and improving the reliability of an FPGA device.

Description

SRAM type FPGA soft error fault tolerance method based on Boolean satisfiability

Technical Field

The invention relates to an FPGA soft error tolerance method, in particular to an SRAM type FPGA soft error tolerance method based on Boolean satisfiability.

Background

With the development of Very Large Scale Integration (VLSI) technology, the manufacturing process has moved from the deep submicron process age to the nanometer process age, and the blueprint report of international semiconductor technology predicts that the VLSI feature size is reduced to 5nm in 2020, which will result in increasingly reduced noise margin for Field Programmable Gate Arrays (FPGAs), increased sensitivity to high energy particle radiation and noise interference, and exponentially increased Soft Error Rate (SER). Research shows that faults caused by soft errors become important reasons for the functional failure of the FPGA, and the reliability of the FPGA device becomes a key factor for restricting the further development of the FPGA industry after performance and power consumption. Therefore, enhancing the soft error tolerance of the FPGA device is an urgent problem to be solved in the academic and industrial fields.

The Static Random Access Memory (SRAM) type FPGA adopts an SRAM unit to store a configuration word stream of configurable resources, and can accommodate more configuration word data with smaller chip area. However, the configuration word controlling the logic resource and the wiring resource of the SRAM type FPGA accounts for about 95% to 99% of the SRAM cell, and is very susceptible to high energy particle radiation and noise interference inside the circuit, and is abnormally charged or discharged, which causes a state error inside the circuit, and finally causes a failure of the circuit function.

The SRAM type FPGA device is very sensitive to the influence of soft errors, not only can the soft errors of FPGA logic resource configuration words change the logic functions of circuits of the FPGA device, but also the soft errors of FPGA wiring resource configuration words can change the structures of the circuits of the FPGA device, so that the functions of the FPGA device are invalid, and the serious influence caused by the soft errors of the configuration words can be eliminated until the FPGA device is refreshed for the next time. Therefore, the research on a soft error fault-tolerant method applicable to a Static Random Access Memory (SRAM) type FPGA is an urgent problem to be solved in the academic and industrial fields, and the solution of the problem can effectively reduce the probability of FPGA functional failure caused by soft errors and enhance the soft error fault-tolerant capability of the FPGA, thereby effectively improving the reliability of an FPGA device and promoting the rapid development of the FPGA industry.

In order to solve the problems, the soft error fault-tolerant method of the SRAM type FPGA aims at a logic resource irrelevant configuration word, a logic resource idle configuration word and a wiring resource interconnection configuration word, and enhances the soft error fault-tolerant capability of the FPGA at the lower fault-tolerant cost.

First, the logical resource independent configuration word related to the present invention: according to the statistical result of the total quantity distribution of irrelevant configuration words in the existing MCNC test circuit set, 15% -40% of configuration words in a lookup table (LUT) have the characteristics of the irrelevant configuration words, and the fact that the irrelevant configuration words are used for logically shielding soft errors is indicated to have a large optimization space. The invention increases the number of equivalent configuration word pairs as much as possible by reconfiguring the configuration bits with irrelevant configuration word characteristics in the LUT, so that the LUT can still generate expected output under the condition of wrong input, and the effect of logic shielding soft errors is realized to the maximum extent.

The invention relates to a logic resource idle configuration word: the FPGA is limited by logic synthesis software, and only 20% of resources such as LUTs, internal carry chains, adders and the like can be simultaneously utilized. A free input in the LUT means that half of the configuration word is in an idle state, making the LUT rarely and difficult to fully utilize. Aiming at a large number of idle configuration words, the optimal logic equivalent decomposition scheme is searched based on the in-place decomposition strategy, and the logic soft error shielding capability is optimized to the maximum extent by combining the in-place replication strategy.

Thirdly, the interconnection configuration word of the wiring resource related by the invention: the FPGA structural model mainly comprises a configurable logic Cell (CLB), a configurable connection switch box (CBOX) and a configurable exchange Switch Box (SBOX), wherein pins of the CLB are connected with wiring line rails in peripheral wiring channels through the CBOX, and wiring line rails in adjacent wiring channels are connected through the SBOX. CBOX and SBOX typically consist of configurable Multiplexers (MUXs) in which any one of the interconnect configuration words may change state due to soft errors, thereby changing the structure of the FPGA circuitry and causing the FPGA to fail. The invention fully utilizes the configurable characteristic of the logic polarity of the LUT and shields the soft errors of the interconnection configuration words on the wiring resources to the maximum extent, thereby enhancing the soft error tolerance capability of the wiring resources.

Disclosure of Invention

The invention relates to a hierarchical FPGA (field programmable gate array) layout and wiring method, which aims at the characteristics of an SRAM (static random access memory) type FPGA logic resource irrelevant configuration word, an idle configuration word and a wiring resource interconnection configuration word, utilizes implicit redundancy existing in an FPGA circuit, and tries to adopt the minimum area, power consumption and performance expenses while ensuring equivalent logic conversion of the circuit by carrying out logic synthesis on an original circuit again, thereby retarding soft errors of the FPGA configuration word and reducing the influence of the soft errors on the functions of an FPGA system.

The invention aims to provide a soft error fault-tolerant method of an SRAM type FPGA based on Boolean satisfiability aiming at the defects in the prior art, thereby enhancing the fault-tolerant capability of an FPGA chip, reducing the fault-tolerant cost and improving the reliability of an FPGA device. To achieve the above object, the present invention is conceived as follows.

The invention relates to a soft error tolerance of an SRAM type FPGA logic resource irrelevant configuration word: the present invention increases the number of equivalent configuration word pairs as much as possible by converting them into non-related configuration word in-place reconfigurations based on boolean satisfiability to enhance the logic soft error masking capability of the LUT to upstream circuits. First, the soft error sensitivity of each LUT node is sorted in a non-increasing order and the nodes are traversed in this order. Then, for each LUT node, a fan-in cone taking the LUT node as a sink point is established, and the LUTs in the cone are reconfigured in situ based on Boolean satisfiability, so that the number of equivalent configuration word pairs in the fan-in cone is increased to the maximum extent while the logic function and the topological structure of the original circuit are ensured, and the propagation of soft errors in the fan-in cone is minimized.

The invention relates to soft error tolerance of idle configuration words of SRAM type FPGA logic resources, which comprises the following steps: the invention can search equivalent logic implementation with less configuration words as much as possible by converting the equivalent logic into the in-place logic equivalent decomposition based on Boolean satisfiability, and optimize the soft error shielding capability of the logic to the maximum extent based on the mode of combining the in-place decomposition and the copy strategy. First, the soft error sensitivities of all LUT nodes are sorted in a non-increasing order, and the nodes are traversed according to the order. Then analyzing each LUT node, if the idle configuration word can contain the copy of the original logic, adopting an in-place copy strategy to shield the propagation of the soft error of the configuration word; otherwise, an in-situ logic equivalent decomposition strategy based on Boolean satisfiability is adopted, the logic function and the topological structure of the original circuit are ensured, an optimal logic equivalent decomposition scheme is searched, and the number of idle configuration words in the LUT is increased to the maximum extent. And then an in-place copy strategy is adopted to copy the equivalent logic and construct convergence logic so as to shield the propagation of configuration word soft errors.

The invention relates to a soft error tolerance of an interconnection configuration word of an SRAM type FPGA wiring resource, which comprises the following steps: the invention reduces the soft error sensitivity sum of the interconnection configuration word of the wiring resource as much as possible by converting the soft error sensitivity sum into the original logic polarity inversion based on Boolean satisfiability, and shields the interconnection configuration word soft error generated on the wiring resource to the maximum extent. First, a pseudo fan-in LUT group is constructed for each routing resource interconnect configuration word, including LUTs selected under normal conditions of the interconnect configuration word and LUTs selected after soft errors have occurred. And then solving the soft error sensitivity sum minimum optimization problem of the interconnection configuration words of the wiring resources according to the 'the sensitivity of the interconnection configuration words under the LUT logic polarity inversion is locally dependent on the pseudo fan-in LUT group', namely, the sensitivity local dependence theorem, and obtaining the configuration optimization scheme of the LUT logic polarity. Furthermore, truth table in-situ conversion based on Boolean satisfiability is carried out on each LUT, the logic polarity of the needed LUT is reversed, the logic function and the topological structure of the original circuit are ensured, the soft error fault-tolerant capability of wiring resources is enhanced, and the failure probability of the FPGA function is reduced.

According to the inventive concept, the technical scheme of the invention is realized as follows: a soft error fault-tolerant method of an SRAM type FPGA based on Boolean satisfiability is characterized by comprising the following specific steps.

Step 1, describing the FPGA design by using a hardware description language, and generating a hardware description language file of the FPGA design.

And 2, inputting a hardware description language file of FPGA design by means of a comprehensive tool xst of an ISE (hardware design suite) of Xilinx company, and generating an NGC netlist file after FPGA synthesis.

And 3, inputting the NGC netlist file and the UCF user constraint file by means of an ngdbuild translation tool of the hardware design suite ISE of Xilinx company, and generating the NGD netlist file after the FPGA translation is completed.

And 4, inputting the NGD netlist file by using a mapping tool map of the Xilinx company hardware design suite ISE, and generating an NCD binary circuit netlist file and a PCF physical constraint file which are mapped by the FPGA.

And 5, inputting the NCD binary circuit netlist file and the PCF physical constraint file which are mapped by the FPGA by using a layout and wiring tool par of the hardware design suite ISE of Xilinx company, and generating the NCD binary circuit netlist file after the FPGA is arranged and wired.

And 6, inputting PCF physical constraint files and NCD binary circuit netlist files after FPGA layout and wiring by using a simulation tool netgen after layout and wiring of the Xilinx company hardware design suite ISE, and generating a V netlist file after FPGA layout and wiring and an SDF (software development framework) delay file after FPGA layout and wiring for simulation.

And 7, inputting the NCD binary circuit netlist file after the FPGA is arranged and wired by means of a netlist conversion tool XDL of an ISE (hardware design kit) of Xilinx company, and generating an XDL netlist file after the FPGA is arranged and wired.

And 8, inputting a TESTBENCH test bed file for simulation, a V netlist file after FPGA layout and wiring and an SDF time delay file after FPGA layout and wiring by means of a simulation tool vsim of a ModelSim simulation suite in HDL hardware language of a Mentor company, and generating a VCD simulation waveform data file after FPGA layout and wiring.

And 9, generating an XDLRC chip netlist description file of the corresponding FPGA model in an FPGA chip database of Xilinx through the report function parameter by using a netlist conversion tool xdl of the hardware design suite ISE of Xilinx company.

Step 10, starting an FPGA soft error fault-tolerant program based on Boolean satisfiability, inputting an XDLRC chip netlist description file of a corresponding FPGA model, an XDL netlist file after FPGA layout and wiring, a VCD simulation result file after FPGA layout and wiring, and outputting the XDL netlist file with FPGA soft error fault-tolerant capability.

And 11, inputting an XDL netlist file with FPGA soft error fault tolerance by using a netlist conversion tool XDL of an ISE (hardware design kit) of Xilinx company, and generating an NCD (binary Circuit netlist) file with FPGA soft error fault tolerance.

And step 12, inputting an NCD (binary Circuit netlist) file with FPGA (field programmable Gate array) soft error fault tolerance by means of a configuration stream generation tool bitgen of an ISE (hardware design kit) of Xilinx company, and generating a BIT (BIT configuration stream) file with FPGA soft error fault tolerance.

In the above step 10, the steps of the FPGA soft error tolerance program based on boolean satisfiability are as follows.

And step 10.1, reading the XDLRC chip netlist description file, and performing lexical analysis, syntactic analysis, semantic analysis, intermediate code generation and extraction of logic resource configurable words and wiring resource configurable words of the FPGA chip.

And step 10.2, reading the XDL netlist file, and performing lexical analysis, syntax analysis, semantic analysis, intermediate code generation and extraction of logic configuration and configuration interconnection information of the circuit after the FPGA design layout and wiring.

And step 10.3, reading the VCD simulation waveform data file, and performing lexical analysis, syntactic analysis, semantic analysis, intermediate code generation and extraction of simulation waveform data after FPGA layout and wiring.

And step 10.4, based on logic configuration and configuration interconnection information realized by the circuit after layout and wiring of the FPGA design, logic resource configurable words and wiring resource configurable words of the FPGA chip, and combining simulation waveform data after layout and wiring of the FPGA, calculating the soft error sensitivity of each LUT node.

And step 10.5, reconfiguring logic resource independent configuration words of the FPGA design in situ based on Boolean satisfiability.

And step 10.6, reconfiguring idle configuration words of logic resources of the FPGA design in situ based on Boolean satisfiability.

And step 10.7, reconfiguring the wiring resource interconnection configuration words of the FPGA design in situ based on Boolean satisfiability.

And step 10.8, outputting an XDL netlist file with FPGA soft error fault tolerance capability by modifying the 0 → 1 or 1 → 0 bit inversion of the logic resource irrelevant configuration word, the logic resource idle configuration word and the wiring resource interconnection configuration word of the FPGA configuration word stream.

In the above step 10.1, the step of extracting the logic resource configurable word and the wiring resource configurable word of the FPGA chip of the XDLRC chip netlist description file is as follows.

Step 10.1.1, lexical analysis of the XDLRC chip information description file reads the XDLRC chip netlist description file one by one from left to right, and scans and decomposes the character stream constituting the source code, thereby recognizing the words one by one.

Step 10.1.2, the syntax analysis of the XDLRC chip information description file decomposes the word sequence into various syntax phrases on the basis of the lexical analysis, and determines whether the whole character stream forms a syntactically correct structure description file or not according to the syntax rules of the chip information description file.

And step 10.1.3, performing semantic analysis on the XDLRC chip information description file, checking whether semantic errors exist in the source code on the basis of the syntactic analysis, and collecting type information for the intermediate code generation stage.

And step 10.1.4, generating an intermediate code of the XDLRC chip information description file, generating the intermediate code of the source code on the basis of syntactic analysis and semantic analysis, and expressing the intermediate code by using an internal intermediate format.

Step 10.1.5, extracting configurable words of the XDLRC chip information description file, generating coordinates and names of Tile, Primitive, Wire and PIP resources contained in the XDLRC chip netlist description file corresponding to the FPGA model chip and interconnection structure information among the resources based on an internal intermediate format, analyzing programmable switches and configuration words contained in FPGA structural elements, and extracting logic resource configurable words and wiring resource configurable words of the FPGA chip.

In the step 10.2, the step of extracting the logic configuration and the configuration interconnection information realized by the FPGA design circuit of the XDL netlist file is as follows.

And 10.2.1, performing lexical analysis on the XDL netlist file, reading the XDL netlist file from left to right one by one, and scanning and decomposing a character stream forming a source code so as to recognize words one by one.

And 10.2.2, analyzing the syntax of the XDL netlist file, decomposing the word sequence into various syntax phrases on the basis of lexical analysis, and determining whether the whole character stream forms a grammatically correct structure description file or not according to the syntax rules of the netlist file.

And 10.2.3, performing semantic analysis on the XDL netlist file, checking whether semantic errors exist in the source code on the basis of the syntactic analysis, and collecting type information for the intermediate code generation stage.

And 10.2.4, generating an intermediate code of the XDL netlist file, and generating the intermediate code of the source code on the basis of syntactic analysis and semantic analysis, wherein the intermediate code is expressed by an internal intermediate format.

And 10.2.5, extracting the basic circuit information and the layout and wiring information of the XDL netlist file, generating Design modules, Inst modules and Net modules which are contained after the XDL netlist file corresponds to the FPGA Design layout and wiring based on the internal intermediate format, and extracting the logic configuration and configuration interconnection information realized by the FPGA Design circuit.

In the above step 10.3, the step of extracting the simulation waveform data after the FPGA layout wiring of the VCD simulation waveform data file is as follows.

Step 10.3.1, lexical analysis of the VCD simulation waveform data file, reading the VCD simulation waveform data file one by one from left to right, and scanning and decomposing the character stream constituting the source code, thereby recognizing individual words.

And step 10.3.2, carrying out syntactic analysis on the VCD simulation waveform data file, decomposing the word sequence into various syntactic phrases on the basis of lexical analysis, and determining whether the whole character stream forms a grammatically correct structure description file or not according to grammatical rules of the simulation waveform data file.

And 10.3.3, performing semantic analysis on the VCD simulation waveform data file, checking whether semantic errors exist in the source code on the basis of the syntactic analysis, and collecting type information for the intermediate code generation stage.

And 10.3.4, generating an intermediate code of the VCD simulation waveform data file, and generating the intermediate code of the source code on the basis of the syntactic analysis and the semantic analysis, wherein the intermediate code is expressed by an internal intermediate format.

And step 10.3.5, extracting the simulation waveform data of the VCD simulation waveform data file, generating value information of signal change caused by time increase based on the internal intermediate format, and extracting the simulation waveform data after FPGA layout and wiring.

In the above step 10.5, the step of reconfiguring the logic resource independent configuration word of the FPGA design in situ based on boolean satisfiability is as follows.

At step 10.5.1, the soft error sensitivities of each LUT node are sorted in a non-increasing order.

At step 10.5.2, the nodes are traversed in a non-increasing order, and a fan-in cone is created for each LUT node with it as the sink.

And 10.5.3, performing in-situ reconfiguration based on Boolean satisfiability on the LUT in the fan-in cone, and increasing the number of the configuration word pairs equivalent to the LUT in the fan-in cone to the maximum extent while ensuring the logic function and the topological structure of the original circuit.

In the above step 10.6, the step of reconfiguring the logic resource idle configuration word of the FPGA design in situ based on boolean satisfiability is as follows.

Step 10.6.1, non-increasing order sorting is performed on the soft error sensitivity of each LUT node.

And step 10.6.2, sequencing and traversing all nodes according to a non-increasing order, analyzing each LUT node, and if the idle configuration word of each LUT node can contain a copy of the original logic, adopting an in-place copy strategy to shield the propagation of the soft error of the configuration word.

And 10.6.3, sequencing and traversing each node according to a non-increasing order, analyzing each LUT node, if the idle configuration word of each LUT node can not contain the copy of the original logic, adopting an in-situ logic equivalent decomposition strategy based on Boolean satisfiability, searching a logic equivalent decomposition scheme to increase the number of the idle configuration words in the LUT to the maximum extent while ensuring the logic function and the topological structure of the original circuit, further adopting an in-situ copy strategy to copy the equivalent logic, and constructing convergence logic to shield the propagation of the soft errors of the configuration words.

In step 10.7, the step of reconfiguring the interconnection configuration word of the routing resource of the FPGA design in situ based on boolean satisfiability is as follows.

At step 10.7.1, a pseudo fan-in LUT set is constructed for each routing resource interconnect configuration word, including the LUT selected under normal conditions of the interconnect configuration word and the LUT selected after a soft error has occurred.

And 10.7.2, solving the optimization problem of the minimum soft error sensitivity sum of the interconnection configuration words of the wiring resources according to the local dependence theorem that the sensitivity of the interconnection configuration words under the LUT logic polarity inversion is locally dependent on the sensitivity of the pseudo-fanning-in LUT group, and obtaining the configuration optimization scheme of the LUT logic polarity.

And 10.7.3, performing in-situ conversion of truth table based on Boolean satisfiability on each LUT, and inverting the logic polarity of the corresponding LUT, so as to ensure the logic function and topology structure of the original circuit and enhance the soft error tolerance of the wiring resource.

Compared with the prior art, the invention has the following obvious and substantial characteristics and remarkable advantages.

The invention relates to a soft error tolerance of an SRAM type FPGA logic resource irrelevant configuration word: the logic resource independent configuration words of the FPGA device can be arbitrarily configured without any additional overhead if they are correct and error free. Aiming at a large number of irrelevant configuration words in the LUT, the method realizes maximization of the number of the equivalent configuration words of the irrelevant configuration words of the logic resources by equivalent in-situ reconfiguration of the logic circuit based on Boolean satisfiability by means of soft error sensitivity quantification of the logic resource configuration words of the FPGA, and effectively enhances the soft error shielding capability of the logic resources.

The invention relates to soft error tolerance of idle configuration words of SRAM type FPGA logic resources, which comprises the following steps: the logic resource idle configuration word of the FPGA device can be configured arbitrarily without adding any additional overhead because the logic resource idle configuration word is in an idle state. Aiming at a plurality of idle configuration words in the LUT, the invention increases the number of idle configuration words of logic resources to the maximum extent while ensuring the logic function and the topological structure of the original circuit through the Boolean satisfiability-based logic circuit equivalent in-situ decomposition, thereby duplicating the equivalent logic in situ and shielding the propagation of soft errors of the configuration words by means of convergence logic.

The invention relates to a soft error tolerance of an interconnection configuration word of an SRAM type FPGA wiring resource, which comprises the following steps: the LUT input and output polarities of the FPGA device can be arbitrarily inverted without adding any additional overhead. The invention aims at the interconnection configuration words of the wiring resources, realizes the minimization of the soft error sensitivity sum of the interconnection configuration words of the wiring resources by means of the quantitative evaluation of the soft error sensitivity of the FPGA, and further reverses the logic polarity of the required LUT (look-up table) through equivalent in-situ polarity reversal of a logic circuit based on Boolean satisfiability to shield soft errors, thereby effectively enhancing the soft error fault-tolerant capability of the wiring resources.

Drawings

The objects, specific structural features and advantages of the present invention will be further understood from the following description of an example of a soft error tolerant method of a boolean satisfiability based SRAM type FPGA in accordance with the present invention in conjunction with the accompanying drawings.

FIG. 1 is a flow chart of the soft error tolerant method of SRAM type FPGA based on Boolean satisfiability of the present invention.

FIG. 2 is a flow chart of the present invention Boolean satisfiability based FPGA soft error fault tolerance program.

FIG. 3 is a flow chart of logic resource configurable words and routing resource configurable words of an FPGA chip for extracting an XDLRC chip netlist description file according to the present invention.

FIG. 4 is a flow chart of the logic configuration and configuration interconnection information for an FPGA design circuit implementation of the present invention for extracting an XDL netlist file.

Fig. 5 is a flowchart of the simulation waveform data after the FPGA layout wiring of the VCD simulation waveform data file is extracted according to the present invention.

FIG. 6 is a flow diagram of the present invention for in-place reconfiguration of logic resource independent configuration words of an FPGA design based on Boolean satisfiability.

FIG. 7 is a flow chart of the present invention for in-place reconfiguration of logic resource idle configuration words of an FPGA design based on Boolean satisfiability.

FIG. 8 is a flow diagram of the present invention for in-place reconfiguration of routing resource interconnect configuration words of an FPGA design based on Boolean satisfiability.

FIG. 9 is an example of the present invention's in-place reconfiguration of logical resource independent configuration words to mask independent configuration word soft errors based on Boolean satisfiability.

FIG. 10 is a block diagram illustrating an example of the present invention for in-place reconfiguration of a logical resource idle configuration word to mask idle configuration word soft errors using an in-place copy policy.

FIG. 11 is an example of the present invention adopting in-place disassembly and replication strategy to reconfigure a logical resource idle configuration word in-place to mask idle configuration word soft errors.

Fig. 12 is an example of the present invention employing a LUT logic polarity forced inversion strategy to reconfigure routing resource interconnect configuration words in-place to reduce interconnect configuration word soft errors.

Detailed Description

In order to clearly understand the technical content of the soft error tolerance method of the SRAM type FPGA based on Boolean satisfiability, the following examples are specifically given for detailed description.

The flow chart of the soft error tolerance method of the SRAM type FPGA based on boolean satisfiability in this embodiment is shown in fig. 1, and the steps are as follows.

And A01, describing the FPGA design by using a hardware description language, and generating a hardware description language file of the FPGA design.

A02, inputting a hardware description language file of FPGA design by means of a synthesis tool xst of an ISI (hardware design kit) of Xilinx company, and generating an NGC netlist file after FPGA synthesis.

A03, inputting an NGC netlist file and a UCF user constraint file by a translation tool ngdbuild of an ISE (hardware design kit) of Xilinx company, and generating an NGD netlist file after FPGA translation is completed.

A04, inputting an NGD netlist file by using a mapping tool map of an Xilinx company hardware design suite ISE, and generating an NCD binary circuit netlist file and a PCF physical constraint file which are mapped by an FPGA.

A05, inputting the NCD binary circuit netlist file and the PCF physical constraint file mapped by the FPGA by using a layout and wiring tool par of an ISE (hardware design kit) of Xilinx company, and generating the NCD binary circuit netlist file after the FPGA is laid out and wired.

A06, inputting PCF physical constraint files and NCD binary circuit netlist files after FPGA layout and wiring by means of a simulation tool netgen after layout and wiring of an ISE (hardware design kit) of Xilinx company, and generating a V netlist file after FPGA layout and wiring and an SDF (software development framework) delay file after FPGA layout and wiring for simulation.

A07, inputting an NCD binary circuit netlist file after FPGA layout and wiring by means of a netlist conversion tool XDL of an ISE (hardware design kit) of Xilinx company, and generating an XDL netlist file after FPGA layout and wiring.

A08, inputting a TESTBENCH test bed file for simulation, a V netlist file after FPGA layout and wiring and an SDF time delay file after FPGA layout and wiring by means of a simulation tool vsim of ModelSim of HDL hardware language simulation suite of Mentor company, and generating a VCD simulation waveform data file after FPGA layout and wiring.

A09, generating an XDLRC chip netlist description file of a corresponding FPGA model in an FPGA chip database of Xilinx through report function parameters by using a netlist conversion tool xdl of Xilinx company hardware design suite ISE.

A10, starting FPGA soft error fault-tolerant program based on Boolean satisfiability, inputting XDLRC chip netlist description file of corresponding FPGA model, XDL netlist file after FPGA layout and wiring, VCD simulation result file after FPGA layout and wiring, and outputting XDL netlist file with FPGA soft error fault-tolerant capability.

A11, inputting an XDL netlist file with FPGA soft error fault tolerance capability by means of a netlist conversion tool XDL of an ISI (hardware design kit) of Xilinx company, and generating an NCD (binary Circuit netlist) file with FPGA soft error fault tolerance capability.

A12, inputting an NCD binary circuit netlist file with FPGA soft error fault tolerance capability by means of a configuration stream generation tool bitgen of an ISE (hardware design kit) of Xilinx company, and generating a BIT configuration stream file with FPGA soft error fault tolerance capability.

The flow chart of the soft error tolerant program of the FPGA based on boolean satisfiability of the present embodiment is shown in fig. 2, and the steps are as follows.

B01, reading the XDLRC chip netlist description file, and performing lexical analysis, syntax analysis, semantic analysis, intermediate code generation and extraction of logic resource configurable words and wiring resource configurable words of the FPGA chip.

B02, reading the XDL netlist file, performing lexical analysis, syntax analysis, semantic analysis, intermediate code generation and extracting logic configuration and configuration interconnection information of the circuit implementation after FPGA design layout and wiring.

And B03, reading the VCD simulation waveform data file, and performing lexical analysis, syntactic analysis, semantic analysis, intermediate code generation and extraction of simulation waveform data after FPGA layout and wiring.

And B04, calculating the soft error sensitivity of each LUT node based on the logic configuration and configuration interconnection information realized by the circuit after layout and wiring of the FPGA design, the logic resource configurable word and the wiring resource configurable word of the FPGA chip, and the simulation waveform data after layout and wiring of the FPGA.

B05, reconfiguring in-place logic resource independent configuration words of the FPGA design based on boolean satisfiability.

B06, reconfiguring logic resource idle configuration words of the FPGA design in situ based on Boolean satisfiability.

B07, reconfiguring in-place the routing resource interconnect configuration words of the FPGA design based on boolean satisfiability.

B08, modifying the 0 → 1 or 1 → 0 bit inversion of the logic resource irrelevant configuration word, the logic resource idle configuration word and the wiring resource interconnection configuration word of the FPGA configuration word flow, and outputting the XDL netlist file with FPGA soft error fault tolerance capability.

The flowchart of the logic resource configurable word and the routing resource configurable word of the FPGA chip for extracting the XDLRC chip netlist description file in this embodiment is shown in fig. 3, and the steps are as follows.

C01, lexical analysis of the XDLRC chip information description file, reading the XDLRC chip netlist description file one by one from left to right, and scanning and decomposing the character stream forming the source code so as to recognize the words one by one.

C02, syntax analysis of XDLRC chip information description file, decomposing word sequence into various syntax phrases on the basis of lexical analysis, and determining whether the whole character stream forms a syntactically correct structure description file according to the syntax rules of the chip information description file.

C03, semantic analysis of XDLRC chip information description file, checking whether semantic error exists in source code on the basis of syntax analysis, and collecting type information for intermediate code generation stage.

C04, generating an intermediate code of the XDLRC chip information description file, generating the intermediate code of the source code on the basis of syntactic analysis and semantic analysis, and expressing the intermediate code by using an internal intermediate format.

C05, extracting configurable words of the XDLRC chip information description file, generating coordinates and names of Tile, Primitive, Wire and PIP resources contained in the XDLRC chip netlist description file corresponding to the FPGA model chip and interconnection structure information among the resources based on the internal intermediate format, analyzing programmable switches and configuration words contained in FPGA structural elements, and extracting logic resource configurable words and wiring resource configurable words of the FPGA chip.

The flowchart of the logic configuration and configuration interconnection information implemented by the FPGA design circuit for extracting the XDL netlist file in this embodiment is shown in fig. 4, and the steps are as follows.

D01, lexical analysis of the XDL netlist file, reading the XDL netlist file one by one from left to right, and scanning and decomposing the character stream forming the source code so as to recognize the words one by one.

D02, syntax analysis of XDL netlist file, decomposing word sequence into various syntax phrases based on lexical analysis, and determining whether the whole character stream forms a syntactically correct structure description file according to the syntax rule of netlist file.

D03, semantic analysis of the XDL netlist file, checking whether semantic errors exist in the source code on the basis of syntactic analysis, and collecting type information for the intermediate code generation stage.

D04, generating intermediate code of the XDL netlist file, generating the intermediate code of the source code on the basis of syntax analysis and semantic analysis, and expressing the intermediate code by using an internal intermediate format.

D05, extracting circuit basic information and layout and wiring information of the XDL netlist file, generating Design modules, Inst modules and Net modules which are contained after the XDL netlist file corresponds to FPGA Design layout and wiring based on an internal intermediate format, and extracting logic configuration and configuration interconnection information realized by the FPGA Design circuit.

The flowchart of the simulation waveform data after the FPGA layout and wiring of the VCD simulation waveform data file is extracted in this embodiment is shown in fig. 5, and the steps are as follows.

E01, lexical analysis of the VCD simulation waveform data file, reading the VCD simulation waveform data file one by one from left to right, and scanning and decomposing the character stream constituting the source code, thereby recognizing individual words.

E02, parsing the VCD simulation waveform data file, decomposing the word sequence into various grammatical phrases on the basis of lexical analysis, and determining whether the whole character stream forms a grammatically correct structure description file or not according to grammatical rules of the simulation waveform data file.

E03, semantic analysis of the VCD simulation waveform data file, checking whether semantic errors exist in the source code on the basis of the syntactic analysis, and collecting type information for the intermediate code generation stage.

E04, generating an intermediate code of the VCD simulation waveform data file, generating the intermediate code of the source code based on the syntax analysis and the semantic analysis, and expressing the intermediate code in an internal intermediate format.

E05, extracting the simulation waveform data of the VCD simulation waveform data file, generating value information of signal change due to time increase based on the internal intermediate format, and extracting the simulation waveform data after the FPGA is laid out and wired.

The flowchart of the logic resource independent configuration word for in-place reconfiguration of an FPGA design based on boolean satisfiability of the present embodiment is shown in fig. 6, and the steps are as follows.

F01, sorting the soft error sensitivity of each LUT node in a non-increasing order.

F02, traversing each node according to non-increasing sequence, and establishing a fan-in cone taking the node as a sink for each LUT node.

And F03, performing in-place reconfiguration based on Boolean satisfiability on the LUT in the fan-in cone, and increasing the number of the configuration word pairs equivalent to the LUT in the fan-in cone to the maximum extent while ensuring the logic function and the topological structure of the original circuit.

The flowchart of the logic resource idle configuration word for the in-place reconfiguration FPGA design based on boolean satisfiability in this embodiment is shown in fig. 7, and includes the following steps.

G01, sorting the soft error sensitivity of each LUT node in a non-increasing order.

G02, sequencing and traversing each node according to a non-increasing order, analyzing each LUT node, and if the idle configuration word of each LUT node can contain the copy of the original logic, adopting an in-place copy strategy to shield the propagation of the soft error of the configuration word.

G03, sequencing and traversing each node according to a non-increasing order, analyzing each LUT node, if the idle configuration word of each LUT node can not accommodate the copy of the original logic, adopting an in-situ logic equivalent decomposition strategy based on Boolean satisfiability, searching a logic equivalent decomposition scheme to increase the number of the idle configuration words in the LUT to the maximum extent while ensuring the logic function and the topological structure of the original circuit, further adopting an in-situ copy strategy to copy the equivalent logic, and constructing convergence logic to shield the propagation of the soft errors of the configuration words.

The flow chart of the routing resource interconnection configuration word for the in-place reconfiguration FPGA design based on boolean satisfiability of the present embodiment is shown in fig. 8, with the following steps.

H01, constructing a pseudo fan-in LUT group for each routing resource interconnection configuration word, including the LUT selected under normal conditions of the interconnection configuration word and the LUT selected after soft errors occur.

H02, solving the optimization problem of minimum soft error sensitivity sum of interconnection configuration words of wiring resources according to the local dependence theorem that the sensitivity of the interconnection configuration words under the LUT logic polarity inversion is locally dependent on the sensitivity of the pseudo-fan-in LUT group, and obtaining the configuration optimization scheme of the LUT logic polarity.

H03, carrying out truth table in-situ conversion based on Boolean satisfiability on each LUT, inverting the logic polarity of the corresponding LUT, ensuring the logic function and topological structure of the original circuit, and enhancing the soft error tolerance capability of the wiring resource.

An example of the boolean satisfiability-based in-place reconfiguration of logic resource independent configuration words to mask independent configuration word soft errors is shown in fig. 9, where the left diagram implements circuit logic using 4 LUT lookup tables, the LUT lookup table 101 of L4, the LUT lookup table 104 of L3, the LUT lookup table 102 of L2, and the LUT lookup table 103 of L1, and the right diagram implements circuit logic using 4 LUT lookup tables, the LUT lookup table 201 of L4, the LUT lookup table 204 of L3, the LUT lookup table 202 of L2, and the LUT lookup table 203 of L1. The circuit of the left diagram and the circuit, circuit logic and connection relation of the right diagramSame as the topology, except for the configuration word C of the LUT look-up table 101 and the LUT look-up table 201₁₁Different. Since the circuits of the left and right diagrams cannot access the configuration words C of the LUT look-up tables 101 and 201 without errors and correctly₁₁And thus the configuration word C of the LUT look-up table 101 and 201₁₁Is an irrelevant configuration word. When the LUT of the left image L4 looks up C of the table 101₁₁When configured as 0, the LUT look-up table 101 of L4 inputs Z₁The LUT lookup table 101 of the configuration word pair of { L (2 'b 00), L (2' b10) } and { L (2 'b 01), L (2' b11) }, L4 inputs Z₂The pair of configuration words of (1) { L (2 'b 00), L (2' b01) } and { L (2 'b 10), L (2' b11) } are not identical at all and cannot mask L₄LUT of (1) look up soft errors for the table 101 input. In contrast, when the LUT of the right graph L4 looks up C of the table 201₁₁When configured as 1, LUT lookup table 201 of L4 inputs Z₁The LUT look-up table 201 of the configuration word pair { L (2 'b 01), L (2' b11) }, L4 inputs Z₂Is equal to the pair of configuration words { L (2 'b 10), L (2' b11) }. Suppose L₄Input Z₁Or Z₂An SEU soft error of 0 → 1 occurs, resulting in L₄From access configuration word C₀₁Or C₁₀Becomes erroneously accessed to the configuration word C₁₁，L₄Still 1 can be correctly output, the equivalent configuration word pair effectively masks the input Z₁Or Z₂The SEU soft error reduces the soft error rate.

An example of adopting the in-place copy policy to reconfigure the idle configuration word of the logic resource in-place to shield the soft error of the idle configuration word in the embodiment is shown in fig. 10, where 301 is a 6-LUT using only 5 inputs; 302 copies the 32-bit configuration word of the 5-input LUT to a copy, places it in the 32-bit idle configuration word of the 6-LUT, and then puts the original logic F₁And logical copy F₂Forming convergence logic F as the output of LUT through AND gate; 303 copying the copy of the original logic in the idle configuration word of the LUT, and then constructing the required convergence logic by using the dual-output structure and carry chain in the LUT, and passing through C_inConfigured, carry logic C_out=F₁·F₂＋F₁·C_in＋C_in·F₂Selection of original logic F capable of meeting convergence logic₁And logical copy F₂To control the effect of soft errors within the LUT.

An example of the present embodiment for in-place reconfiguration of a logic resource idle configuration word to mask idle configuration word soft errors by adopting in-place decomposition and copy policy is shown in FIG. 11, where for logic F shown in 401, solving convergence logic ⊙ decomposes F into two sub-logic Fs₁And F₂And F = ⊙ (F)₁,F₂) Let the sub-logic F shown at 402₁And F₂The 6-input AND gate of 403 is broken down into two 3-input AND gates of 404 AND is equivalent to the original logic under the convergence logic of the 2-input AND gate, thus, the 64-bit configuration word required by the original logic of 403 reduces the 16-bit configuration word required by the two 3-input AND gates of 404 AND the carry chain required by the 2-input AND gate, effectively increasing the idle configuration word, then a copy of ⊙ is made at 405 based on an in-place copy policy (F ⊙)₁,F₂) AND then the output of the original logic AND the logic copy is used as the final output of the LUT through a 2-input AND gate, thereby effectively shielding the propagation of soft errors of the configuration words.

An example of the present embodiment for in-place reconfiguration of routing resource interconnect configuration words to reduce interconnect configuration word soft errors using LUT logic polarity forcing inversion strategy is shown in fig. 12 for MUX 501_mFunction ofobserv(m) Indicating by interconnect configuration wordb _kAnd if the output error of the multiplexer caused by the soft error is propagated to an output pin of the FPGA. Thus, the configuration word is interconnectedb _kHas a soft error rate ofSER(b_k)=(v(i)⊕v(j))·observ(m). 502 pass pair MUX_mThe logic polarity of the input j port is forced to reverse, effectively shielding the interconnection configuration wordb _kError output resulting from soft errors. Data analysis shows that the soft error rate SER of the interconnection configuration word of this example is reduced from 74% at 503 to 26% at 504.

Claims

1. A Boolean satisfiability-based SRAM type FPGA soft error fault tolerance method is characterized by comprising the following specific steps:

step 1, describing the FPGA design by using a hardware description language, and generating a hardware description language file of the FPGA design;

step 2, inputting a hardware description language file of FPGA design by means of a comprehensive tool xst of an ISE (hardware design suite) of Xilinx company, and generating an NGC netlist file after FPGA synthesis;

step 3, inputting an NGC netlist file and a UCF user constraint file by means of a translation tool ngdbuild of an ISE (hardware design kit) of Xilinx company, and generating an NGD netlist file after FPGA translation is completed;

step 4, inputting an NGD netlist file by using a mapping tool map of an ISI (hardware design kit) of Xilinx company, and generating an NCD binary circuit netlist file and a PCF (physical constraint of fiber) file mapped by the FPGA;

step 5, inputting the NCD binary circuit netlist file and the PCF physical constraint file mapped by the FPGA by using a layout and wiring tool par of the hardware design suite ISE of Xilinx company to generate the NCD binary circuit netlist file after the FPGA is arranged and wired;

step 6, inputting PCF physical constraint files and NCD binary circuit netlist files after FPGA layout and wiring by using a simulation tool netgen after layout and wiring of an ISI (integrated service environment) of a Xilinx company hardware design kit, and generating a V netlist file after FPGA layout and wiring and an SDF (software development framework) delay file after FPGA layout and wiring for simulation;

step 7, inputting an NCD binary circuit netlist file after FPGA layout and wiring by means of a netlist conversion tool XDL of an ISE (hardware design kit) of Xilinx company, and generating an XDL netlist file after FPGA layout and wiring;

step 8, inputting a TESTBENCH test bed file for simulation, a V netlist file after FPGA layout and wiring and an SDF time delay file after FPGA layout and wiring by means of a simulation tool vsim of a ModelSim simulated by HDL hardware language simulation suite of a Mentor company, and generating a VCD simulation waveform data file after FPGA layout and wiring;

step 9, generating an XDLRC chip netlist description file of a corresponding FPGA model in an FPGA chip database of Xilinx through report functional parameters by means of a netlist conversion tool xdl of a hardware design suite ISE of Xilinx company;

step 10, starting an FPGA soft error fault-tolerant program based on Boolean satisfiability, inputting an XDLRC chip netlist description file of a corresponding FPGA model, an XDL netlist file after FPGA layout and wiring, and a VCD simulation result file after FPGA layout and wiring, and outputting an XDL netlist file with FPGA soft error fault-tolerant capability;

step 11, inputting an XDL netlist file with FPGA soft error fault-tolerant capability by using a netlist conversion tool XDL of an ISE (hardware design kit) of Xilinx company, and generating an NCD (binary Circuit netlist) file with FPGA soft error fault-tolerant capability;

step 12, inputting an NCD (binary Circuit netlist) file with FPGA (field programmable Gate array) soft error fault tolerance by means of a configuration stream generation tool bitgen of an ISE (hardware design kit) of Xilinx company, and generating a BIT (BIT configuration stream) file with FPGA soft error fault tolerance;

in the step 10, the step of the FPGA soft error tolerance program based on boolean satisfiability is as follows:

step 10.1, reading an XDLRC chip netlist description file, and performing lexical analysis, syntactic analysis, semantic analysis, intermediate code generation and extraction of logic resource configurable words and wiring resource configurable words of the FPGA chip;

step 10.2, reading an XDL netlist file, and performing lexical analysis, syntax analysis, semantic analysis, intermediate code generation and extraction of logic configuration and configuration interconnection information of the circuit implementation after FPGA design layout and wiring;

step 10.3, reading a VCD simulation waveform data file, and performing lexical analysis, syntactic analysis, semantic analysis, intermediate code generation and extraction of simulation waveform data after FPGA layout and wiring;

step 10.4, based on the logic configuration and the configuration interconnection information realized by the circuit after the layout and wiring of the FPGA design, the logic resource configurable word and the wiring resource configurable word of the FPGA chip, and combining the simulation waveform data after the layout and wiring of the FPGA, calculating the soft error sensitivity of each LUT node;

step 10.5, reconfiguring logic resource irrelevant configuration words of the FPGA design in situ based on Boolean satisfiability;

step 10.6, reconfiguring logic resource idle configuration words of the FPGA design in situ based on Boolean satisfiability;

step 10.7, reconfiguring wiring resource interconnection configuration words of the FPGA design in situ based on Boolean satisfiability;

step 10.8, outputting an XDL netlist file with FPGA soft error fault tolerance capability by modifying the 0 → 1 or 1 → 0 bit inversion of a logic resource irrelevant configuration word, a logic resource idle configuration word and a wiring resource interconnection configuration word of the FPGA configuration word flow;

in the step 10.1, the step of extracting the logic resource configurable word and the wiring resource configurable word of the FPGA chip of the XDLRC chip netlist description file is as follows:

step 10.1.1, lexical analysis of the XDLRC chip information description file, reading the XDLRC chip netlist description file one by one from left to right, and scanning and decomposing the character stream forming the source code, thereby identifying the words one by one;

step 10.1.2, the syntax analysis of the XDLRC chip information description file decomposes the word sequence into various syntax phrases on the basis of lexical analysis, and determines whether the whole character stream forms a syntactically correct structure description file or not according to the syntax rules of the chip information description file;

step 10.1.3, performing semantic analysis on the XDLRC chip information description file, checking whether semantic errors exist in the source code on the basis of the syntactic analysis, and collecting type information for the intermediate code generation stage;

step 10.1.4, generating an intermediate code of the XDLRC chip information description file, generating the intermediate code of the source code on the basis of syntactic analysis and semantic analysis, and expressing the intermediate code by using an internal intermediate format;

step 10.1.5, extracting configurable words of the XDLRC chip information description file, generating coordinates and names of Tile, Primitive, Wire and PIP resources contained in the XDLRC chip netlist description file corresponding to the FPGA model chip and interconnection structure information among the resources based on an internal intermediate format, analyzing a programmable switch and configuration words thereof contained in FPGA structural elements, and extracting logic resource configurable words and wiring resource configurable words of the FPGA chip;

in the step 10.2, the step of extracting the logic configuration and the configuration interconnection information realized by the FPGA design circuit of the XDL netlist file is as follows:

step 10.2.1, performing lexical analysis on the XDL netlist file, reading the XDL netlist file from left to right one by one, and scanning and decomposing a character stream forming a source code so as to recognize words;

step 10.2.2, syntax analysis of the XDL netlist file, which decomposes the word sequence into various syntax phrases on the basis of lexical analysis, and determines whether the whole character stream forms a grammatically correct structural description file according to the syntax rules of the netlist file;

10.2.3, performing semantic analysis on the XDL netlist file, checking whether semantic errors exist in the source code on the basis of the syntactic analysis, and collecting type information for the intermediate code generation stage;

10.2.4, generating an intermediate code of the XDL netlist file, generating the intermediate code of the source code on the basis of syntactic analysis and semantic analysis, and expressing the intermediate code by using an internal intermediate format;

step 10.2.5, extracting circuit basic information and layout and wiring information of the XDL netlist file, generating Design modules, Inst modules and Net modules which are contained after the XDL netlist file corresponds to FPGA Design layout and wiring based on an internal intermediate format, and extracting logic configuration and configuration interconnection information realized by the FPGA Design circuit;

in the step 10.3, the step of extracting the simulation waveform data after the FPGA layout wiring of the VCD simulation waveform data file is performed is as follows:

step 10.3.1, lexical analysis of the VCD simulation waveform data file, reading the VCD simulation waveform data file one by one from left to right, and scanning and decomposing the character stream constituting the source code, thereby identifying words one by one;

step 10.3.2, the syntax analysis of the VCD simulation waveform data file decomposes the word sequence into various syntax phrases on the basis of the lexical analysis, and determines whether the whole character stream forms a syntactically correct structure description file or not according to the syntax rules of the simulation waveform data file;

10.3.3, performing semantic analysis on the VCD simulation waveform data file, checking whether semantic errors exist in the source code on the basis of the syntactic analysis, and collecting type information for the intermediate code generation stage;

10.3.4, generating an intermediate code of the VCD simulation waveform data file, generating the intermediate code of the source code on the basis of the syntactic analysis and the semantic analysis, and expressing the intermediate code by using an internal intermediate format;

10.3.5, extracting the simulation waveform data of the VCD simulation waveform data file, generating value information of signal change caused by time increase based on an internal intermediate format, and extracting the simulation waveform data after FPGA layout and wiring;

in the above step 10.5, the step of reconfiguring the logic resource independent configuration word of the FPGA design in situ based on boolean satisfiability is as follows:

step 10.5.1, sorting the soft error sensitivities of each LUT node in a non-increasing order;

step 10.5.2, traversing each node according to non-increasing sequence, and establishing a fan-in cone with each LUT node as a sink;

step 10.5.3, performing in-situ reconfiguration based on Boolean satisfiability on the LUT in the fan-in cone, and increasing the number of the configuration word pairs equivalent to the LUT in the fan-in cone to the maximum extent while ensuring the logic function and topology structure of the original circuit;

in the above step 10.6, the step of reconfiguring the logic resource idle configuration word of the FPGA design in situ based on boolean satisfiability includes:

step 10.6.1, non-increasing sequence sorting is carried out on the soft error sensitivity of each LUT node;

step 10.6.2, sequencing and traversing each node according to a non-increasing order, analyzing each LUT node, and if the idle configuration word of each LUT node can contain the copy of the original logic, adopting an in-place copy strategy to shield the propagation of the soft error of the configuration word;

step 10.6.3, sequencing and traversing each node according to a non-increasing order, analyzing each LUT node, if the idle configuration word of each LUT node can not accommodate the copy of the original logic, adopting an in-situ logic equivalent decomposition strategy based on Boolean satisfiability, searching a logic equivalent decomposition scheme to increase the number of the idle configuration words in the LUT to the maximum extent while ensuring the logic function and the topological structure of the original circuit, further adopting an in-situ copy strategy to copy the equivalent logic, and constructing convergence logic to shield the propagation of the soft error of the configuration word;

in the above step 10.7, the step of reconfiguring in-place the interconnection configuration word of the routing resource of the FPGA design based on boolean satisfiability is as follows:

step 10.7.1, constructing a pseudo fan-in LUT group for each interconnection configuration word of the wiring resources, wherein the LUT group comprises the LUT selected under the normal condition of the interconnection configuration word and the LUT selected after the soft error occurs;

step 10.7.2, solving the problem of minimum soft error sensitivity sum optimization of interconnection configuration words of wiring resources according to the local dependence theorem that the sensitivity of interconnection configuration words under the LUT logic polarity inversion depends on the sensitivity of the pseudo-fanning-in LUT group, and obtaining the configuration optimization scheme of the LUT logic polarity;