CN111221685A - Physical memory detection method, device, equipment and readable storage medium - Google Patents
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Abstract
The text discloses a physical memory detection method, a physical memory detection device and a readable storage medium, which belong to the technical field of communication, wherein the method comprises the following steps: copying the memory test program from the bootstrap program to a second-level cache; running the memory test program, and outputting a physical memory test result, wherein the memory test result is a test passing area or a test failing area; when the test result comprises a test passing area, copying the bootstrap program to the test passing area to continue running; when the physical memory is completely damaged, stopping running and suspending the CPU; the memory test program is copied to the second-level cache to test the integrity of the physical memory, so that the position of the fault memory particle can be accurately positioned.
Description
Technical Field
The present disclosure relates to the field of communications technologies, and in particular, to a method, an apparatus, a device, and a readable storage medium for physical memory detection.
Background
Generally, the process of the embedded device starting the boot phase is as follows: the equipment is powered on, a bootstrap program is copied from the ROM to the main physical memory RAM, the bootstrap program is executed, the CPU/SOC and the small system are initialized in the bootstrap program, the memory is tested, other peripheral equipment is initialized, and then an interactive command line is entered or a system mirror image is loaded for starting. The memory test program is used for testing only a small section of memory with high starting speed, and whether other areas of the memory have problems cannot be known.
In the boot stage under a general condition, if there is a problem with the memory granule and the related circuit of the main physical memory, the following three conditions are caused:
1. the main physical memory and the related circuit of the boot program are loaded and operated to cause problems; in this case, the bootstrap program cannot run, the CPU is hung up or restarted, and the debugging interface has no output; under the phenomenon, the fault positioning means is less and the positioning process is complex; even if the memory problem is identified, it cannot be excluded whether other areas of the memory have problems, and the conventional operation is to remove all memory particles and re-weld them.
2. The section of the memory and the related circuits in the boot program and the test interval are loaded and operated without problems, but other areas of the memory have problems; in this case, memory problems may be revealed in the subsequent boot system phase or system operation phase, which typically results in a hang-up or reboot of the system. Such a system hangs up or abnormally restarts such a failure, and the locating process will be time consuming and laborious.
3. The testing fails in the section of the memory testing; in this case, it can be determined that the memory has a problem, but it is unclear whether the memory outside the test interval has a problem, and the research and development personnel needs to continue positioning by using another means.
Disclosure of Invention
The invention provides a physical memory detection method, a physical memory detection device, physical memory detection equipment and a readable storage medium, wherein the physical memory is subjected to integrity test by copying a memory test program into a secondary cache, so that the position of a fault memory particle can be accurately positioned.
The technical scheme adopted for solving the technical problems is as follows:
according to an aspect of the present disclosure, a method for detecting a physical memory is provided, including:
copying the memory test program from the bootstrap program to a second-level cache;
running the memory test program, and outputting a physical memory test result, wherein the memory test result is a test passing area or a test failing area;
when the test result comprises a test passing area, copying the bootstrap program to the test passing area to continue running;
and when the physical memory is completely damaged, stopping running and suspending the CPU.
Optionally, after the running the memory test program and outputting the physical memory test result, the method further includes:
and when the test result comprises the area which does not pass the test, outputting the position of the area which does not pass the test.
Optionally, before copying the memory test program from the boot program to the secondary cache, the method further includes:
initializing a CPU and a memory management unit MMU, and configuring a secondary cache as a static random access memory SRAM; and enabling the memory management unit and the first-level cache.
Optionally, before copying the memory test program from the boot program to the secondary cache, the method further includes:
the CPU initialization configuration is copied from the boot program to the secondary cache.
Optionally, before the running the memory test program and outputting the physical memory test result, the method further includes:
and initializing a CPU memory controller and a universal asynchronous receiver-transmitter interface UART.
Optionally, the initialization CPU and the memory management unit MMU configure the second level cache as a static random access memory SRAM; before enabling the memory management unit and the first-level cache, the method further comprises:
when the boot program is stored in the firmware, jumping to the firmware code to obtain the boot program.
Optionally, the initialization CPU and the memory management unit MMU configure the second level cache as a static random access memory SRAM; before enabling the memory management unit and the first-level cache, the method further comprises:
and when the bootstrap program is stored in the NandFlash/Eeprom, the bootstrap program is obtained from the NandFlash/Eeprom according to the hardware configuration.
According to another aspect of the present disclosure, there is provided a physical memory detecting apparatus, including:
the cache module is used for copying the memory test program from the bootstrap program to the second-level cache;
the test module is used for operating the memory test program and outputting a physical memory test result, wherein the memory test result is a test passing area or a test failing area;
the running module is used for copying the bootstrap program to the area which passes the test to continue running when the area which passes the test is included in the test result; and when the physical memory is completely damaged, stopping running and suspending the CPU.
According to yet another aspect herein, there is provided an electronic device comprising a memory, a processor, and at least one application stored in the memory and configured to be executed by the processor, the application configured to perform the physical memory detection method described above.
According to yet another aspect herein, there is provided a readable storage medium having stored thereon a computer program which, when executed by a processor, implements the physical memory detection method described above.
The embodiment of the invention provides a physical memory detection method, a physical memory detection device, a physical memory detection equipment and a readable storage medium, wherein the method comprises the following steps: copying the memory test program from the bootstrap program to a second-level cache; running the memory test program, and outputting a physical memory test result, wherein the memory test result is a test passing area or a test failing area; when the test result comprises a test passing area, copying the bootstrap program to the test passing area to continue running; when the physical memory is completely damaged, stopping running and suspending the CPU; the memory test program is copied to the second-level cache to test the integrity of the physical memory, so that the position of the fault memory particle can be accurately positioned.
Drawings
Fig. 1 is a flowchart of a physical memory detection method according to an embodiment of the present invention;
fig. 2 is a flowchart of another physical memory detection method according to an embodiment of the present invention;
fig. 3 is a flowchart of another physical memory detection method according to an embodiment of the present invention;
fig. 4 is a flowchart of another physical memory detection method according to an embodiment of the present invention;
fig. 5 is a flowchart of another physical memory detection method according to an embodiment of the present invention;
fig. 6 is a flowchart of another physical memory detection method according to an embodiment of the present invention;
fig. 7 is a flowchart of another physical memory detection method according to an embodiment of the present invention;
fig. 8 is a block diagram illustrating an exemplary structure of a physical memory detection apparatus according to a second embodiment of the present invention.
The objects, features, and advantages described herein will be further explained with reference to the accompanying drawings.
Detailed Description
In order to make the technical problems, technical solutions and advantages to be solved by the present invention clearer and more obvious, the present invention is further described in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not restrictive.
Example one
As shown in fig. 1, in this embodiment, a method for detecting a physical memory includes:
s10, copying the memory test program from the bootstrap program to a secondary cache;
s20, operating the memory test program, and outputting a physical memory test result, wherein the memory test result is a test passing area or a test failing area;
s30, when the test result includes the area passing the test, copying the bootstrap program to the area passing the test to continue running;
and S40, when the physical memory is damaged completely, terminating the operation and suspending the CPU.
In this embodiment, the memory test program is copied to the second-level cache to perform integrity test on the physical memory, so that the location of the faulty memory particle can be accurately located.
In this embodiment, the method is used for testing the availability of the memory granules and the circuit of the main memory of the CPU/SoC small system. The dependence of a test program on the physical memory can be separated, the test on the main physical memory can be carried out only by utilizing the self cache in the CPU/SoC chip, and the damaged position of the memory is positioned for accurate maintenance.
In this embodiment, the memory test program is used to perform integrity test on physical memory particles, data, and address buses, and after the test of the main physical memory is completed, the other part of the boot program is loaded into the main memory segment that passes the test, so as to continue to initialize and test the other part of the device. Therefore, the early initialization and memory detection program of the equipment does not depend on the quality of the main memory particles, and the fault position of the memory can be tested; in addition, the back part of the bootstrap program can be operated in the memory segment passing the test, so as to initialize and test other peripheral equipment, thereby being convenient for finding other faults.
In this embodiment, the second-level cache is an internal memory of the CPU/SOC, the first-level cache of the CPU/SOC is divided into icache and dcache, and the capacity is small, and many CPUs/SOCs do not have third-level caches. The second-level cache capacity is at MB level, and can be generally configured into SRAM mode, which can meet the storage and operation requirements of a small number of program segments.
In this embodiment, a part of the firmware or the boot program is copied to the second level cache of the CPU/SoC, and the memory test program is added to the boot program, and the memory test program is run to perform a complete test on the physical memory, thereby locating a fault location in the main memory. The test results were divided into 3 cases:
1. the whole physical memory has no problem, the output test is passed, the latter half part of the bootstrap program is loaded to the memory, and the operation is continued and the bootstrap is completed;
2. outputting a problem area when a certain segment of physical memory has a problem, and operating other parts of the bootstrap program on the memory area passing the test; under the condition, the hardware can not only locate the particle with the problem through the output problem area, so that the accurate maintenance is convenient, but also load the following bootstrap program, initialize and test other peripherals and identify whether the other peripherals have the problem;
3. if the whole physical memory is unavailable, outputting a test result and terminating operation; in this case, it can be seen that the entire memory has a problem.
As shown in fig. 2, in this embodiment, after step S20, the method further includes:
and S21, when the test result includes the area which does not pass the test, outputting the position of the area which does not pass the test.
In the present embodiment, the case 1 and the case 2 in the background art do not occur. Even if the memory has faults, the faults of no output, system hang-up and the like in the background situation can not occur, positioning analysis by developers is not needed, and manpower and material resources are saved. And even if the memory part area has a fault, the subsequent part of the bootstrap program can still be operated, so that the fault position of the memory can be determined, and whether other peripheral equipment has problems can also be tested.
As shown in fig. 3, in this embodiment, before the step S10, the method further includes:
s01, initializing the CPU and the memory management unit MMU, and configuring the secondary cache as a Static Random Access Memory (SRAM); and enabling the memory management unit and the first-level cache.
And preparing for accessing the second-level cache and running a bootstrap program.
As shown in fig. 4, in the present embodiment, before the step S10 and after the step S01, the method further includes:
and S02, copying the CPU initialization configuration from the boot program to the secondary cache.
In this embodiment, the CPU initialization configuration and the memory test program are small and can be placed in the second level cache.
As shown in fig. 5, in the present embodiment, before the step S20 and after the step S10, the method further includes:
s11, initializing the CPU memory controller and the UART interface.
As shown in fig. 6, in this embodiment, before the step S01, the method further includes:
and S001, when the boot program is stored in the firmware, jumping to the firmware code to obtain the boot program.
In this embodiment, the boot program of the communication device is stored in the firmware, and after the communication device is powered on, the device is powered on and reset, and jumps to the firmware code to obtain the boot program.
As another embodiment, as shown in fig. 7, before the step S01, the method further includes:
and S002, when the bootstrap program is stored in the NandFlash/Eeprom, acquiring the bootstrap program from the NandFlash/Eeprom according to the hardware configuration.
In the embodiment, the method is suitable for a communication device without firmware or a firmware program independent of a memory, the bootstrap program of the communication device is stored in a non-NorFlash ROM such as NandFlash/Eeprom, and after the communication device is powered on, the device is powered on and reset, and the bootstrap program is obtained from the NandFlash/Eeprom according to hardware configuration.
In this embodiment, the Nand-flash memory is one of flash memories, and a nonlinear macro-cell mode is adopted in the Nand-flash memory, so that a cheap and effective solution is provided for realizing a solid-state high-capacity memory. The Nand-flash memory has the advantages of large capacity, high rewriting speed and the like, is suitable for storing a large amount of data, and is widely applied in the industry, for example, embedded products comprise a digital camera, an MP3 walkman memory card, a small-sized U-disk and the like.
Example two
As shown in fig. 8, in this embodiment, a physical memory detection apparatus includes:
the cache module 10 is configured to copy the memory test program from the boot program to the second level cache;
the test module 20 is configured to run the memory test program and output a physical memory test result, where the memory test result is a test-passing area or a test-failing area;
the running module 30 is configured to copy the boot program to the test-passed area to continue running when the test result includes the test-passed area; and when the physical memory is completely damaged, stopping running and suspending the CPU.
In this embodiment, the memory test program is copied to the second-level cache to perform integrity test on the physical memory, so that the location of the faulty memory particle can be accurately located.
In this embodiment, the apparatus is used to test the availability of memory granules and circuits of the main memory of the CPU/SoC small system. The dependence of a test program on the physical memory can be separated, the test on the main physical memory can be carried out only by utilizing the self cache in the CPU/SoC chip, and the damaged position of the memory is positioned for accurate maintenance.
In this embodiment, the memory test program is used to perform integrity test on physical memory particles, data, and address buses, and after the test of the main physical memory is completed, the other part of the boot program is loaded into the main memory segment that passes the test, so as to continue to initialize and test the other part of the device. Therefore, the early initialization and memory detection program of the equipment does not depend on the quality of the main memory particles, and the fault position of the memory can be tested; in addition, the back part of the bootstrap program can be operated in the memory segment passing the test, so as to initialize and test other peripheral equipment, thereby being convenient for finding other faults.
In this embodiment, the second-level cache is an internal memory of the CPU/SOC, the first-level cache of the CPU/SOC is divided into icache and dcache, and the capacity is small, and many CPUs/SOCs do not have third-level caches. The second-level cache capacity is at MB level, and can be generally configured into SRAM mode, which can meet the storage and operation requirements of a small number of program segments.
In this embodiment, a part of the firmware or the boot program is copied to the second level cache of the CPU/SoC, and the memory test program is added to the boot program, and the memory test program is run to perform a complete test on the physical memory, thereby locating a fault location in the main memory. The test results were divided into 3 cases:
1. the whole physical memory has no problem, the output test is passed, the latter half part of the bootstrap program is loaded to the memory, and the operation is continued and the bootstrap is completed;
2. outputting a problem area when a certain segment of physical memory has a problem, and operating other parts of the bootstrap program on the memory area passing the test; under the condition, the hardware can not only locate the particle with the problem through the output problem area, so that the accurate maintenance is convenient, but also load the following bootstrap program, initialize and test other peripherals and identify whether the other peripherals have the problem;
3. if the whole physical memory is unavailable, outputting a test result and terminating operation; in this case, it can be seen that the entire memory has a problem.
EXAMPLE III
In this embodiment, an electronic device includes a storage, a processor, and at least one application program stored in the storage and configured to be executed by the processor, where the application program is configured to perform the physical memory detection method according to the first embodiment.
Example four
An embodiment of the present invention provides a readable storage medium, on which a computer program is stored, which when executed by a processor, implements any of the method embodiments described in the above physical memory detection method embodiments.
It should be noted that the above device, apparatus, and readable storage medium embodiments and method embodiments belong to the same concept, and specific implementation processes thereof are described in detail in the method embodiments, and technical features in the method embodiments are correspondingly applicable in the device embodiments, which are not described herein again.
The embodiment of the invention provides a physical memory detection method, a physical memory detection device, a physical memory detection equipment and a readable storage medium, wherein the method comprises the following steps: obtaining the numerical characteristics of the text pairs according to the text pair data set; constructing a sample feature matrix through the numerical features of the text pairs; performing model training according to the sample characteristic matrix and the prediction vector to obtain a prediction model; obtaining a target text pair, and obtaining a similarity score of the target text pair according to the sample feature matrix and the prediction model; the text similarity is judged by acquiring a plurality of numerical characteristics of the text pair and considering the semantics and the syntactic structure, and the method has the advantages of trainable weight, less manual intervention, simplicity, rapidness, easiness in implementation, high accuracy and the like, and improves the user experience.
It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof.
In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.
The preferred embodiments of the present invention have been described above with reference to the accompanying drawings, and are not to be construed as limiting the scope of the invention. Any modifications, equivalents and improvements which may occur to those skilled in the art without departing from the scope and spirit of the present invention are intended to be within the scope of the claims.
Claims (10)
1. A physical memory detection method comprises the following steps:
copying the memory test program from the bootstrap program to a second-level cache;
running the memory test program, and outputting a physical memory test result, wherein the memory test result is a test passing area or a test failing area;
when the test result comprises a test passing area, copying the bootstrap program to the test passing area to continue running;
and when the physical memory is completely damaged, stopping running and suspending the CPU.
2. The method according to claim 1, wherein the running the memory test program and outputting the physical memory test result further comprises:
and when the test result comprises the area which does not pass the test, outputting the position of the area which does not pass the test.
3. The method as claimed in claim 1, wherein before copying the memory test program from the boot program to the secondary cache, the method further comprises:
initializing a CPU and a memory management unit MMU, and configuring a secondary cache as a static random access memory SRAM; and enabling the memory management unit and the first-level cache.
4. The method as claimed in claim 3, wherein before copying the memory test program from the boot program to the secondary cache, the method further comprises:
the CPU initialization configuration is copied from the boot program to the secondary cache.
5. The method according to claim 4, wherein before the running the memory test program and outputting the physical memory test result, the method further comprises:
and initializing a CPU memory controller and a universal asynchronous receiver-transmitter interface UART.
6. A physical memory detection method according to claim 3, wherein said initialization CPU and memory management unit MMU configures the second level cache as static random access memory SRAM; before enabling the memory management unit and the first-level cache, the method further comprises:
when the boot program is stored in the firmware, jumping to the firmware code to obtain the boot program.
7. A physical memory detection method according to claim 3, wherein said initialization CPU and memory management unit MMU configures the second level cache as static random access memory SRAM; before enabling the memory management unit and the first-level cache, the method further comprises:
and when the bootstrap program is stored in the NandFlash/Eeprom, the bootstrap program is obtained from the NandFlash/Eeprom according to the hardware configuration.
8. A physical memory sensing apparatus, comprising:
the cache module is used for copying the memory test program from the bootstrap program to the second-level cache;
the test module is used for operating the memory test program and outputting a physical memory test result, wherein the memory test result is a test passing area or a test failing area;
the running module is used for copying the bootstrap program to the area which passes the test to continue running when the area which passes the test is included in the test result; and when the physical memory is completely damaged, stopping running and suspending the CPU.
9. An electronic device comprising a memory, a processor, and at least one application stored in the memory and configured to be executed by the processor, wherein the application is configured to perform the physical memory detection method of any one of claims 1-7.
10. A readable storage medium, having stored thereon a computer program which, when executed by a processor, implements the physical memory sensing method of any one of claims 1-7.
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| CN201811419036.8A CN111221685A (en) | 2018-11-26 | 2018-11-26 | Physical memory detection method, device, equipment and readable storage medium |
| PCT/CN2019/121049 WO2020108494A1 (en) | 2018-11-26 | 2019-11-26 | Physical memory detection method and apparatus, device, and readable storage medium |
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