CN111208893B

CN111208893B - CPU reset control method, system and storage medium

Info

Publication number: CN111208893B
Application number: CN202010031207.0A
Authority: CN
Inventors: 梁栋; 吴闽华; 孟庆晓; 秦金昆; 刘文清
Original assignee: Shenzhen Genew Technologies Co Ltd
Current assignee: Shenzhen Genew Technologies Co Ltd
Priority date: 2020-01-13
Filing date: 2020-01-13
Publication date: 2021-07-06
Anticipated expiration: 2040-01-13
Also published as: CN111208893A

Abstract

The invention discloses a control method, a system and a storage medium for CPU reset, wherein before a monitoring chip or a CPLD logically resets a CPU, the CPLD sends an external interrupt signal to the CPU; the CPU responds to the external interrupt signal and shuts down all modules of the CPU which need to access the DDR2, the DDR2 controller and a clock signal sent to the DDR2 in an interrupt service program; the CPU executes the write CPLD register according to a part of instructions latched in the instruction cache, and confirms the reset; and if the CPLD is used for resetting, the hardware reset pin of the CPU is pulled down after time delay, and the CPU is really reset. In the invention, before resetting the CPU, the CPU already closes all accesses to the DDR2 memory, and after the CPLD delays for 1 second and the DDR2 is not accessed internally, the CPU is reset.

Description

CPU reset control method, system and storage medium

Technical Field

The invention relates to the technical field of computer embedded driving, in particular to a control method and a control system for CPU reset and a storage medium.

Background

The embedded environment, like a normal desktop system, also often restarts the entire system. Windows and linux desktop systems are generally manual click or command reset systems, and various resources, such as saved files, can be closed during reset, so that file damage and even disk damage can be prevented. When the embedded system needs to be reset, a monitoring chip (a watchdog is called as a watchdog in nature, the watchdog generally has an input and an output, the input is called as a feed dog, the output is generally connected to a reset end of the other part and is generally connected to a single chip microcomputer, the watchdog is used for regularly checking the internal condition of the chip, and once an error occurs, a reset signal is sent to the chip, and the watchdog orders to have the highest priority in the interruption of a program) to pull down a hardware reset signal of a CPU (Central processing Unit), so that the system is forcibly reset. Of course, there is also an action to close the saved file before resetting the system, but this is typically an active reset. These operations may not be implemented at all if reset by the watchdog.

Meanwhile, an early DDR2(DDR Double Data Rate, DDR SDRAM Double Data Rate, which is a Double Data Rate synchronous dynamic random access memory, is a commonly known DDR and is an operating memory at ordinary times, and DDR2 is a second-generation DDR) memory does not have a hardware reset function, and if forced reset may cause an error in the internal state of a DDR2 chip, the memory is read and written inconsistently, a CPU cannot execute an instruction correctly, and an embedded system cannot be started any more unless power is off and restarted. In general hardware design, independent powering on and powering off of the DDR2 is not good, once an embedded system cannot be restarted normally, equipment paralysis can be caused in an unattended environment, and the consequences are serious unless manual intervention is performed.

Accordingly, the prior art is yet to be improved and developed.

Disclosure of Invention

The present invention is directed to a method, a system and a storage medium for controlling CPU reset, which are used to solve the above-mentioned drawbacks of the prior art.

In order to achieve the above object, the present invention provides a CPU reset control method, wherein the CPU reset control method includes:

before the monitoring chip or the CPLD logically resets the CPU, the CPLD sends an external interrupt signal to the CPU;

the CPU responds to the external interrupt signal and shuts down all modules of the CPU which need to access the DDR2, the DDR2 controller and a clock signal sent to the DDR2 in an interrupt service program;

the CPU executes the write CPLD register according to a part of instructions latched in the instruction cache, and confirms the reset;

and if the CPLD is used for resetting, the hardware reset pin of the CPU is pulled down after time delay, and the CPU is really reset.

Optionally, the CPU reset control method, wherein sending an external interrupt signal to the CPU by the CPLD specifically includes:

the CPLD sends a/IRQ 0 to the CPU, and the/IRQ 0 is an external interrupt signal.

Optionally, the method for controlling CPU reset, wherein the preferential response of the CPU to the external interrupt signal specifically includes:

the CPLD outputs a low level to the CPU, and the CPU triggers an interrupt and enters a preset interrupt reset program.

Optionally, in the method for controlling CPU reset, the interrupt service program is a program executed after the CPU is triggered to be interrupted.

Optionally, in the method for controlling CPU reset, the CPLD directly resets the CPU through the/HD-RST signal, and the/HD-RST signal is active low.

Optionally, the CPU reset control method further includes:

before resetting the CPU by the CPLD, the CPU closes all accesses to the DDR2 memory, and after the CPLD delays for 1 second and the DDR2 is not accessed internally, the CPU is reset.

Optionally, the CPU reset control method further includes:

when the interrupt service program starts, closing the network port hardware and unloading the drive;

closing the DMA channel, and prohibiting DMA from accessing the DDR 2;

shutting down the coprocessor of the CPU, and prohibiting the coprocessor from accessing the DDR 2;

closing a memory controller of the CPU, and closing a memory refreshing clock;

writing the CPLD register, and immediately resetting the CPU;

and (4) waiting for software endless loop, resetting the CPU after the CPLD waits for 1 second, and restarting the CPU.

Optionally, in the method for controlling CPU reset, the network port directly accesses the memory through the DMA controller.

In addition, in order to achieve the above object, the present invention further provides a CPU reset control system, wherein the CPU reset control system includes: a CPU and a CPLD; before the monitoring chip or the CPLD logically resets the CPU, the CPLD sends an external interrupt signal to the CPU; the CPU responds to the external interrupt signal preferentially, and in an interrupt service program, all modules of the CPU which need to access the DDR2, the DDR2 controller and a clock signal sent to the DDR2 are closed; the CPU executes the write CPLD register according to a part of instructions latched in the instruction cache, and confirms the reset; and if the CPLD is used for resetting, the hardware reset pin of the CPU is pulled down after time delay, and the CPU is really reset.

In addition, in order to achieve the above object, the present invention further provides a storage medium, wherein the storage medium stores a CPU reset control program, and the CPU reset control program realizes the steps of the CPU reset control method described above when being executed by a processor.

In the invention, before the monitoring chip or CPLD logically resets the CPU, the CPLD sends an external interrupt signal to the CPU; the CPU responds to the external interrupt signal and shuts down all modules of the CPU which need to access the DDR2, the DDR2 controller and a clock signal sent to the DDR2 in an interrupt service program; the CPU executes the write CPLD register according to a part of instructions latched in the instruction cache, and confirms the reset; and if the CPLD is used for resetting, the hardware reset pin of the CPU is pulled down after time delay, and the CPU is really reset. In the invention, before resetting the CPU, the CPU already closes all accesses to the DDR2 memory, after the CPLD delays for 1 second and the DDR2 is not accessed internally, the CPU is reset, after the CPU is restarted, the DDR2 controller is reconfigured, and the DDR2 memory can also work normally.

Drawings

FIG. 1 is a flow chart of a preferred embodiment of a control method for CPU reset according to the present invention;

FIG. 2 is a schematic diagram of the CPU and CPLD interactive communication in the preferred embodiment of the control method and system for CPU reset of the present invention;

FIG. 3 is a flowchart of the CPU starting the interrupt service routine in the preferred embodiment of the control method for CPU reset of the present invention;

FIG. 4 is a flowchart of the CPU reset control method according to the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer and clearer, the present invention is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

As shown in fig. 1, the method for controlling CPU reset according to the preferred embodiment of the present invention includes:

step S10, before the monitoring chip or CPLD logically resets the CPU, the CPLD sends an external interrupt signal to the CPU;

step S20, the CPU responds to the external interrupt signal, and in the interrupt service program, all modules of the CPU which need to access the DDR2, the DDR2 controller and a clock signal sent to the DDR2 are closed;

step S30, the CPU executes the write CPLD register according to the partial instruction latched in the instruction cache, and confirms the reset;

and step S40, pulling down the hardware reset pin of the CPU by the CPLD, and really resetting the CPU, if the monitoring chip is reset, pulling down the hardware reset pin of the CPU after time delay, and really resetting the CPU.

Specifically, the embedded system is actively reset, and the software can perform file protection. For the hardware watchdog or CPLD logic, the CPU reset signal is directly pulled down, and the CPU is reset, so that the software cannot be perceived at all. Due to the defect that DDR2 cannot be reset hard (DDR3/DDR4 can both be reset hard), the particles of the defective DDR2 may appear in peripheral circuits such as a CPU and the like and are reset completely, but the inside of the peripheral circuits is disordered. At this time, the CPU reads and writes its unit contents inconsistently, resulting in the CPU not being able to execute instructions correctly. Even if the CPU is restarted repeatedly, the fatal problem cannot be solved unless the entire environment is powered off first and the DDR2 internal capacitor is discharged completely, and then the CPU is powered on again, and the CPU can correctly read and write the unit of DDR2 and start normally.

In the invention, before the watchdog or CPLD logic resets the CPU, the CPLD first gives an external interrupt signal to the CPU (the CPLD has a signal connected to an external interrupt pin of the CPU, and the CPLD pulls down the signal line to send interrupt to the CPU). The CPU responds the interrupt preferentially, various modules (including network ports, DMA and coprocessors) of the CPU, which need to access the DDR2, are closed in an interrupt reset program, then the DDR2 controller is closed, a clock signal sent to the DDR2 is closed, and at the moment, the CPU depends on a small part of instructions locked in an instruction cache of the CPU: continuing to write the CPLD register, the validation can be reset. At this time, the CPLD immediately pulls down the hardware reset pin of the CPU, and the CPU is actually reset. If the watchdog is reset, the hardware pipe of the CPU is pulled down after the watchdog is directly delayed for 1.8 seconds, and the CPU is really reset.

As shown in FIG. 2, CPLD directly and hard resets CPU through/HD-RST signal, the signal is active low; before resetting, an interrupt is sent to the CPU. the/IRQ 0 is an external interrupt signal of the CPU, the CPLD outputs low level to the CPU, the CPU can trigger the interrupt and enter a preset interrupt reset program to execute the operation flow described above.

Further, as shown in fig. 3, the interrupt service routine is a routine executed after the CPU is triggered to interrupt, and the priority of the routine is the highest, and all current events must be interrupted to execute the service routine.

The CPU has a batch of interrupt types and interrupt sources; INT0 is an external interrupt source. The low level is active, i.e. when the level of INT0 is low, the CPU is triggered to interrupt to execute the service routine.

Different operating systems provide an interrupt registration function, which allows the CPU to know how to operate when an interrupt occurs. If the interrupt service routine is not registered, the interrupt does nothing in detail.

Further, as shown in fig. 4, after the interrupt service routine is started, the network port hardware is closed, and the driver is unloaded; closing the DMA channel, and prohibiting DMA from accessing the DDR 2; shutting down the coprocessor of the CPU, and prohibiting the coprocessor from accessing the DDR 2; closing a memory controller of the CPU, and closing a memory refreshing clock; writing the CPLD register, and immediately resetting the CPU; and (4) waiting for software endless loop, resetting the CPU after the CPLD waits for 1 second, and restarting the CPU.

The network port can directly access the DDR memory, and the access mode is a DMA channel. The network port equipment can directly access the memory through the DMA controller; this access is transparent to the CPU or software, so the portal must be closed to prevent it from accessing memory through the DMA channel.

Many CPUs are not single general-purpose chips and many have coprocessors for processing specific services. The POWERPC chip provided by the invention is provided with a coprocessor to process network messages and narrow-band data. Like the first portal, the coprocessor also accesses memory. The main CPU is also unaware of the memory access, so the coprocessor is first turned off to terminate its memory access.

The memory controller is a hardware interface for the CPU to access the memory. DDR has very complicated time sequence, and the controller realizes the protocols, so that the CPU can read and write the memory transparently. After the DDR controller is closed, any hardware module cannot access the memory. The memory chip enters a free state and is not affected by the outside.

And finally, the CPLD is enabled to reset the CPU. After software writes a register of the CPLD, the CPLD pulls down a CPU/RESET signal after 1 second, and the CPU is restarted.

In the invention, before the CPLD resets the CPU, the CPU already closes all accesses to the DDR2 memory, and after the CPLD delays for 1 second and the DDR2 is not accessed internally, the CPU is reset; after the CPU is restarted, the DDR2 controller is reconfigured, and the DDR2 memory can work normally.

Further, based on the above CPU reset control method, the present invention further provides a CPU reset control system, as shown in fig. 2, the CPU reset control system includes: a CPU and a CPLD; before the monitoring chip or the CPLD logically resets the CPU, the CPLD sends an external interrupt signal to the CPU; the CPU responds to the external interrupt signal preferentially, and in an interrupt service program, all modules of the CPU which need to access the DDR2, the DDR2 controller and a clock signal sent to the DDR2 are closed; the CPU executes the write CPLD register according to a part of instructions latched in the instruction cache, and confirms the reset; and if the CPLD is used for resetting, the hardware reset pin of the CPU is pulled down after time delay, and the CPU is really reset.

The present invention also provides a storage medium, wherein the storage medium stores a CPU reset control program, and the CPU reset control program implements the steps of the CPU reset control method described above when executed by a processor.

In summary, the present invention provides a method, a system and a storage medium for controlling CPU reset, wherein the method includes: before the monitoring chip or the CPLD logically resets the CPU, the CPLD sends an external interrupt signal to the CPU; the CPU responds to the external interrupt signal and shuts down all modules of the CPU which need to access the DDR2, the DDR2 controller and a clock signal sent to the DDR2 in an interrupt service program; the CPU executes the write CPLD register according to a part of instructions latched in the instruction cache, and confirms the reset; and if the CPLD is used for resetting, the hardware reset pin of the CPU is pulled down after time delay, and the CPU is really reset. In the invention, before resetting the CPU, the CPU already closes all accesses to the DDR2 memory, after the CPLD delays for 1 second and the DDR2 is not accessed internally, the CPU is reset, after the CPU is restarted, the DDR2 controller is reconfigured, and the DDR2 memory can also work normally.

Of course, it will be understood by those skilled in the art that all or part of the processes of the methods of the above embodiments may be implemented by a computer program, which may be stored in a computer readable storage medium, and may include the processes of the above method embodiments when executed. The storage medium may be a memory, a magnetic disk, an optical disk, etc.

It is to be understood that the invention is not limited to the examples described above, but that modifications and variations may be effected thereto by those of ordinary skill in the art in light of the foregoing description, and that all such modifications and variations are intended to be within the scope of the invention as defined by the appended claims.

Claims

1. A control method for CPU reset is characterized in that the control method for CPU reset comprises the following steps:

the interrupt service program is a program executed after the CPU is triggered and interrupted, the priority of the program is highest, all current things are interrupted, and the service program is executed;

pulling down the hardware reset pin of the CPU by the CPLD, and really resetting the CPU, if the monitoring chip is reset, pulling down the hardware reset pin of the CPU after time delay, and really resetting the CPU;

before the CPLD resets the CPU, the CPU closes all accesses to the DDR2 memory, after the CPLD delays for 1 second and the DDR2 is not accessed internally, the CPU is reset, after the CPU is restarted, the DDR2 controller is reconfigured, and the DDR2 memory works normally;

when the interrupt service program starts, closing the network port hardware and unloading the drive; closing the DMA channel, and prohibiting DMA from accessing the DDR 2; shutting down the coprocessor of the CPU, and prohibiting the coprocessor from accessing the DDR 2; closing a memory controller of the CPU, and closing a memory refreshing clock; writing the CPLD register, and immediately resetting the CPU; software endless loop waiting, the CPLD resets the CPU after waiting for 1 second, and the CPU is restarted;

before a watchdog or CPLD logic resets a CPU, the CPLD gives an external interrupt signal to the CPU; the CPU responds to the interrupt preferentially, various modules of the CPU which need to access the DDR2 are closed in an interrupt reset program, then the DDR2 controller is closed, a clock signal sent to the DDR2 is closed, and at the moment, the CPU depends on a small part of instructions locked in an instruction cache of the CPU: continuously executing the writing of the CPLD register, and confirming that the CPLD register can be reset; at the moment, the CPLD immediately pulls down a hardware reset pin of the CPU, and the CPU is really reset; if the watchdog is reset, the hardware pipe of the CPU is pulled down after the watchdog is directly delayed for 1.8 seconds, and the CPU is really reset.

2. The CPU reset control method according to claim 1, wherein the sending, by the CPLD, an external interrupt signal to the CPU is specifically:

3. The CPU reset control method according to claim 1, wherein the preferential response of the CPU to the external interrupt signal is specifically:

4. The CPU reset control method according to claim 1, wherein the CPLD directly resets the CPU by a/HD-RST signal, and the/HD-RST signal is active low.

5. The CPU reset control method according to claim 1, further comprising:

6. The method according to claim 1, wherein the portal directly accesses the memory through the DMA controller.

7. A control system for CPU reset, the control system for CPU reset comprising: a CPU and a CPLD;

before the monitoring chip or the CPLD logically resets the CPU, the CPLD sends an external interrupt signal to the CPU; the CPU responds to the external interrupt signal preferentially, and in an interrupt service program, all modules of the CPU which need to access the DDR2, the DDR2 controller and a clock signal sent to the DDR2 are closed; the interrupt service program is a program executed after the CPU is triggered and interrupted, the priority of the program is highest, all current things are interrupted, and the service program is executed; the CPU executes the write CPLD register according to a part of instructions latched in the instruction cache, and confirms the reset; pulling down the hardware reset pin of the CPU by the CPLD, and really resetting the CPU, if the monitoring chip is reset, pulling down the hardware reset pin of the CPU after time delay, and really resetting the CPU; before the CPLD resets the CPU, the CPU closes all accesses to the DDR2 memory, after the CPLD delays for 1 second and the DDR2 is not accessed internally, the CPU is reset, after the CPU is restarted, the DDR2 controller is reconfigured, and the DDR2 memory works normally; when the interrupt service program starts, closing the network port hardware and unloading the drive; closing the DMA channel, and prohibiting DMA from accessing the DDR 2; shutting down the coprocessor of the CPU, and prohibiting the coprocessor from accessing the DDR 2; closing a memory controller of the CPU, and closing a memory refreshing clock; writing the CPLD register, and immediately resetting the CPU; software endless loop waiting, the CPLD resets the CPU after waiting for 1 second, and the CPU is restarted; before a watchdog or CPLD logic resets a CPU, the CPLD gives an external interrupt signal to the CPU; the CPU responds to the interrupt preferentially, various modules of the CPU which need to access the DDR2 are closed in an interrupt reset program, then the DDR2 controller is closed, a clock signal sent to the DDR2 is closed, and at the moment, the CPU depends on a small part of instructions locked in an instruction cache of the CPU: continuously executing the writing of the CPLD register, and confirming that the CPLD register can be reset; at the moment, the CPLD immediately pulls down a hardware reset pin of the CPU, and the CPU is really reset; if the watchdog is reset, the hardware pipe of the CPU is pulled down after the watchdog is directly delayed for 1.8 seconds, and the CPU is really reset.

8. A storage medium storing a control program for CPU reset, which when executed by a processor implements the steps of the control method for CPU reset according to any one of claims 1 to 6.