CN111198829B - FIFO master interface, FPGA with same and application - Google Patents

FIFO master interface, FPGA with same and application Download PDF

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CN111198829B
CN111198829B CN201911394654.6A CN201911394654A CN111198829B CN 111198829 B CN111198829 B CN 111198829B CN 201911394654 A CN201911394654 A CN 201911394654A CN 111198829 B CN111198829 B CN 111198829B
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interface
data
command
signal
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CN111198829A (en
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张洪柳
付云燕
于秀龙
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Qingdao Fangcun Microelectronic Technology Co ltd
Shandong Fangcun Microelectronics Technology Co ltd
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Qingdao Fangcun Microelectronic Technology Co ltd
Shandong Fangcun Microelectronics Technology Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package

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Abstract

The invention provides an FIFO master interface, an FPGA with the FIFO master interface and application. The FIFO master interface comprises a finite state machine, a state path, a write FIFO module and a read FIFO module; a status path for pulling a FIFO slave interface status signal downstream of the interface to the interface upstream; the write FIFO module is used for receiving write commands/data when a write command/data FIFO full signal in the upstream end of the interface indicates that the interface is in a non-full state, and generating corresponding control signals by the finite state machine to write commands/data to the command FIFO/data FIFO of the FIFO slave interface when the finite state machine judges that the command FIFO/data FIFO in the downstream of the interface is in the non-full state; and the read FIFO module is used for generating a corresponding control signal by the finite state machine to read the command/data from the slave FIFO slave interface and pressing the command/data into the read FIFO module when the empty signal of the read command/data FIFO in the upstream end of the interface indicates a non-empty state and the finite state machine judges that the empty signal of the read command/data FIFO in the downstream of the interface is non-empty.

Description

FIFO master interface, FPGA with same and application
Technical Field
The invention belongs to the technical field of communication interfaces, and particularly relates to an FIFO master interface, an FPGA with the FIFO master interface and application of the FPGA.
Background
The statements in this section merely provide background information related to the present disclosure and may not necessarily constitute prior art.
The inventor finds that the conventional FIFO master is basically SoC (system-on-chip), generally only for one slave FIFO, the FIFO master is relatively inflexible for products that support FIFO but not FIFO master mode, the development period is long, the time consumption is high, and the internal signal of the interface IP (Intellectual Property) is not transparent.
Disclosure of Invention
In order to solve the above problems, a first aspect of the present invention provides an FIFO master interface, which can implement conversion from a common FIFO interface to an FIFO master interface, so that a user can directly call the FIFO master interface as required, flexible docking of an upper layer and a lower layer is implemented, and reuse of an FPGA connected to the FIFO master interface is achieved.
In order to achieve the purpose, the invention adopts the following technical scheme:
a FIFO master interface comprising: the device comprises a finite state machine, a state path, a write FIFO module and a read FIFO module;
a status path for pulling a FIFO slave interface status signal downstream of the interface to the interface upstream;
the write FIFO module is used for receiving write commands/data when a write command/data FIFO full signal in the upstream end of the interface indicates that the interface is in a non-full state, and generating corresponding control signals by the finite state machine to write commands/data to the command FIFO/data FIFO of the FIFO slave interface when the finite state machine judges that the command FIFO/data FIFO in the downstream of the interface is in the non-full state;
and the read FIFO module is used for generating a corresponding control signal by the finite state machine to read the command/data from the slave FIFO slave interface and pressing the command/data into the read FIFO module when the empty signal of the read command/data FIFO in the upstream end of the interface indicates a non-empty state and the finite state machine judges that the empty signal of the read command/data FIFO in the downstream of the interface is non-empty.
As an embodiment, the FIFO slave interface status signal downstream of the interface includes: a write command FIFO full signal, a read command FIFO empty signal, a write data FIFO full signal, and a read data FIFO empty signal.
As one embodiment, the status path pulls FIFO slave interface status signals downstream of the interface to the upstream end of the interface, including a full signal indicating a write command FIFO, an empty signal indicating a read command FIFO, a full signal indicating a write data FIFO, and an empty signal indicating a read data FIFO.
In one embodiment, the upstream end of the FIFO master interface is further configured to receive upstream control signals, where the upstream control signals include an input clock signal, a write enable signal, a read enable signal, and an end of packet input signal provided by an upstream device.
In one embodiment, the downstream end of the FIFO master interface is further configured to send downstream interface control signals that control the chip select signal, the read data/command enable signal, the write data/command enable signal, the data/command input/output, the command FIFO select signal, and the end of packet signal.
In one embodiment, the FIFO master interface is implemented by a field programmable gate array.
In order to solve the above problems, a second aspect of the present invention provides an application of a FIFO master interface for enabling intercommunication between an upstream device and a downstream device respectively connected to the FIFO master interface.
In order to achieve the purpose, the invention adopts the following technical scheme:
an FIFO master interface, its upstream end couples to upstream device, the downstream end couples to downstream device; the upstream device is provided with an FIFO interface, and the FIFO interface is used for calling the FIFO master interface; the downstream device conforms to a slave FIFO timing; the FIFO master interface is used for realizing the intercommunication between the upstream device and the downstream device.
As an embodiment, the process of the FIFO master interface for implementing intercommunication between the upstream device and the downstream device is:
the upstream device writes commands/data into a write FIFO module in an FIFO master interface through an FIFO interface, and a finite state machine in the FIFO master interface is used for judging the FIFO empty and full state of the downstream device so as to generate corresponding control signals and perform write command/data operation on the downstream device;
the upstream device carries out reading command/data operation according to the empty and full state of the FIFO of the downstream device, a finite state machine in the FIFO master interface generates corresponding control signals, reads back the command/data from the FIFO slave of the downstream device, and caches the command/data into a reading FIFO module in the FIFO master interface.
In one embodiment, when the empty signal of the read FIFO module is in a non-empty state, the upstream device reads the command/data in the read FIFO module through the FIFO interface.
In order to solve the above problems, a third aspect of the present invention provides an FPGA having an FIFO master interface, which can implement conversion from a common FIFO interface to the FIFO master interface, so that a user can directly call the FIFO master interface as required, thereby implementing flexible docking between an upper layer and a lower layer, and implementing reuse of the FPGA connected to the FIFO master interface.
In order to achieve the purpose, the invention adopts the following technical scheme:
an FPGA has a FIFO master interface.
The invention has the beneficial effects that:
(1) the invention can provide an interface which is used for providing an upstream corresponding FIFO interface and a downstream corresponding FIFO slave, can realize the conversion of interface time sequence in a field programmable gate array (such as FPGA), can support some designs which support FIFO but do not support FIFO master protocol, and realize FIFO master function through the interface.
(2) The FIFO depth used by the invention can be correspondingly adjusted according to the requirements of users, thereby ensuring the flexibility of the whole design and increasing the use experience of users.
(3) The invention can use the field programmable gate array to construct the whole realization, has low cost, is compatible with field programmable gate arrays of different models, only needs a user to correspondingly modify according to requirements, ensures the universality of the FIFO master interface and is easy to debug.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the invention and not to limit the invention.
FIG. 1 is a schematic diagram of a FIFO master interface according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of the read/write timing sequence of the FIFO interface according to the embodiment of the present invention;
FIG. 3 is a schematic diagram of the read/write timing sequence of the FIFO master interface according to the embodiment of the present invention;
fig. 4 is a schematic diagram of an application of the FIFO master interface according to the embodiment of the present invention.
Detailed Description
The invention is further described with reference to the following figures and examples.
It is to be understood that the following detailed description is exemplary and is intended to provide further explanation of the invention as claimed. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
Interpretation of terms:
FIFO: first input First output, First in First out queue;
FIFO master interface: a main interface of a first-in first-out queue;
FIFO slave interface: slave interfaces of the first-in first-out queues.
Example one
As shown in fig. 1, a FIFO master interface of the present embodiment includes: the device comprises a finite state machine, a state path, a write FIFO module and a read FIFO module.
In fig. 1, FSM: finish State Machine, Finite State Machine; the control center is composed of a state register and a combinational logic circuit, can perform state transition according to a preset state according to a control signal, coordinates the action of the related signal and completes a specific operation.
For example: the finite state machine can be realized by adopting a field programmable gate array FPGA.
In fig. 1, WFIFO, refers to: write FIFO, write FIFO module;
RFIFO refers to: read FIFO, read FIFO module;
as shown in fig. 1, the FIFO master interface of the present embodiment specifically includes:
a status path for pulling a FIFO slave interface status signal downstream of the interface to the interface upstream;
the write FIFO module is used for receiving write commands/data when a write command/data FIFO full signal in the upstream end of the interface indicates that the interface is in a non-full state, and generating corresponding control signals by the finite state machine to write commands/data to the command FIFO/data FIFO of the FIFO slave interface when the finite state machine judges that the command FIFO/data FIFO in the downstream of the interface is in the non-full state;
and the read FIFO module is used for generating a corresponding control signal by the finite state machine to read the command/data from the slave FIFO slave interface and pressing the command/data into the read FIFO module when the empty signal of the read command/data FIFO in the upstream end of the interface indicates a non-empty state and the finite state machine judges that the empty signal of the read command/data FIFO in the downstream of the interface is non-empty.
The signals connected by the FIFO master interface of the present embodiment include an upstream control signal, a status path signal, a FIFO interface signal and a downstream interface control signal.
As shown in fig. 1 in particular, the upstream control signals include:
1) clk _ in: input clk (clock, clock signal) to upstream device;
2) when cfifo _ full _ line/full _ line is pulled low, the wr _ en is pulled low (write enable);
3) rd _ en: when cfifo _ empty _ line/empty _ line is pulled low, rd _ en (read enable) is pulled low.
4) pkg _ end _ in, an end-of-packet signal indicating completion of transmission of a packet of data;
the status path signals include:
1) cfifo _ full _ line indicating a full signal of the write command FIFO;
2) cfifo _ empty _ line indicating an empty signal of the read command FIFO;
3) full _ line indicating a full signal of the write data FIFO;
4) empty _ line indicating the empty signal of the read data FIFO;
5) cfifo _ sel _ in the upstream command FIFO select signal.
The FIFO interface signal includes:
1) wd _ push: push signal of WFIFO;
2) pop (pop-up) signal of RFIFO;
3) WFIFO full signal;
4) wdata _ empty is the null signal of WFIFO;
5) rdata _ full is the full signal of RFIFO;
6) rdata _ empty is the null signal of RFIFO.
The downstream interface control signals include:
1) cs _ n is a chip select signal;
2) re _ n is a read data/command enable signal;
3) we _ n write data/command enable signal;
4) cfifo _ sel _ n, a downstream command FIFO select signal;
5) dq [31:0] data/command input/output;
6) a cfifo _ full write command FIFO full signal;
7) cfifo _ empty is a read command FIFO empty signal;
8) full, write data FIFO full signal;
9) empty signal of reading data FIFO;
10) pkgent _ n: and (4) packaging the end signal.
As shown in FIG. 2, the FIFO read/write timing diagram is described as follows:
1) on the rising edge of the clock, push and wdata are in the same clock period;
2) on the rising edge of the clock, the next clock cycle of pop outputs rdata;
3) setting FIFO full signal;
4) FIFO reads empty, empty signal is set.
As shown in FIG. 4, the FIFO master read/write timing diagram is described as follows:
CMD write, device select, write enable, command FIFO select, status feedback command FIFO not full, command write downstream device command FIFO.
DATA read, device SELECT, READ ENABLE, NONCIT FIFO SELECT, DATA FIFO NOT NULL, reads DATA from downstream device DATA FIFO.
DATA write, device selected, write enable, no command FIFO selected, downstream device DATA FIFO not full, DATA write downstream device DATA FIFO.
CMD read, device selection, read enable, command FIFO selection, status feedback command FIFO non-empty, read data from downstream device command FIFO.
Specifically, the whole data flow of the FIFO master interface of the present embodiment is:
(1) writing commands: when cfifo _ full _ line is in a non-full state, the upstream device writes a command to the WFIFO through the FIFO interface, and the control logic determines that cfifo _ full is not full and writes a command to the command FIFO of the FIFO slave.
(2) And (3) reading commands: when cfifo _ empty _ line is in a non-empty state, the control logic judges that cfifo _ empty is not empty, and reads a command from the FIFO slave and pushes RFIFO. When rdata _ empty is not empty, the upstream device reads the command through the FIFO interface.
(3) Writing data: when full _ line is in a non-full state, the upstream device writes data to WFIFO through the FIFO interface, and the control logic judges that full is not full, and then writes data to the data FIFO of FIFO slave.
(4) Reading data: when the empty _ line is in a non-empty state, the control logic judges that the empty is not empty, reads data from the FIFO slave and presses the RFIFO. When rdata _ empty is not empty, the upstream device reads the data through the FIFO interface.
The embodiment can provide an interface for providing an upstream corresponding FIFO interface and a downstream corresponding FIFO slave, can realize the conversion of interface time sequence in a field programmable gate array (such as an FPGA), can support some designs which support FIFO but do not support FIFO master protocol, and realize FIFO master function through the interface.
The FIFO depth used in the embodiment can be correspondingly adjusted according to the user requirements, so that the flexibility of the whole design is ensured, and the use experience of the user is increased.
The embodiment can use the field programmable gate array to construct the finite-state machine, has low cost, is compatible with field programmable gate arrays of different models, only needs a user to correspondingly modify according to requirements, ensures the universality of the FIFO master interface, and is easy to debug.
Example two
The embodiment provides application of a FIFO master interface.
As shown in fig. 4, the upstream end of the FIFO master interface of the present embodiment is connected to an upstream device, and the downstream end is connected to a downstream device; the upstream device is provided with an FIFO interface, and the FIFO interface is used for calling the FIFO master interface; the downstream device conforms to a slave FIFO timing; the FIFO master interface is used for realizing the intercommunication between the upstream device and the downstream device.
In a specific implementation, the process of the FIFO master interface for implementing the mutual communication between the upstream device and the downstream device is:
the upstream device writes commands/data into a write FIFO module in an FIFO master interface through an FIFO interface, and a finite state machine in the FIFO master interface is used for judging the FIFO empty and full state of the downstream device so as to generate corresponding control signals and perform write command/data operation on the downstream device;
the upstream device carries out reading command/data operation according to the empty and full state of the FIFO of the downstream device, a finite state machine in the FIFO master interface generates corresponding control signals, reads back the command/data from the FIFO slave of the downstream device, and caches the command/data into a reading FIFO module in the FIFO master interface.
When the empty signal of the read FIFO module is in a non-empty state, the upstream device reads the command/data in the read FIFO module through the FIFO interface.
EXAMPLE III
The embodiment is an FPGA, and the FIFO master interface specifically mentioned above can realize the conversion from the common FIFO interface to the FIFO master interface, so that a user can directly call the FIFO master interface according to the requirement, the flexible butt joint of the upper layer and the lower layer is realized, and the reutilization of the FPGA connected with the FIFO master interface is realized.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (9)

1. A FIFO master interface device, comprising: the device comprises a finite state machine, a state path, a write FIFO module and a read FIFO module;
a status path for pulling FIFO slave interface status signals downstream of the interface to the interface upstream, including a full signal indicating a write command FIFO, an empty signal indicating a read command FIFO, a full signal indicating a write data FIFO, and an empty signal indicating a read data FIFO;
the write FIFO module is used for receiving write commands or data when the write command or data FIFO full signal indicated in the upstream end of the interface is in a non-full state and the finite state machine judges that the command FIFO or data FIFO downstream of the interface is in a non-full state, and generating corresponding control signals by the finite state machine to write commands or data FIFO to the FIFO slave interface;
and the read FIFO module is used for generating a corresponding control signal by the finite state machine to read the command or the data from the slave FIFO slave interface and pressing the command or the data into the read FIFO module when the read command or the empty signal of the data FIFO is indicated to be in a non-empty state in the upstream end of the interface and the read command or the empty signal of the data FIFO in the downstream of the interface is judged to be non-empty by the finite state machine.
2. The FIFO master interface device of claim 1, wherein the FIFO slave interface state signal downstream of the interface comprises: a write command FIFO full signal, a read command FIFO empty signal, a write data FIFO full signal, and a read data FIFO empty signal.
3. The FIFO master interface device of claim 1, wherein the upstream end of the FIFO master interface is further to receive upstream control signals including an input clock signal to an upstream device, a write enable signal, a read enable signal, and an end of packet input signal.
4. The FIFO master interface device of claim 1, wherein the downstream end of the FIFO master interface is further to transmit downstream interface control signals, the downstream interface control signals being a chip select signal, a read data or command enable signal, a write data or command enable signal, a data or command input or output, a command FIFO select signal, and an end of packet signal.
5. The FIFO master interface device of claim 1, wherein the FIFO master interface is implemented using a field programmable gate array.
6. An FIFO master interface system is characterized in that the upstream end of the FIFO master interface system is connected with an upstream device, and the downstream end of the FIFO master interface system is connected with a downstream device; the upstream device is provided with a FIFO interface for invoking the FIFO master interface device of any one of claims 1-5; the downstream device conforms to a slave FIFO timing; the FIFO master interface is used for realizing the intercommunication between the upstream device and the downstream device.
7. The FIFO master interface system of claim 6, wherein the FIFO master interface is operable to effect intercommunication between the upstream device and the downstream device by:
the upstream device writes commands or data into a write FIFO module in an FIFO master interface through an FIFO interface, and a finite state machine in the FIFO master interface is used for judging the FIFO empty and full state of the downstream device so as to generate corresponding control signals and perform write command or data operation on the downstream device;
the upstream device carries out reading command or data operation according to the empty and full state of the FIFO of the downstream device, a finite state machine in the FIFO master interface generates corresponding control signals, reads back commands or data from the FIFO slave of the downstream device, and caches the commands or data into a reading FIFO module in the FIFO master interface.
8. The FIFO master interface system of claim 6, wherein the upstream device reads the command or data in the read FIFO block through the FIFO interface when the empty signal of the read FIFO block is in a non-empty state.
9. An FPGA chip having a FIFO master interface device according to any one of claims 1-5.
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CN203590251U (en) * 2013-11-22 2014-05-07 中国电子科技集团公司第三十二研究所 FlexRay control system based on serial RapidIO bus
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