CN111192233B - Preparation method and preparation device of semiconductor structure - Google Patents
Preparation method and preparation device of semiconductor structure Download PDFInfo
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- CN111192233B CN111192233B CN201811353789.3A CN201811353789A CN111192233B CN 111192233 B CN111192233 B CN 111192233B CN 201811353789 A CN201811353789 A CN 201811353789A CN 111192233 B CN111192233 B CN 111192233B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
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- G06T7/0002—Inspection of images, e.g. flaw detection
- G06T7/0004—Industrial image inspection
- G06T7/001—Industrial image inspection using an image reference approach
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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Abstract
The invention provides a preparation method of a semiconductor structure. The semiconductor manufacturing method may include acquiring a reference image of each substrate; selecting a reference image of any base body with a connecting part as a target image; determining at least one comparison image according to the target image, wherein a substrate of the comparison image is connected with a substrate of the target image; and correcting the image of the connecting part corresponding to the image in the target image according to the image of at least one connecting part in the comparison image to obtain a standard image. And correcting the images corresponding to the substrate connecting parts with the connecting relationship, and fully considering the correlation among the images of each layer, so that the process window of the semiconductor structure prepared by the method is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a preparation method of a semiconductor structure and a semiconductor preparation device applying the semiconductor preparation method.
Background
With the development of semiconductor technology, the design and manufacture of semiconductor structures have entered the ultra-deep submicron stage, and the feature size has been close to or even smaller than the wavelength of light used in the photolithography process. In this case, the image on the mask plate will be deformed during the transfer, so that there is a certain deformation and deviation between the actually obtained lithography pattern and the mask pattern, and such an error in the lithography directly affects the performance of the semiconductor structure.
In order to eliminate such errors as much as possible, the images are usually corrected, and in the prior art, the relationship between the multiple layers of images is usually not considered, and each layer is corrected separately, so that the process window for preparing the semiconductor structure by adopting the method is poor.
The above information disclosed in this background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not constitute prior art that is already known to a person of ordinary skill in the art.
Disclosure of Invention
The invention aims to overcome the defect of poor process window of the semiconductor structure manufactured in the prior art and provides a method for manufacturing the semiconductor structure with a higher process window.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
According to an aspect of the present invention, a method of manufacturing a semiconductor structure including a plurality of stacked substrates that are connected to each other through a connection portion each included, includes:
acquiring a reference image of each matrix;
selecting a reference image of any one of the substrates with the connecting part as a target image;
determining at least one comparison image according to the target image, wherein a substrate of the comparison image is connected with a substrate of the target image;
and correcting the image of the connecting part corresponding to the image in the target image according to the image of at least one connecting part in the comparison image to obtain a standard image.
In an exemplary embodiment of the present disclosure, the method of manufacturing a semiconductor structure further includes:
and carrying out optical proximity correction on the reference image.
In an exemplary embodiment of the present disclosure, the method of manufacturing a semiconductor structure further includes:
the semiconductor structure is formed according to the plurality of layers of the standard image.
In an exemplary embodiment of the present disclosure, the method of manufacturing a semiconductor structure further includes:
and forming a plurality of layers of the base body according to the plurality of layers of the standard images, wherein the plurality of layers of the base body are stacked to form the semiconductor structure.
In an exemplary embodiment of the present disclosure, the determining at least one comparison image from the target image, the interconnecting of the comparison image substrate and the target image substrate includes:
and determining all comparison images according to the target image, wherein the matrix of the comparison images is connected with the matrix of the target image.
In an exemplary embodiment of the present disclosure, the correcting the image of the connecting portion corresponding to the image of the at least one connecting portion in the target image according to the comparison image to obtain the standard image includes:
and correcting the images of the connecting parts corresponding to the reference images according to the images of all the connecting parts in the comparison images to obtain standard images.
In an exemplary embodiment of the present disclosure, the correcting the image of the connecting portion corresponding to the image of the at least one connecting portion in the target image according to the comparison image to obtain the standard image includes:
and correcting the position of the image of the connecting part in the target image so that the image of the connecting part of the target image is just opposite to the image of the connecting part of the comparison image.
In an exemplary embodiment of the present disclosure, the correcting the image of the connecting portion corresponding to the image of the at least one connecting portion in the target image according to the comparison image to obtain the standard image includes:
correcting one or more of the size and the shape of the image of the connecting part in the target image.
In an exemplary embodiment of the disclosure, a first overlay alignment process window is provided between the substrate corresponding to the standard image and the substrate corresponding to the comparison image, a second overlay alignment process window is specifically provided between the substrate corresponding to the reference image and the substrate corresponding to the comparison image, and the first overlay alignment process window is larger than the second overlay alignment process window.
According to an aspect of the present disclosure, there is provided a manufacturing apparatus of a semiconductor structure, including:
the acquisition module is used for acquiring a reference image of each matrix;
the selection module is used for selecting any reference image of the base body with the connecting part as a target image;
the analysis determination module is used for determining at least one comparison image according to the target image, and a matrix of the comparison image is connected with a matrix of the target image;
and the correction module is used for correcting the image of the connecting part corresponding to the image in the target image according to the image of at least one connecting part in the comparison image to obtain a standard image.
According to the technical scheme, the invention has at least one of the following advantages and positive effects:
the invention relates to a method and equipment for preparing a semiconductor structure, wherein the semiconductor structure comprises a plurality of laminated substrates, at least two substrates are connected with each other through a connecting part respectively included in the substrates, and the method for preparing the semiconductor structure comprises the steps of acquiring reference images of the substrates; selecting a reference image of any base body with a connecting part as a target image; determining at least one comparison image according to the target image, wherein a substrate of the comparison image is connected with a substrate of the target image; and correcting the image of the connecting part corresponding to the image in the target image according to the image of at least one connecting part in the comparison image to obtain a standard image, and correcting the image corresponding to the connecting part of the base body with the connection relation. In the process, because the images corresponding to the connecting parts of the substrates with the connection relation are corrected, the correlation among the images with the connection relation is fully considered, and the process window of the prepared semiconductor structure is improved.
Drawings
The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.
FIG. 1 is a flow chart of a semiconductor manufacturing process of the present invention;
FIG. 2 is a schematic illustration of a first reference image in an example embodiment of the invention;
FIG. 3 is a schematic illustration of a second reference image in an example embodiment of the invention;
FIG. 4 is a schematic illustration of a third reference image in an example embodiment of the invention;
FIG. 5 is a diagram illustrating a first reference image as a target image and a second reference image as a comparison image according to an exemplary embodiment of the present invention;
FIG. 6 is a diagram illustrating a first reference image as a target image and a second reference image and a third reference image as comparison images in an exemplary embodiment of the invention;
fig. 7 is a schematic diagram of a block diagram of the structure of a semiconductor structure fabrication apparatus in an example embodiment of the invention.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.
The present invention provides, in a first aspect, a method of fabricating a semiconductor structure, which may include a plurality of stacked substrates, at least two of which are interconnected by a respective connection, the semiconductor structure being a chip or other structure.
As shown in fig. 1, the method for fabricating the semiconductor structure may include the steps of:
step S110, a reference image of each of the substrates is acquired.
And step S120, selecting a reference image of any base body with the connecting part as a target image.
Step S130, determining at least one comparison image according to the target image, wherein a matrix of the comparison image is connected with a matrix of the target image.
Step S140, correcting the image of the connecting part corresponding to the image in the target image according to the image of at least one connecting part in the comparison image to obtain a standard image.
Next, a method for manufacturing the semiconductor structure in this example embodiment will be further described.
In step S110, a reference image of each of the substrates is acquired.
In the present exemplary embodiment, the semiconductor structure to be fabricated has a plurality of layers of substrates, the plurality of layers of substrates are stacked, each layer of substrate corresponds to a reference image, and the substrate is fabricated according to the corresponding reference image; and acquiring a reference image corresponding to each substrate, and performing optical proximity correction on each layer of acquired reference image, wherein the optical proximity correction can be model-based optical proximity correction.
In step S120, a reference image of any one of the substrates having the connecting portion is selected as a target image.
And identifying whether the image of the connecting part exists in the reference images of the base bodies, and determining the reference image of the connecting part exists, so that one target image is selected from the reference images of the connecting part. The shape of the image corresponding to the connecting part can be rectangular, circular, oval or other shapes.
In step S130, at least one comparison image is determined from the target image, and the base of the comparison image and the base of the target image are connected to each other.
And selecting at least one image as a comparison image from reference images corresponding to the base body with the connecting part corresponding to the target image.
The base body corresponding to the target image can only have a connection relation with the base body of one layer of comparison image, and the base body corresponding to the target image can also be connected with the base bodies corresponding to the multiple layers of reference images, at this time, one comparison image can be determined, and a plurality of comparison images can also be determined; it is also possible to confirm all as comparison images.
For example, the substrate corresponding to the selected target image is connected with the substrates corresponding to the four layers of reference images, and at this time, only one layer of the four layers of reference images can be confirmed as a comparison image, and two or three layers of the four layers of reference images can also be confirmed as comparison images; all four-layer reference images can also be used as comparison images.
When all reference images corresponding to the base bodies which are connected with the base bodies corresponding to the target images are used as comparison images, the target images can be repaired more comprehensively, so that the alignment error redundancy of the base bodies corresponding to the target images and the base body connecting parts of the comparison images is improved, namely, the alignment process window is improved, and the process window for manufacturing the semiconductor structure is further improved.
The connection relationship may be that the substrate corresponding to the target image is in direct contact with the substrate corresponding to the comparison image, for example, a contact point is formed between the upper layer and the lower layer; the substrate corresponding to the target image may be indirectly connected to the substrate corresponding to the comparison image by other means, such as a plug hole.
In step S140, the image of the corresponding connection portion in the target image is corrected according to the image of at least one connection portion in the comparison image to obtain a standard image.
The base body corresponding to the target image and the base body corresponding to the comparison image are provided with connecting parts, the connecting parts on the base bodies correspond to the connecting areas on the images, and the target image and each layer of comparison image can be provided with one connecting area or a plurality of connecting areas. And correcting the target image by taking the contrast image as a reference. In the calibration, only one connected region on the target image may be calibrated, or all connected regions on the comparison image may be calibrated, which is not specifically limited herein. When all the connection areas on the target image are corrected, the target image can be repaired more comprehensively, so that the alignment error redundancy of the connection part of the base body corresponding to the target image and the base body of the comparison image is improved, namely, the alignment process window is improved, and the process window for manufacturing the semiconductor structure is further improved.
Correcting the target image may include correcting one or more of a size and a shape of an image of the connection portion in the target image; and correcting the position of the image of the connecting part in the target image, so that the image of the connecting part of the base body corresponding to the target image is just opposite to the image of the connecting part of the base body corresponding to the comparison image.
During correction, one or more of the size and the shape of the image of the connecting part in the target image can be corrected, and the correction process can be to match the size, the shape and the like of the target image with the comparison image, for example, the image of the connecting part of the base body corresponding to the comparison image is square, but the image of the connecting part of the base body corresponding to the target image is rectangular, during correction, the image of the connecting part of the base body corresponding to the target image is corrected to be square, and the side length of the square is slightly larger than that of the image of the connecting part of the base body corresponding to the comparison image; here, the size and the dimension of the image of the substrate connecting portion corresponding to the target image are corrected, and only the dimension or only the shape may be corrected.
Of course, the target Image may be corrected according to CD (critical dimension), DOF (Depth of focus), MEEF (Mask Error Enhancement factor), and NILS (Normalized Image Log Slope) Normalized logarithmic Slope in the correction process. A first overlay alignment process window is arranged between the substrate corresponding to the standard image and the substrate corresponding to the comparison image, a specific second overlay alignment process window is arranged between the substrate corresponding to the target image and the substrate corresponding to the comparison image, and the first overlay alignment process window is larger than the second overlay alignment process window; that is, the overlay alignment error redundancy of the first overlay alignment process window is greater than the overlay alignment error redundancy of the second overlay alignment process window. The correction of the target image may be correction of the entire target image or correction of a local region of the target image. The size relationship between the first and second overlay alignment process windows is explained below by two example embodiments.
As an example, a connection portion between the base corresponding to the target image and the base corresponding to the comparison image is a square, a side length of the square of the connection portion of the base corresponding to the target image is 5 micrometers, and a side length of the square of the connection portion of the base corresponding to the comparison image is about 4 micrometers; after correction, the connecting part between the base body corresponding to the standard image and the base body corresponding to the comparison image can also be a square, the side length of the square of the connecting part of the base body corresponding to the standard image can be about 6 micrometers, and the side length of the square of the connecting part of the base body corresponding to the comparison image is also 4 micrometers; at the moment, the first alignment process window is larger than the second alignment process window, so that a certain error redundancy range can be reserved in the production process.
As an example, a connecting part is arranged between a substrate corresponding to a target image and a substrate corresponding to a comparison image, the connecting part of the substrate corresponding to the target image is a line with the width of 50 nanometers, the length is not limited, the connecting part of the substrate corresponding to the comparison image is a square with the side length of about 40 nanometers, the distance between two sides of the square and two sides of the line is 2 nanometers and 8 nanometers respectively, after correction, the width of the line is increased by 4 nanometers on the side, which is 2 nanometers away from the side of the square, of the connecting part of the line and the square, so that the alignment error redundancy of the rectangle for alignment of the line is increased; the connecting part of the base body corresponding to the standard image is a line with the width of 54 nanometers, the connecting part of the base body corresponding to the comparison image is a square with the side length of 40 nanometers, and at the moment, the distance between the square and the two ends of the line is respectively 6 nanometers and 8 nanometers, so that the purpose that the first alignment process window is larger than the second alignment process window is achieved, and a certain error redundancy range is reserved in the production process.
After the above steps are finished, the preparation method of the embodiment of the present disclosure may further include:
step S160, forming the semiconductor structure according to the plurality of layers of the standard images.
The semiconductor structure may be formed using a masking process, for example, by fabricating a plurality of masks according to a plurality of standard images, each standard image corresponding to one mask, the pattern on each mask being the same as the standard image corresponding to the mask;
and sequentially forming each layer of matrix on a substrate by adopting each mask plate and utilizing a photoetching process, wherein the patterns on each layer of matrix are the same as the patterns on the corresponding mask plate.
The method of fabricating the semiconductor structure of the present invention is described below with reference to a specific example.
In the present exemplary embodiment, referring to fig. 2, fig. 3 and fig. 5, the target image in fig. 2 is used as a first reference image, the first reference image may be a connection layer image 1, the comparison image is a second reference image, the second reference image may be a contact layer image 2, the connection layer image 1 is located above the contact layer image 2, and the connection layer image 1 and the contact layer image 2 have a plurality of first connection regions. At this time, the connection layer image 1 is corrected by considering the contact hole layer image 2, and only one first connection area can be corrected during correction, so that the connection layer image 1 in the first connection area completely covers the touch layer image in the same first connection area; it is also possible to correct all the link layer images 1 in the first connection area of the link layer image 1 and the touch layer image so that the link layer image 1 completely covers the contact hole layer image 2. In another exemplary embodiment, the contact hole layer image 2 may be a target image, and the interconnect layer image 1 may be a comparison image.
In order to consider the case where only one layer of the reference image and the target image have a connected region, the following describes a correction method when two layers of the reference image and the target image have a connected region.
In this example embodiment, referring to fig. 2, 3, 4, and 6, the target image is a first reference image, the first reference image may be a link layer image 1, the comparison image may be a second reference image and a third reference image, the second reference image may be a contact layer image 2, and the third reference image may be a contact layer image 3; the connecting line layer image 1 is positioned on the contact hole layer image 2, and the contact layer is positioned on the connecting line layer; at the moment, the connecting line layer image 1 is corrected by simultaneously considering the contact hole layer image 2 and the contact layer image 3, so that the connecting line layer image 1 completely covers the contact layer image 2, and meanwhile, the contact layer image 3 can be completely positioned in the connecting line layer image 1; during correction, the connecting layer image 1 and the contact hole layer image 2 are provided with a first connecting area, the first connecting area on the connecting layer image 1 is properly amplified, and a certain overlay alignment error redundant space is reserved while the connecting area of the contact hole layer image 2 and the connecting layer image 1 is completely covered by the connecting layer image 1. The wiring layer image 1 and the contact layer image 3 have a second connection area, the second connection area on the wiring layer image 1 is properly enlarged, and a certain overlay alignment error redundant space is reserved while the wiring layer image 1 completely covers the second connection area of the contact layer image 3 and the wiring layer image 1.
It should be noted that, when there are multiple layers of comparison images, the target image may be corrected by referring to the correction method when there are two layers of comparison images, and meanwhile, the target image and the comparison images in the above-mentioned exemplary embodiment may be interchanged.
Referring to fig. 7, the present invention further provides a semiconductor structure manufacturing apparatus 1000, which can be used for manufacturing semiconductor structures, such as chips or other structures on a wafer.
The apparatus for manufacturing a semiconductor structure comprises an acquisition module 1010, a selection module 1020, an analysis determination module 1030, and a correction module 1040, wherein:
the obtaining module 1010 may be configured to obtain a reference image of each substrate;
the selection module 1020 is used for selecting a reference image of any one of the substrates with the connecting part as a target image;
the analysis determining module 1030 is configured to determine at least one comparison image according to the target image, wherein a base body of the comparison image is connected with a base body of the target image;
the correcting module 1040 is configured to correct the image of the connecting portion corresponding to the image in the target image according to the image of at least one connecting portion in the comparison image, so as to obtain a standard image.
The details of each module in the above semiconductor structure manufacturing apparatus have been described in detail in the corresponding semiconductor structure manufacturing method, and therefore, the details are not described herein again.
The manufacturing apparatus 1000 according to the embodiment of the present invention may further include manufacturing a plurality of layers of masks according to the obtained standard image, and then manufacturing a semiconductor structure by using the masks manufactured using the standard image through a photolithography process or other processes.
It should be noted that although in the above detailed description several modules or units of the device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit, according to embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into embodiments by a plurality of modules or units.
The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments, and the features discussed in connection with the embodiments are interchangeable, if possible. In the above description, numerous specific details are provided to give a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention may be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.
The terms "about" and "approximately" as used herein generally mean within 20%, preferably within 10%, and more preferably within 5% of a given value or range. The amounts given herein are approximate, meaning that the meaning of "about", "approximately" or "approximately" may still be implied without specific recitation.
Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be appreciated that if the device of the icon were turned upside down, the element described as "upper" would become the element "lower". When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.
In this specification, the terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising," "including," and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.; the terms "first," "second," and "third," etc. are used merely as labels, and are not limiting on the number of their objects.
It is to be understood that the invention is not limited in its application to the details of construction and the arrangement of components set forth in the description. The invention is capable of other embodiments and of being practiced and carried out in various ways. The foregoing variations and modifications fall within the scope of the present invention. It will be understood that the invention disclosed and defined in this specification extends to all alternative combinations of two or more of the individual features mentioned or evident from the text and/or drawings. All of these different combinations constitute alternative aspects of the present invention. The embodiments described in this specification illustrate the best mode known for carrying out the invention and will enable those skilled in the art to utilize the invention.
Claims (8)
1. A method of fabricating a semiconductor structure comprising a plurality of stacked substrates, at least two of the substrates being interconnected by a respective connection, the method comprising:
acquiring a reference image of each matrix, and carrying out optical proximity correction on the reference image;
selecting a reference image of any one of the substrates with the connecting part as a target image;
determining at least one comparison image according to the target image, wherein a substrate of the comparison image is connected with a substrate of the target image;
correcting the image of the connecting part corresponding to the image in the target image according to the image of at least one connecting part in the comparison image to obtain a standard image;
the semiconductor structure is formed according to the plurality of layers of the standard image.
2. The method of claim 1, further comprising:
and forming a plurality of layers of the base body according to the plurality of layers of the standard images, wherein the plurality of layers of the base body are stacked to form the semiconductor structure.
3. The method of claim 1, wherein said determining at least one alignment image from said target image, said interconnecting of said alignment image substrate and said target image substrate comprises:
and determining all comparison images according to the target image, wherein the matrix of the comparison images is connected with the matrix of the target image.
4. The method as claimed in claim 1, wherein the step of correcting the image of the corresponding connection portion in the target image according to the image of the corresponding connection portion in the comparison image to obtain a standard image comprises:
and correcting the images of the connecting parts corresponding to the reference images according to the images of all the connecting parts in the comparison images to obtain standard images.
5. The method as claimed in claim 1, wherein the step of correcting the image of the corresponding connection portion in the target image according to the image of the corresponding connection portion in the comparison image to obtain a standard image comprises:
and correcting the position of the image of the connecting part in the target image so that the image of the connecting part of the target image is just opposite to the image of the connecting part of the comparison image.
6. The method as claimed in claim 4, wherein the step of correcting the image of the corresponding connection portion in the target image according to the image of the corresponding connection portion in the comparison image to obtain a standard image comprises:
correcting one or more of the size and the shape of the image of the connecting part in the target image.
7. The method of claim 1, wherein a first overlay alignment process window is provided between the substrate corresponding to the standard image and the substrate corresponding to the comparison image, a second overlay alignment process window is provided between the substrate corresponding to the reference image and the substrate corresponding to the comparison image, and the first overlay alignment process window is larger than the second overlay alignment process window.
8. An apparatus for fabricating a semiconductor structure, comprising:
the acquisition module is used for acquiring a reference image of each matrix and carrying out optical proximity correction on the reference image;
the selection module is used for selecting any reference image of the base body with the connecting part as a target image;
the analysis determination module is used for determining at least one comparison image according to the target image, and a matrix of the comparison image is connected with a matrix of the target image;
the correction module is used for correcting the image of the connecting part corresponding to the image in the target image according to the image of at least one connecting part in the comparison image to obtain a standard image;
the semiconductor structure manufacturing apparatus is used for forming the semiconductor structure according to the plurality of layers of the standard images.
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