CN111190646A

CN111190646A - eMMC initialization and control method, device and terminal based on FPGA

Info

Publication number: CN111190646A
Application number: CN201911321030.1A
Authority: CN
Inventors: 王立浩
Original assignee: Shenzhen Pango Microsystems Co Ltd
Current assignee: Shenzhen Pango Microsystems Co Ltd
Priority date: 2019-12-19
Filing date: 2019-12-19
Publication date: 2020-05-22

Abstract

The invention discloses an FPGA-based eMMC initialization and control method, device and terminal, wherein the FPGA-based eMMC control device comprises a third receiving module and a third sending module, receives a target instruction which is sent by a CPU and comprises identification information of a target instruction object eMMC, and sends the target instruction to each initialized target eMMC in parallel respectively. The invention also discloses an eMMC initialization and control method, a device and a terminal based on the FPGA, and solves the problems that in the related technology, a plurality of eMMC chips are bridged to a CPU host, the pressure on PCB wiring is large, the interface processing is not flexible enough, and the speed of reading and writing a plurality of eMMC by the CPU is limited. The multi-piece eMMC is connected with the CPU in parallel in a bridging mode through the eMMC control device based on the FPGA, the target instruction of the CPU is sent to each eMMC including the target instruction object eMMC in parallel, the reading and writing of the plurality of eMMC by the CPU are not limited by the PCB routing, the reading and writing speed of the plurality of eMMC by the CPU is improved, and interface processing is flexible.

Description

eMMC initialization and control method, device and terminal based on FPGA

Technical Field

The invention relates to the field of memory interface processing, in particular to an eMMC initialization and control method, an eMMC initialization and control device and a terminal based on an FPGA.

Background

With the flexible requirements for signal transmission in the fields of communication, storage, and the like, it is difficult for the current CPU as a host to meet the requirements of flexible processing interfaces in an implementation method of interfacing multiple eMMC (embedded multimedia Card). Because the reading of the eMMC chip data needs to be initialized, data receiving and sending control and the like according to an eMMC protocol, a CPU host is in bridge connection with a plurality of eMMC chips, interface processing is not flexible enough, the requirement on PCB wiring delay is high, the quantity of the eMMC is more, the PCB wiring pressure is higher, and the speed of reading and writing a plurality of eMMC by the CPU is limited.

Disclosure of Invention

The invention aims to solve the technical problems that a plurality of eMMC chips are bridged to a CPU host, the pressure on PCB routing is high, interface processing is not flexible enough, and the speed of reading and writing a plurality of eMMC chips by a CPU is limited in the related technology.

In order to solve the above technical problem, the present invention provides an FPGA-based eMMC control device that bridges in parallel at least two pieces of initialized target eMMC, the FPGA-based eMMC control device including:

a third receiving module, configured to receive a target instruction sent by the CPU, where the target instruction includes identification information of a target instruction object eMMC, and the target instruction object eMMC is one target eMMC in the target eMMC that has completed initialization;

and the third sending module is used for sending the target instruction to each initialized target eMMC in parallel.

Optionally, the FPGA-based eMMC control apparatus further includes a second determination module;

the second judging module is used for judging the target instruction object eMMC aiming at the target instruction

Whether a response target instruction needs to be sent;

and/or the presence of a gas in the gas,

and the method is used for judging whether the target instruction is legal or not.

Optionally, the FPGA-based eMMC control apparatus further includes a fourth receiving module and a fourth sending module;

the fourth receiving module is used for judging the target instruction if the second judging module judges that the target instruction is aimed at

The target instruction object eMMC needs to send a response target instruction and receives the response target instruction sent by the target instruction object eMMC;

the fourth sending module is configured to send the response target instruction to the CPU.

Optionally, the FPGA-based eMMC control device further includes a data processing module, and the target instruction includes a data transmission instruction;

the data processing module is used for receiving the data transmission instruction sent by the CPU and then transmitting the data

Before the transmission instruction is sent to the target instruction object eMMC, a first processing operation is performed on data in the data transmission instruction.

Optionally, the data processing module is further configured to receive a response sent by the target instruction object eMMC

And after the target instruction, before the response target instruction is sent to the CPU, performing second processing operation on the data in the response target instruction.

Optionally, the FPGA-based eMMC control apparatus further includes at least one of: the device comprises a checking module and a time sequence control module;

the check module is used for at least one of the following: judging whether the target instruction received by the third receiving module is legal or not and judging whether the response target instruction received by the fourth receiving module is legal or not;

the timing control module is used for at least one of the following: the receiving time sequence of the third receiving module for receiving the target instruction is controlled, the sending time sequence of the third sending module for sending the target instruction is controlled, the receiving time sequence of the fourth receiving module for receiving the response target instruction is controlled, and the sending time sequence of the response target instruction sent by the fourth sending module is controlled.

The invention also provides an eMMC initialization device based on the FPGA, which comprises:

the first receiving module is used for receiving an eMMC initialization operation instruction sent by the CPU;

the parallel control module is used for determining a target eMMC which is not initialized;

a first sending module, configured to send the eMMC initialization operation instruction to the target eMMC;

a second receiving module, configured to receive an initialization response message of the target eMMC for the eMMC initialization operation instruction, where the initialization response message includes identification information of the target eMMC;

and the second sending module is used for sending the initialization response message to the CPU.

Optionally, the FPGA-based eMMC initialization apparatus further includes:

the identification module is used for identifying the eMMC initialization operation instruction;

the first judging module is used for judging whether the eMMC initialization operation instruction is a legal instruction or not before the first sending module sends the eMMC initialization operation instruction to the target eMMC.

Optionally, the FPGA-based eMMC initialization apparatus bridges at least two emmcs in parallel, and the FPGA-based eMMC initialization apparatus further includes:

an adjustment module, configured to determine the number of emmcs that are bridged in parallel by the FPGA-based eMMC initialization apparatus;

and/or the presence of a gas in the gas,

the method and the device are used for determining the total quantity of the target eMMC determined by the parallel control module in an accumulated mode in a preset period, wherein the preset period comprises a period from a first eMMC initialization operation instruction to a last eMMC initialization operation instruction which are continuously sent by the CPU.

The invention also provides an eMMC control method based on the FPGA, which is applied to any one of the eMMC control devices based on the FPGA, and comprises the following steps:

receiving a target instruction sent by a CPU, wherein the target instruction comprises identification information of a target instruction object eMMC, and the target instruction object eMMC is one target eMMC in the target eMMC after initialization is completed;

sending the target instruction to each initialized target eMMC in parallel;

if a response target instruction needs to be sent to the target instruction object eMMC aiming at the target instruction, receiving the response target instruction sent by the target instruction object eMMC;

and sending the response target instruction to the CPU.

The invention also provides a terminal which comprises a CPU, at least two target eMMC and an FPGA, wherein one end of the FPGA is connected with the CPU, the other end of the FPGA is in parallel bridge connection with each target eMMC, and the FPGA comprises any one of the eMMC control device based on the FPGA and/or any one of the eMMC initialization device based on the FPGA.

The invention has the following beneficial effects:

the invention provides an FPGA-based eMMC control device, which is used for bridging at least two initialized target eMMC in parallel and receiving a target instruction sent by a CPU through a third receiving module, wherein the target instruction comprises identification information of a target instruction object eMMC, the target instruction object eMMC is one target eMMC in the initialized target eMMC, and the target instruction is respectively sent to each initialized target eMMC in parallel through the third sending module. The multi-piece eMMC is bridged to the CPU through the eMMC control device based on the FPGA, and a target instruction of the CPU is parallelly sent to each eMMC including a target instruction object eMMC, so that the reading and writing of the plurality of eMMC by the CPU are not influenced by PCB routing, the reading and writing speed of the plurality of eMMC by the CPU is improved, and interface processing is more flexible. Meanwhile, the identity identification information of the target instruction object eMMC is added in the target instruction, so that a plurality of target eMMC which are in parallel bridge connection with the eMMC control device of the FPGA can receive the target instruction immediately, but only the target instruction object eMMC corresponding to the identity identification information can respond to the target instruction, and the CPU can also realize the control of a certain target eMMC in a targeted manner.

Drawings

Fig. 1 is a schematic structural diagram of an eMMC initialization apparatus based on an FPGA according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of an eMMC control device 200 based on an FPGA according to a second embodiment of the present invention;

fig. 3-1 is a system block diagram of an eMMC parallel bridge CPU in the third embodiment of the present invention;

fig. 3-2 is a connection diagram of an eMMC _ Bridge module inside the FPGA of fig. 3-1 according to a third embodiment of the present invention;

fig. 4 is a schematic flowchart of an eMMC initialization method based on an FPGA according to a fourth embodiment of the present invention;

fig. 5 is a schematic flowchart of an eMMC control method based on an FPGA according to a fifth embodiment of the present invention;

fig. 6 is a schematic structural diagram of a terminal in a sixth embodiment of the present invention.

Detailed Description

The present invention will be described in further detail below with reference to the accompanying drawings and the following embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the invention.

Example 1

As shown in fig. 1, an FPGA-based eMMC initialization apparatus 100 according to an embodiment of the present invention includes:

a first receiving module 101, configured to receive an eMMC initialization operation instruction sent by a CPU;

a parallel control module 102, configured to determine a target eMMC;

the first sending module 103 is configured to send an eMMC initialization operation instruction to a target eMMC;

a second receiving module 104, configured to receive an initialization response message of the target eMMC for the eMMC initialization operation instruction;

a second sending module 105, configured to send the initialization response message to the CPU.

It should be noted that the FPGA-based eMMC initialization apparatus in this embodiment is connected to the CPU and the at least one eMMC, and when the FPGA-based eMMC initialization apparatus is connected to the plurality of emmcs, the plurality of emmcs based on the FPGA can be connected to the CPU in parallel.

Note that the target eMMC has not yet been initialized.

In some embodiments, when the FPGA-based eMMC initialization apparatus is connected to multiple emmcs, the parallel control module determines only one target eMMC from among the emmcs upon receiving one eMMC initialization operation instruction. Thus, one eMMC initialization operation instruction of the CPU can be ensured to initialize only one piece of eMMC connected with the current eMMC initialization device. After the eMMC is initialized, an initialization response message is sent, where the response message includes identification information of the target eMMC. Based on the above principle, after the second sending module sends the initialization response message to the CPU, the CPU may obtain the identification information of each eMMC that has currently completed initialization. Specifically, when the eMMC initialization device is connected with 3 pieces of eMMC, after the CPU receives an initialization response message of a first piece of eMMC, the eMMC initialization operation command is sent again, the parallel control module selects a piece of target eMMC again, the target eMMC is not initialized, further, after the CPU receives an initialization response message of a second piece of target eMMC for the second time, the eMMC initialization operation command is sent for the third time, the parallel control module selects a piece of target eMMC again, the target eMMC is not initialized, further, after the CPU receives an initialization response message of a third piece of target eMMC for the third time, the eMMC initialization operation command is sent for the fourth time, at the moment, because the connected eMMC are only three pieces in total, the parallel control module can not determine a piece of target eMMC, and within a certain time, the CPU does not receive the initialization response message and considers that the current pieces of MCs needing initialization are all initialized, and finishing the initialization process. Since each initialization response message includes the identification information of the target eMMC from which the initialization response message is sent, when the CPU ends the initialization process, the CPU has already acquired the identification information of each eMMC bridged with the CPU. Note that, multiple emmcs are bridged in parallel with the FPGA-based eMMC initialization apparatus, and the identification information of each eMMC is unique.

In some embodiments, when the initialization apparatus is connected to multiple emmcs, the first receiving module is further configured to receive an eMMC initialization operation instruction that is sent again by the CPU after receiving the initialization response message, determine a next target eMMC through the parallel control module, send the eMMC initialization operation instruction to the next target eMMC through the first sending module, send the initialization response message sent by the next target eMMC to the CPU, and loop until the parallel control module determines that the next target eMMC is not located in the emmcs connected to the initialization apparatus. It is noted that in some embodiments, the reason for the concurrency control module determining that there is less than one target eMMC may be referred to as the adjustment module described below.

In some embodiments, referring to fig. 1, the FPGA-based eMMC initialization apparatus 100 further includes:

the identification module 106 is configured to identify an eMMC initialization operation instruction;

the first determining module 107 is configured to determine whether the eMMC initialization operation instruction is a legal instruction before the first sending module 101 sends the eMMC initialization operation instruction to the target eMMC.

It should be noted that, in some embodiments, the identification module is also used for reading and writing the status register.

It should be noted that, when the first determining module determines that the eMMC initialization operation instruction is a legal instruction, the first sending module sends the eMMC initialization operation instruction to the target eMMC.

In some embodiments, the parallel control module determines a target eMMC only when the first determining module determines that the eMMC initialization operation instruction is a legal instruction.

When the FPGA-based eMMC initialization device is bridged in parallel with at least two emmcs, sometimes it is not necessary to initialize all the emmcs, and at this time, the number of the initialized emmcs can be adjusted by setting the adjustment module, and therefore, in some embodiments, the FPGA-based eMMC initialization device further includes the adjustment module:

the adjusting module is used for determining the number of the eMMC bridged in parallel by the eMMC initializing device based on the FPGA;

and/or the presence of a gas in the gas,

the method is used for determining the total quantity of the target eMMC determined by the parallel control module in an accumulated mode in a preset period, wherein the preset period comprises a period from a first time of eMMC initialization operation instruction to a last time of eMMC initialization operation instruction which are continuously sent by the CPU.

It is to be understood that the adjustment direction of the adjustment module may be, on one hand, adjusting the number of emmcs connected to the initialization device, and/or adjusting the number of target emmcs determined by the parallel control module according to each eMMC initialization operation instruction, and determining the cumulative number of target emmcs within a preset period, thereby adjusting the number of initialization emmcs.

In some embodiments, the number of eMMC chips that need to be increased or decreased may be adjusted via the DEV _ NUM parameter.

In some embodiments, after the CPU issues the last eMMC initialization operation instruction, the CPU completes initialization of the eMMC if the initialization response message is not received within a certain time. At this time, on one hand, the CPU acquires the identification information of each eMMC bridged therewith, on the other hand, each eMMC indirectly establishes a connection relationship with the CPU, and each instruction subsequent to the CPU may be sent to each eMMC connected with the CPU.

In some embodiments, the parallel control module is further configured to, after the CPU completes initialization of the eMMC, perform a parallel processing on each eMMC reply.

In some embodiments, the first receiving module and the second receiving module may be integrated into a first tri _ ctrl module, and through the control of the first tri _ ctrl module on the FPGA device IO, the independent modules are very friendly to platform migration and addition of the eMMC device.

In some embodiments, the first sending module and the second sending module may be integrated into a second tri _ ctrl module, and through the control of the second tri _ ctrl module on the FPGA device IO, the independent modules are very friendly to platform migration and addition of the eMMC device.

The embodiment of the invention provides an eMMC initialization device based on an FPGA, which determines a target eMMC by receiving an eMMC initialization operation instruction sent by a CPU, sends the eMMC initialization operation instruction to the target eMMC, receives an initialization response message of the target eMMC according to the eMMC initialization operation instruction, and sends the initialization response message to the CPU. Because the parallel control module only determines one target eMMC each time, when the parallel control module determines one target eMMC, the eMMC initialization operation instruction sent by the CPU is only sent to the target eMMC, and the received initialization response message only comprises the identity information of the target eMMC. When the FPGA-based eMMC initialization device is connected with N pieces of eMMC, only an eMMC initialization operation instruction needs to be sent to one piece of eMMC determined by the parallel control module each time, and identity identification information of the N pieces of eMMC is respectively sent to the CPU by receiving the eMMC initialization operation instruction sent by the CPU for N +1 times and correspondingly sending an initialization response message to the CPU for N times. The FPGA-based eMMC initialization device is used for realizing the respective initialization of a plurality of pieces of eMMC by the CPU, so that the CPU can obtain the identity information of each piece of eMMC initialized by the CPU, and on the other hand, the FPGA-based eMMC initialization device is used for realizing the initialization of the eMMC, so that the resource consumption is lower.

Furthermore, an interface with parameterized configuration is provided, and the requirement of users on different eMMC quantities can be met by adjusting the module.

Example 2

An embc control apparatus 200 based on an FPGA according to an embodiment of the present invention bridges at least two pieces of initialized target emmcs in parallel, as shown in fig. 2, the apparatus includes:

a third receiving module 201, configured to receive a target instruction sent by the CPU, where the target instruction includes identification information of a target instruction object eMMC, and the target instruction object eMMC is a piece of target eMMC in the target eMMC that has completed initialization;

a third sending module 202, configured to send the target instruction to each target eMMC that has completed initialization in parallel.

The FPGA-based eMMC control device in the first embodiment of the present invention is connected to the CPU and the at least two emmcs, respectively, and the eMMC is initialized by using the FPGA-based eMMC initialization device in the first embodiment. When the FPGA-based eMMC control device is respectively connected with the CPU and the at least two eMMC, the FPGA-based at least two eMMC parallel bridging CPUs can be realized.

In some embodiments, the third sending module sends the target instruction to each initialized target eMMC including the target instruction object eMMC currently bridged in parallel with the CPU, and although the non-target instruction object eMMC also receives the target instruction, since the identification information in the target instruction does not conform to the non-target instruction object eMMC, the non-target instruction object eMMC does not respond to the target instruction, and only the target instruction object eMMC conforming to the identification information responds to the target instruction.

In some embodiments, a target instruction sent by the CPU includes only identification information of a target instruction object eMMC.

In some embodiments, referring to fig. 2, the FPGA-based eMMC initialization apparatus further includes a second determination module 203;

the second judging module 203 is used for judging whether a target instruction object eMMC needs to send a response target instruction or not for the target instruction;

and/or the presence of a gas in the gas,

for determining whether the target instruction is legal.

It should be noted that the target instruction includes, but is not limited to, a processing instruction to the protocol state machine, including, but not limited to: a bus reset instruction, a standby state instruction, a command state instruction, a data transfer state instruction, an erase state instruction, etc.

In some embodiments, when the target instruction includes an erase state instruction, the second determining module is further configured to excite the eMMC corresponding to the target instruction to enter an erase state.

With continued reference to fig. 2, in some embodiments, the FPGA-based eMMC initialization apparatus further includes a fourth receive module 204 and a fourth transmit module 205;

the fourth receiving module 204 is configured to receive a response target instruction sent by the target instruction object eMMC if the second determining module determines that the response target instruction needs to be sent for the target instruction target eMMC;

and the fourth sending module is used for sending the response target instruction to the CPU.

In some embodiments, the FPGA-based eMMC control device further includes a data processing module, the target instruction including a data transfer instruction;

the data processing module is used for performing first processing operation on data in a data transmission instruction after receiving the data transmission instruction sent by the CPU and before sending the data transmission instruction to a target instruction object eMMC.

It should be noted that the first processing operation includes, but is not limited to, encryption of data, compression of data, and the like.

It should be noted that the data processing module may be built in the FPGA or may be set at the user side, and after the user processes the data, the data is sent to the corresponding target instruction object eMMC through the eMMC control device based on the FPGA.

In some embodiments, the data processing module is further configured to perform a second processing operation on data in the response target instruction after receiving the response target instruction sent by the target instruction object eMMC and before sending the response target instruction to the CPU.

It should be noted that the second processing operation corresponds to the first processing operation, and the second processing operation includes, but is not limited to: decryption, data decompression, etc.

In some embodiments, the FPGA-based eMMC control device further includes at least one of: the device comprises a checking module and a time sequence control module;

the verification module is used for at least one of the following: judging whether the target instruction received by the third receiving module is legal or not and judging whether the response target instruction received by the fourth receiving module is legal or not;

In some embodiments, the check module is further configured to determine a type of the corresponding target instruction.

It should be noted that, in some embodiments, when the timing control module is used to control the third sending module and the fourth sending module, the timing control module calculates the CRC while sending, and splices the CRC result into the response timing specified by the protocol.

It should be noted that, when the verification module exists, the verification module may send the target instruction to the target instruction object eMMC or send the response target instruction to the CPU only when determining that the target instruction is legal or the response target instruction is legal.

In some embodiments, the third receiving module includes a third data receiving module and a third command receiving module, where the third data receiving module is configured to receive a data transmission instruction sent by the CPU, and the third command receiving module is configured to receive a command instruction sent by the CPU.

In some embodiments, the third sending module includes a third command sending module and a third command sending module, where the third data sending module is configured to send a data transmission instruction sent by the CPU to the target instruction object eMMC; and the third command sending module is used for sending the command instruction sent by the CPU to the target command object eMMC.

In some embodiments, the fourth receiving module includes a fourth data receiving module and a fourth command receiving module, where the fourth data receiving module is configured to receive a data transmission response instruction sent by the target instruction object eMMC, and the fourth command receiving module is configured to receive a command response instruction sent by the target instruction object eMMC.

In some embodiments, the fourth sending module includes a fourth data sending module and a fourth command sending module, where the fourth data sending module is configured to send the data transmission response instruction sent by the target instruction object eMMC to the CPU; and the fourth command sending module is used for sending the command response command sent by the target command object eMMC to the CPU.

In some embodiments, the FPGA-based eMMC control apparatus according to the embodiments of the present invention implements a scheme for interfacing multiple eMMC devices of an eMMC5.1 protocol with a CPU, where the scheme includes eMMC protocol processing, data reading, data verification, data uploading, and data read-write processing of different eMMC devices by the CPU. When the eMMC is connected with 2 pieces in parallel, the resource consumption LUT of the FPGA is about 1.8k, and the highest clock frequency reported by time sequence analysis exceeds 229 MHz; the data is sampled by adopting two clock edges, and can reach HS400 DDR according to a protocol; the practical test result of the upper plate meets the system performance requirement.

The embodiment of the invention provides an eMMC control device based on an FPGA, and the target instruction sent by a CPU is received through a third receiving module, comprises the identification information of a target instruction object eMMC, and is sent to the target instruction object eMMC. The target instruction of the CPU can be quickly transmitted to the corresponding target instruction object eMMC through the eMMC control device based on the FPGA, the parallel processing and pipeline technology is adopted, the requirement of quick data interaction is met, and meanwhile balance is achieved between FPGA resource consumption and data reading rate. In addition, in the embodiment of the invention, the specifications of the FPGA such as a specific manufacturer are not limited, and the transplanting is convenient.

Furthermore, the eMMC control device based on the FPGA further comprises a data processing module, wherein the data processing module is used for carrying out first processing operation on data in the data transmission instruction and carrying out second processing operation on the data in the response target instruction, FPGA hardware resources are fully utilized, parallel processing and pipeline technology are adopted, the requirements of the current CPU and eMMC on the data processing speed are met, such as data encryption, data compression and the like, and the optimization of performance and resources is achieved.

Example 3

The following further specifically describes, by a specific embodiment, the FPGA-based eMMC initialization apparatus and the FPGA-based eMMC control apparatus provided by the present invention, referring to fig. 3-1, fig. 3-1 is a system block diagram of an eMMC parallel Bridge CPU, as shown in fig. 3-1, the system includes a Host controller composed of a CPU, a Device controller composed of at least two emmcs, and an FPGA-based eMMC control apparatus, referring to the eMMC-Bridge in the figure, where the Host controller and the Device controller implement eMMC5.1 protocol functions, the FPGA-based eMMC control apparatus implements CPU Host data read-write caching and processing, and a connection relationship between the modules may be referred to fig. 3-1. The FPGA-based eMMC control device further comprises a Data processing module, namely a User _ Data _ Pro module in the figure 3-1.

In some embodiments, the FPGA chip employs the PGL22G and is primarily responsible for processing of the eMMC interface protocol, including receiving and processing CPU commands and making responses, eMMC data reading, CRC checking of data, distributing data to different eMMC devices, and processing of reading and writing CPU and eMMC data.

The CPU is in butt joint with the FPGA and is mainly responsible for issuing eMMC protocol commands, including power-on initialization commands, data read-write commands and the like.

As shown in fig. 3-2, the eMMC _ Bridge module in the FPGA of fig. 3-1 is connected, and referring to fig. 3-2, the eMMC _ Bridge module mainly includes 6 modules: 1. an eMMC _ fsm module; 2. a CMD _ Ctrl module; 3. a Data _ Ctrl block; 4. a Register module; 5. a parallelr _ Ctrl module; 6. a tri _ ctrl module, 7 and a User _ Data _ Pro module, wherein the functions of the modules are as follows:

1) eMMC _ fsm module

The eMMC _ fsm module is responsible for processing a protocol state machine and comprises a first judging module used for judging whether an eMMC initialization operation instruction is a legal command or not; and the second judgment module is used for judging whether the target command is legal and/or judging whether a response is returned to the target command and judging and controlling the response type. When the CPU issues an enter erase command, the module will cause the eMMC to enter the erase state. Wherein the target instructions include, but are not limited to, bus reset, standby state, command state, data transfer state, erase state, etc.

2) CMD _ Ctrl module

The CMD _ Ctrl module is responsible for controlling command receiving and command responding time sequences and comprises a time sequence control module, a Host _ CMD _ Ctrl module and a Device _ CMD _ Ctrl module, wherein the Host _ CMD _ Ctrl module comprises a third command sending module and a fourth command receiving module, and the Device _ CMD _ Ctrl module comprises a third command instruction receiving module and a fourth command sending module. The CMD _ Ctrl module comprises an idle state, a command receiving state, a response waiting state, a response state and a response splicing CRC state. When receiving a command instruction, the module controls a receiving time sequence and carries out CRC (cyclic redundancy check) on the received command instruction to judge whether an error occurs in the command transmission process; after receiving the command response instruction and before sending the command response instruction to the CPU, a time sequence control module in the module controls the response time sequence, calculates CRC while sending, and splices the CRC result into the response time sequence specified by the protocol.

3) Data _ Ctrl module

The Data _ Ctrl module is responsible for controlling the Data receiving and Data sending time sequences, and comprises an idle state, a Data receiving state, a response waiting state, a response state and a response splicing CRC state. The module comprises a Host _ Data _ Ctrl module, a Device _ Data _ Ctrl module, and a timing control module, wherein the Host _ Data _ Ctrl module comprises a third Data transmission module and a fourth Data reception module, and the Device _ Data _ Ctrl module comprises a third Data reception module and a fourth Data transmission module. When receiving data, a time sequence control module in the module controls a receiving time sequence and carries out CRC check on a received command to judge whether errors occur in the command transmission process; when data is responded, the time sequence control module in the module controls the response time sequence, calculates CRC while sending, and splices the CRC result into the response time sequence specified by the protocol.

4) Register module

The Register module is also an identification module, and is mainly used for reading and writing a state Register, and the module identifies when the CPU issues a command.

5) Parallelr _ Ctrl module

The paralleler _ Ctrl module, that is, the parallel control module, is mainly used for eMMC device initialization and data distribution processing, and for parallel processing of eMMC responses.

6) Tri _ ctrl module

the tri _ ctrl module comprises a Device _ tri _ ctrl module and a Host _ tri _ ctrl module, wherein the Device _ tri _ ctrl module comprises a first receiving module, a second sending module, a third receiving module and a fourth sending module; the Host _ tri _ ctrl module comprises a first sending module, a second receiving module, a third sending module and a fourth receiving module, is mainly used for controlling the IO of the FPGA device, and is very friendly to platform transplantation and the addition of the eMMC device.

7) User _ Data _ Pro module

The User _ Data _ Pro module is also a Data processing module, and the module is used for Data processing and can carry out operations such as Data encryption and decryption and the like according to needs.

By providing the FPGA-based multi-eMMC bridge CPU implementation device and adopting parallel processing and pipeline technology, the requirement for rapid data interaction is met; meanwhile, the balance between FPGA resource consumption and data reading rate is achieved, a parameterized configuration interface is provided, and the application requirements of data interaction under different eMMC quantities of customers are met.

Example 4

When the FPGA-based eMMC initialization apparatus described in embodiment 1 is used, a flow of the FPGA-based eMMC initialization method according to an embodiment of the present invention is shown in fig. 4, where the method specifically includes the following steps:

s401: the CPU sends an eMMC initialization operation instruction;

s402: receiving an eMMC initialization operation instruction sent by a CPU;

s403: whether a target eMMC is determined, if yes, S404 is executed;

s404: sending an eMMC initialization operation instruction to a target eMMC;

s405: receiving an initialization response message of a target eMMC aiming at an eMMC initialization operation instruction;

s406: the initialization response message is sent to the CPU.

The target eMMC is an eMMC that has not been initialized, and if it is determined that the target eMMC is not reached, the flow is terminated.

Note that the initialization response message includes identification information of the target eMMC.

In some embodiments, the FPGA-based eMMC initialization method is applied to an FPGA-based eMMC initialization device that is connected to a CPU and at least one eMMC, respectively, wherein when the number of emmcs is greater than or equal to 2, each eMMC is connected in parallel to the FPGA-based eMMC initialization device.

In some embodiments, after the receiving, at S402, the eMMC initialization operation instruction sent by the CPU, and before the sending, at S404, the eMMC initialization operation instruction to the target eMMC, the method further includes:

identifying an eMMC initialization operation instruction;

and judging whether the eMMC initialization operation instruction is a legal instruction or not.

In some embodiments, the FPGA-based eMMC initialization apparatus bridges at least two emmcs in parallel, the FPGA-based eMMC initialization method further comprising:

determining a number of eMMC's to which an FPGA-based eMMC initialization apparatus is to be bridged in parallel

And/or the presence of a gas in the gas,

and determining the total quantity of the determined target eMMC in an accumulated mode within a preset period.

It should be noted that the preset period includes a period from a first eMMC initialization operation instruction to a last eMMC initialization operation instruction, which are continuously sent by the CPU.

The embodiment of the invention provides an eMMC initialization method based on FPGA, which comprises the steps of determining a target eMMC by receiving an eMMC initialization operation instruction sent by a CPU, sending the eMMC initialization operation instruction to the target eMMC, receiving an initialization response message of the target eMMC according to the eMMC initialization operation instruction, and sending the initialization response message to the CPU. Thus, when the parallel control module determines a target eMMC, the eMMC initialization operation instruction sent by the sub-CPU is only sent to the target eMMC, and the received initialization response message also only includes the identification information of the target eMMC. When the N pieces of eMMC exist, only the eMMC initialization operation instruction needs to be sent to the determined piece of eMMC each time, and the identity identification information of the N pieces of eMMC is respectively sent to the CPU by receiving the eMMC initialization operation instruction sent by the CPU for N +1 times and correspondingly sending initialization response information to the CPU for N times. By utilizing the eMMC initialization method based on the FPGA provided by the embodiment of the invention, the resource consumption is smaller, and meanwhile, a parameterized configuration interface is provided to meet the requirements of users on different eMMC quantities.

Example 5

When the FPGA-based eMMC control device described in embodiment 2 is used, a flow of the FPGA-based eMMC control method according to the embodiment of the present invention is shown in fig. 5, where the method specifically includes the following steps:

s501: receiving a target instruction sent by a CPU;

s502: sending the target instruction to each initialized target eMMC including a target instruction object eMMC in parallel;

s503: judging whether a response target instruction needs to be sent aiming at a target instruction target eMMC, if so, executing S504;

s504: receiving a response target instruction sent by a target instruction object eMMC;

s505: the response target instruction is sent to the CPU.

It should be noted that the target instruction includes identification information of a target instruction object eMMC, and the target instruction object eMMC is one piece of target eMMC in the target eMMC whose initialization has been completed.

If the response target instruction does not need to be transmitted, the flow ends.

In some embodiments, the FPGA-based eMMC control method according to the present invention is applied to an FPGA-based eMMC control device, and the FPGA-based eMMC control device is respectively connected in parallel with a CPU and at least two pieces of initialized target eMMC, and the target eMMC is initialized by using the FPGA-based eMMC initialization method according to embodiment 4. When the FPGA-based eMMC control device is respectively connected with the CPU and the at least two eMMC, the FPGA-based at least two eMMC parallel bridging CPUs can be realized.

In some embodiments, if the target instruction includes a data transfer instruction, after receiving the data transfer instruction sent by the CPU, before sending the data transfer instruction to the target instruction object eMMC, the method further includes:

and carrying out first processing operation on the data in the data transmission instruction.

In some embodiments, if the response target instruction is a response message of the data transfer instruction, after receiving the response target instruction sent by the target instruction object eMMC, before sending the response target instruction to the CPU, the method further includes:

and performing a second processing operation on the data in the response target instruction.

It should be noted that the first processing operation and the second processing operation may be corresponding processing operations, such as encryption, decryption, compression, decompression, and the like.

In some embodiments, before receiving the target instruction sent by the CPU, the method further includes:

controlling the receiving timing of the target instruction.

In some embodiments, after receiving the target instruction sent by the CPU and before sending the target instruction to the target instruction object eMMC, the method further includes:

and judging the legality of the target instruction.

In some embodiments, before sending the target instruction to the target instruction object eMMC, the method further includes:

controlling the transmission timing of the target instruction.

In some embodiments, before receiving the response target instruction sent by the target instruction object eMMC, the method further includes:

the reception timing of the response target instruction is controlled.

In some embodiments, after receiving the response target instruction sent by the target instruction object eMMC and before sending the response target instruction to the CPU, the method further includes:

and judging the validity of the response target instruction.

In some embodiments, before sending the response target instruction to the CPU, the method further includes:

the transmission timing of the response target instruction is controlled.

The embodiment of the invention provides an FPGA-based eMMC control method, which is characterized in that a target instruction sent by a CPU is received, the target instruction comprises identification information of a target instruction object eMMC, and the target instruction is sent to each initialized target eMMC including the target instruction object eMMC. And only the target instruction object eMMC responds to the target instruction. The target instruction of the CPU can be quickly transmitted to the corresponding target instruction object eMMC, the parallel processing and pipeline technology is adopted, the requirement of quick data interaction is met, and meanwhile balance between FPGA resource consumption and data reading rate is achieved. In addition, in the embodiment of the invention, the specifications of the FPGA such as a specific manufacturer are not limited, and the transplanting is convenient.

Furthermore, the FPGA-based eMMC control method further comprises the steps of carrying out first processing operation on data in the data transmission instruction and carrying out second processing operation on the data in the response target instruction, fully utilizing FPGA hardware resources, adopting parallel processing and pipeline technology, meeting the requirements of the current CPU and eMMC on data processing speed, such as data encryption, data compression and the like, and achieving optimization of performance and resources.

Example 6

An embodiment of the present invention further provides a terminal, as shown in fig. 6, the terminal 600 includes a CPU, at least two target emmcs, and an FPGA, where one end of the FPGA is connected to the CPU, and the other end of the FPGA is in parallel bridge connection with each target eMMC: the FPGA comprises

The FPGA-based eMMC initialization apparatus 601 as described in the first embodiment above,

and/or the presence of a gas in the gas,

the FPGA-based eMMC control device 602 described in embodiment two above.

Example 7

Embodiments of the present invention also provide a computer-readable storage medium including volatile or non-volatile, removable or non-removable media implemented in any method or technology for storage of information such as computer-readable instructions, data structures, computer program modules or other data. Computer-readable storage media include, but are not limited to, RAM (Random Access Memory), ROM (Read-Only Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), flash Memory or other Memory technology, CD-ROM (Compact disk Read-Only Memory), Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer.

The computer-readable storage medium in this embodiment may be configured to store one or more first computer programs, where the one or more first computer programs stored therein may be executed by the first processor to implement at least one step of the FPGA-based eMMC initialization method in embodiment 4 above;

or the like, or, alternatively,

the computer-readable storage medium in this embodiment may be configured to store one or more second computer programs, where the one or more second computer programs stored therein may be executed by the second processor to implement at least one step of the FPGA-based eMMC control method in embodiment 5 above;

the present embodiment also provides a computer program (or computer software), which can be distributed on a computer-readable medium and executed by a computing device to implement at least one step of the event processing method in the foregoing embodiments; and in some cases at least one of the steps shown or described may be performed in an order different than that described in the embodiments above.

It should be understood that in some cases, at least one of the steps shown or described may be performed in a different order than described in the embodiments above.

The present embodiments also provide a computer program product comprising a computer readable means on which a computer program as shown above is stored. The computer readable means in this embodiment may include a computer readable storage medium as shown above.

It will be apparent to those skilled in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software (which may be implemented in computer program code executable by a computing device), firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit.

In addition, communication media typically embodies computer readable instructions, data structures, computer program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to one of ordinary skill in the art. Thus, the present invention is not limited to any specific combination of hardware and software.

The foregoing is a more detailed description of embodiments of the present invention, and the present invention is not to be considered limited to such descriptions. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, and the scope of the invention should not be limited to the embodiments described above.

Claims

1. The utility model provides an eMMC controlling means based on FPGA which characterized in that, eMMC controlling means based on FPGA bridges at least two target eMMC that have accomplished initialization in parallel, eMMC controlling means based on FPGA includes:

2. The FPGA-based eMMC control device of claim 4, further comprising a second determination module;

the second judging module is used for judging whether the target instruction object eMMC needs to send a response target instruction or not aiming at the target instruction;

and/or the presence of a gas in the gas,

3. The FPGA-based eMMC control apparatus of claim 5, further comprising a fourth receive module and a fourth transmit module;

the fourth receiving module is configured to receive a response target instruction sent by the target instruction object eMMC if the second determining module determines that the target instruction object eMMC needs to send a response target instruction for the target instruction;

4. The FPGA-based eMMC control device of claim 6, further comprising a data processing module, the target instruction comprising a data transfer instruction;

the data processing module is configured to perform a first processing operation on data in a data transmission instruction after receiving the data transmission instruction sent by the CPU and before sending the data transmission instruction to the target instruction object eMMC.

5. The FPGA-based eMMC control device of claim 7,

the data processing module is further configured to perform a second processing operation on data in the response target instruction after receiving the response target instruction sent by the target instruction object eMMC and before sending the response target instruction to the CPU.

6. The FPGA-based eMMC control device of claim 6, further comprising at least one of: the device comprises a checking module and a time sequence control module;

7. An FPGA-based eMMC initialization device, characterized in that, the FPGA-based eMMC initialization device includes:

8. The FPGA-based eMMC initialization apparatus of claim 1, further comprising:

9. The FPGA-based eMMC initialization apparatus of claim 1, wherein the FPGA-based eMMC initialization apparatus bridges at least two emmcs in parallel, the FPGA-based eMMC initialization apparatus further comprising:

and/or the presence of a gas in the gas,

10. An FPGA-based eMMC control method applied to the FPGA-based eMMC control apparatus according to any one of claims 1 to 6, comprising:

sending the target instruction to each initialized target eMMC in parallel;

and sending the response target instruction to the CPU.

11. A terminal, comprising a CPU, at least two target emmcs, and an FPGA, one end of the FPGA being connected to the CPU and the other end of the FPGA being bridged in parallel with each of the target emmcs, the FPGA comprising an FPGA-based eMMC control apparatus as claimed in any one of claims 1 to 6 and/or an FPGA-based eMMC initialization apparatus as claimed in any one of claims 7 to 9.