CN111182276A - Multi-path high-speed serial port transparent transmission optical transceiver and equipment based on FPGA - Google Patents
Multi-path high-speed serial port transparent transmission optical transceiver and equipment based on FPGA Download PDFInfo
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- CN111182276A CN111182276A CN201811329658.1A CN201811329658A CN111182276A CN 111182276 A CN111182276 A CN 111182276A CN 201811329658 A CN201811329658 A CN 201811329658A CN 111182276 A CN111182276 A CN 111182276A
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04N7/00—Television systems
- H04N7/22—Adaptations for optical transmission
Abstract
The embodiment of the invention provides a multi-channel high-speed serial port transparent transmission optical transceiver and equipment based on an FPGA (field programmable gate array), which utilize the characteristics of high bandwidth and low time delay of optical communication and reasonably configure an FPGA chip to obtain the serial port transmission optical transceiver with ultra-low time delay, multi-channel parallelism and customizable capacity.
Description
Technical Field
The invention relates to the technical field of digital signal remote transmission, in particular to a multi-channel high-speed serial port transparent transmission optical transceiver and equipment based on an FPGA (field programmable gate array).
Background
The 422/232 serial port is a transmission protocol which is widely applied at present, has the characteristics of simple and convenient application, high reliability and the like, but is limited by the impedance limit of a connecting wire, the transmission distance is generally within 40 meters, and the requirement of long-distance transmission cannot be met.
The optical fiber transmission has the advantages of good confidentiality, strong anti-interference performance, high transmission rate, large capacity and the like, and the 422/232 serial port is converted into an optical signal, so that the optical fiber transmission is an ideal solution for realizing long-distance transmission. However, in the existing 422/232 serial port conversion optical fiber conversion equipment, serial port information needs to be analyzed into data according to a set baud rate, then the data is transmitted to a far end and is restored into the serial port information, the two processes can cause great delay to signal transmission, and meanwhile, the communication baud rate needs to be set in the use process, so that the use difficulty is increased. In addition, a single optical fiber can only transmit serial port information of 1 to 2 paths, and the bandwidth of the optical fiber is greatly wasted.
Therefore, it is urgently needed to develop a serial optical transceiver with multiple channels and ultra-low latency, which can automatically adapt to multiple communication rates, and simultaneously, the hardware platforms of the transmitting end and the receiving end of the optical transceiver can be used universally through reasonable hardware design.
Disclosure of Invention
In view of this, the embodiment of the present invention provides a multi-channel high-speed serial port transparent transmission optical transceiver and device based on an FPGA.
In a first aspect, the invention provides a multi-path high-speed serial port transparent transmission optical transceiver based on FPGA, which comprises an FPGA chip, a serial interface module and a photoelectric conversion module, the FPGA chip is respectively and electrically connected with the serial interface module and the photoelectric conversion module, the FPGA chip comprises an interface driving module for receiving high-speed serial port information and driving the serial interface module, and a high-speed serial data stream for converting multi-path parallel serial port level information into one path of high-speed serial data stream, meanwhile, the high-speed serial data stream transmitted by the other end is analyzed into a high-speed serial driving module of multi-path parallel serial port level information and a clock management module used for clock management in the FPGA and system synchronous reset function, the interface driving module is respectively electrically connected with the serial interface module and the high-speed serial driving module, the high-speed serial driving module is electrically connected with the clock management module and the photoelectric conversion module respectively.
As an optional scheme, the FPGA chip further includes an indication signal control module, which is used for controlling a signal lamp of the optical transceiver, indicating the on-off state of the current system, and whether serial port information exists, and the indication signal control module is electrically connected with the high-speed serial driving module.
As an optional scheme, the system further comprises a GTP high-speed serial interface, the high-speed serial driving module comprises a GTP high-speed serial interface driver, the clock management module is electrically connected to the GTP high-speed serial interface driver, and the interface driving module is electrically connected to the GTP high-speed serial interface driver.
As an optional scheme, the photoelectric conversion module includes an optical fiber connection base, an SFP optical module, and an electromagnetic shielding cage, where the optical fiber connection base and the SF optical module are located in the electromagnetic shielding cage.
As an optional scheme, the mobile terminal further comprises a FLASH memory chip for storing a system binary program file, wherein the FLASH memory chip is electrically connected with the GTP high-speed serial interface driver.
As an optional scheme, the clock management module further comprises an external clock for providing a reference clock for the clock management module, and the external clock is electrically connected with the clock management module.
As an optional solution, the serial interface module includes an MDR50 socket, a 422 interface chip, a 232 interface chip, and an interface protection chip, and the MDR50 socket is electrically connected to the 422 interface chip and the 232 interface chip, respectively.
As an optional scheme, the device further comprises an LED signal indicator light, and the LED signal indicator light is electrically connected with the GTP high-speed serial interface drive.
As an optional scheme, the multi-path high-speed serial port transparent transmission optical transceiver based on the FPGA is a receiving end or a sending end.
In a second aspect, the invention provides a multi-path high-speed serial port transparent transmission device based on an FPGA, which comprises a receiving end and a sending end, wherein the receiving end and the sending end both adopt the multi-path high-speed serial port transparent transmission optical transceiver based on the FPGA.
According to the technical scheme, the embodiment of the invention has the following advantages:
the embodiment of the invention provides a multi-channel high-speed serial port transparent transmission optical transceiver and equipment based on an FPGA (field programmable gate array), which utilize the characteristics of high bandwidth and low time delay of optical communication and reasonably configure an FPGA chip to obtain the serial port transmission optical transceiver with ultra-low time delay, multi-channel parallelism and customizable capacity.
Drawings
Fig. 1 is a structural block diagram of an embodiment of a multi-path high-speed serial port transparent transmission optical transceiver based on an FPGA according to the present invention;
fig. 2 is a block diagram of a structure of an embodiment of the multi-path high-speed serial port transparent transmission optical transceiver based on the FPGA as a transmitting end according to the present invention;
fig. 3 is a block diagram of a structure of another embodiment of the multi-path high-speed serial port transparent transmission optical transceiver based on the FPGA according to the present invention;
fig. 4 is a structural block diagram of an embodiment of the multi-path high-speed serial port transparent transmission optical transceiver based on the FPGA as a receiving end according to the present invention.
Reference numerals: the device comprises a sending end 1, a receiving end 2, a serial interface module 3, a 422 interface chip 31, a 232 interface chip 32, an MDR50 socket 33, an FPGA chip 4, an interface driving module 41, a high-speed serial driving module 42, a GTP high-speed serial interface driver 421, a clock management module 43, a GTP high-speed serial interface 44, a photoelectric conversion module 5, a FLASH memory chip 6, an external clock 7 and an LED signal indicator light 8.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, the present invention provides a multi-channel high-speed serial port transparent transmission optical transceiver based on FPGA, which includes an FPGA chip 4, a serial interface module 3, and a photoelectric conversion module 5, wherein the FPGA chip 4 is electrically connected to the serial interface module 3 and the photoelectric conversion module 5, the FPGA chip 4 includes an interface driving module 41 for receiving high-speed serial port information and driving the serial interface module 3, a high-speed serial driving module 42 for converting multi-channel parallel serial port level information into a single-channel high-speed serial data stream and analyzing the high-speed serial data stream transmitted at the other end into multi-channel parallel serial port level information, and a clock management module 43 for clock management and system synchronization reset functions inside the FPGA, the interface driving module 41 is electrically connected to the serial interface module 3 and the high-speed serial driving module 42, the high-speed serial driving module 42 is electrically connected with the clock management module 43 and the photoelectric conversion module 5 respectively, and by utilizing the characteristics of high bandwidth and low time delay of optical communication and reasonably configuring an FPGA chip, a serial port transmission optical transceiver with ultralow time delay, multipath parallelism and customizable capacity is obtained.
In this embodiment, the FPGA chip 4 further includes an indication signal control module, which is used for controlling a signal lamp of the optical transceiver, indicating the on-off state of the current system, and indicating whether serial port information exists, and the indication signal control module is electrically connected to the high-speed serial driving module 42.
In this embodiment, the apparatus further includes a GTP high-speed serial interface 44, the high-speed serial driving module 42 includes a GTP high-speed serial interface driver 421, the clock management module 43 is electrically connected to the GTP high-speed serial interface driver 421, and the interface driving module 41 is electrically connected to the GTP high-speed serial interface 44.
In this embodiment, the photoelectric conversion module 5 includes an optical fiber connection base, an SFP optical module, and an electromagnetic shielding cage, where the optical fiber connection base and the SF optical module are located in the electromagnetic shielding cage, the SFP optical module converts a high-speed serial data stream into a binary optical signal, and simultaneously restores the received optical signal into a serial data stream, and the SFP optical module is directly driven by using a GTP high-speed serial interface 44 inside the FPGA, so that the number of chips used in the optical transceiver is reduced, the size is reduced, the system complexity is reduced, and the reliability is improved. Meanwhile, the transmission delay of the whole system is controlled within 100ns by using high-speed clock sampling, in the embodiment, the SFP optical module selects a 2.5G bandwidth module, and the communication wavelength is 1310nm/1270 nm.
In this embodiment, the mobile terminal further includes a FLASH memory chip 6 for storing a system binary program file, and the FLASH memory chip 6 is electrically connected to the GTP high-speed serial interface driver 421.
In this embodiment, the serial port interface further includes an external clock 7 for providing a reference clock for the clock management module 43, where the external clock 7 is electrically connected to the clock management module 43, and serial port information is transmitted by a high-speed clock sampling mode, a highest bandwidth supported by a system interface chip is 31Mhz, a sampling rate at the FPGA end is 62.5Mhz, and a highest supported frequency of each serial port is 30Mhz according to nyquist sampling theorem. Through reasonable GTP high-speed serial-parallel conversion interface driving configuration, the delay of the whole transmission process can be lower than 100 ns. In addition, the GTP high-speed serial-parallel conversion interface driver can adaptively support simplex communication and duplex communication, and the optical fiber channels in each direction are independently synchronous. The synchronization code adopts a K28.5 protocol, the longest synchronization code of 2000 clock cycles is sent each time, and the receiving end 2 adopts a synchronization mode that P-type and N-type synchronization codes are received simultaneously. After the connection between the sending end 1 and the receiving end 2 is successfully established, the sending end 1 sends a connection check code according to a fixed frequency, and the receiving end 2 circularly detects the connection check code through a state machine, so that the condition abnormity can be detected within 1ms after the optical fiber is broken, the data output of a subsequent port is stopped, and the output of an error level signal is prevented.
In this embodiment, the serial interface module 3 includes an MDR50 socket, a 422 interface chip 31, an 232 interface chip 32, and an interface protection chip, and the MDR50 socket is electrically connected to the 422 interface chip 31 and the 232 interface chip 32, respectively.
In this embodiment, the system further comprises an LED signal indicator lamp 8, the LED signal indicator lamp 8 is electrically connected to the GTP high-speed serial interface driver 421, the high-speed serial interface driver controls the LED signal indicator lamp 8, the system completion state synchronization is indicated by the lighting of the lamp, and the received optical information is valid.
In this embodiment, the multi-path high-speed serial port transparent transmission optical transceiver based on the FPGA is the receiving end 2 or the sending end 1, and the hardware configurations of the receiving end 2 and the sending end 1 are completely the same, and both include two MDR50 sockets, an FPGA chip 4, a FLASH memory chip 6, a 422 interface chip 31, a 232 interface chip 32, an external clock 7, and an LED signal indicator light 8.
The invention utilizes the characteristics of high bandwidth and low time delay of light communication, and obtains the serial port transmission optical transmitter and receiver with ultra-low time delay, multipath parallelism and customizable capacity by reasonably configuring the FPGA chip 4. Meanwhile, through reasonable software and hardware design, the hardware design of the transmitting end 1 and the receiving end 2 of the optical transceiver is completely the same. Due to the design of the high-speed serial driving module 42, various working modes such as single-fiber duplex, double-fiber duplex, single-fiber simplex and the like can be realized by changing the configuration of the SFP optical module.
Referring to fig. 1, when the multi-channel high-speed serial port transparent transmission optical transceiver based on the FPGA provided in the embodiment of the present invention is used as a transmitting end 1, the optical transceiver includes an FPGA chip 4, a serial interface module 3, and a photoelectric conversion module 5. The FPGA chip 4 includes a high-speed serial driver module 42, an interface driver module 41, and a clock management module 43.
And the high-speed serial driving module 42 is used for driving a high-speed serial interface, establishing synchronous connection between the sending end 1 board card and the receiving end 2 board card, managing the connection state, and realizing the function of converting a multi-path parallel signal into a single-path serial signal under the condition of ensuring stable connection.
The interface driving module 41 enables or stops the input/output function of the interface chip according to the state of the high-speed serial driving module 42, simultaneously corresponds the input/output interface chip to the parallel signals in the FPGA chip 4 one by one according to the protocol, samples/restores the signals by using the high-speed clock, and exchanges data with the high-speed serial driving module 42 according to the agreed format.
The clock management module 43 receives a clock signal generated by an external crystal oscillator, converts the externally input clock signal into clock signals of different frequencies used by the internal module according to an internal convention, and is used for synchronization of a high-speed serial interface, sampling/restoration of the interface driving module 41, and the like. The clock management module 43 is also responsible for outputting a synchronous reset signal for the entire system.
The serial interface module 3 is mainly responsible for converting the 422/232 serial port level into a system internal level signal, and is provided with an input/output enabling control end.
The photoelectric conversion module 5 converts the high-speed serial binary electrical signals into binary optical signals through the SPF optical module, and then performs remote transmission through an optical fiber.
Referring to fig. 2, when the multi-channel high-speed serial port transparent transmission optical transceiver based on the FPGA is provided as the transmitting end 1 in the embodiment of the present invention, the transmitting end 11 further includes a FLASH memory chip 6, an external clock 7, and an LED signal indicator 8, where the FLASH memory chip 6 is used to store a system binary program file, and is used in cooperation with the FPGA chip 4 to ensure that a program automatically runs after the system is powered on, and in the embodiment, a W25Q64FV chip is used. The external clock 7 is responsible for providing a reference clock, in an embodiment 125MHz, for the clock management module 43, and the LED signal indicator 8 is used for indicating the on/off of the optical fiber and the working state of each module.
The serial interface module 3 mainly comprises an MDR50 socket, four 422 interface chips 31, a 232 interface chip 32 and 4 interface protection chips.
The photoelectric conversion module 5 mainly comprises an optical fiber connection base, an SFP optical module and an electromagnetic shielding cage, wherein the optical fiber connection base and the SF optical module are positioned in the electromagnetic shielding cage, and the optical fiber connection base is selected from UL74441 of Molex company.
The FPGA chip 4 adopts a Spartan6 series chip, preferably, a Spartan6-csg324 chip of Xilinx company is selected, the interior of the chip is designed by a Verilog HDL hardware description language, and the chip mainly comprises a high-speed serial driving module 42, an interface driving module 41 and a clock management module 43, wherein the high-speed serial driving module 42 also has the control function of the LED lamp.
The specific working process of the transmitting end 1 is as follows: after the system is powered on, the FPGA chip 4 automatically reads program information from the FLASH memory chip 6, the clock management module 43 starts to receive external clock 7 oscillation and generate an internal clock, after the internal clock is stable for 1s, the clock management module 43 generates a reset signal, and the whole system is synchronously reset to an initial state. The interface driving module 41 enables an external interface chip to start to acquire level information of the multiple parallel serial ports, and transmits the level information to the high-speed serial driving module 42 through an internal bus, and the high-speed serial driving module 42 circularly sends k28.5 synchronous codes and acquired parallel information according to a set frequency. The GTP high-speed serial interface 44 converts the information into a high-speed serial signal of 1.25Gbp through 8b/10b coding, and transmits the signal to the photoelectric conversion module 5. The SFP optical module in the photoelectric conversion module 5 converts the level signal into an optical signal, and transmits the optical signal to the SFP optical module of the receiving end 2, thereby implementing the remote transmission function of the multi-path parallel serial port.
Referring to fig. 3 and 4, when the multi-channel high-speed serial port transparent transmission optical transceiver based on the FPGA provided by the present invention is used as the receiving end 2, the receiving end 2 mainly includes a photoelectric conversion module 5, an FPGA chip 4, a serial interface module 3, a FLASH memory chip 6, an external clock 7 and an LED signal indicator light 8, and the working mode of the receiving end 2 is as follows: when the system is powered on, the FPGA chip 4 automatically loads programs from the FLASH memory chip 6, the clock management module 43 starts to receive the oscillation of the external clock 7 and generate an internal clock, after the internal clock is stable for 1s, the clock management module 43 generates a reset signal, and the whole system is synchronously reset to be in an initial state. The high-speed serial driving module 42 starts to receive the level signal converted by the photoelectric conversion module 5 according to the optical information after the reset is completed, extracts the synchronization code information from the serial level signal, completes the state synchronization after receiving enough synchronization code information, and starts to output the parallel information through the internal bus. The interface driving module 41 receives the parallel information and the state synchronization completion information, enables the serial interface module 3, and starts to output a plurality of parallel serial port levels externally according to the parallel information. The serial interface module 3 receives the parallel serial port level, restores the parallel serial port level to a serial port signal with 422/232 level standard through a special interface chip, and in addition, the high-speed serial driving module 42 also controls the LED signal indicator light 8, and the system completion state synchronization is shown through the light-on, so that the received optical information is effective.
The invention uses the FPGA core to replace the traditional high-speed serial-parallel conversion chip, realizes the transparent high-speed transmission of 10-path full-duplex 422 serial ports and 2-path full-duplex 232 serial ports within a smaller hardware size through reasonable software and hardware design, the delay time of each channel is within 100ns, and simultaneously the hardware design of a transmitting end and a receiving end is completely the same.
Correspondingly, the invention provides a multichannel high-speed serial port transparent transmission device based on the FPGA, which comprises a receiving end 2 and a sending end 1, wherein the receiving end 2 and the sending end 1 both adopt the multichannel high-speed serial port transparent transmission optical transceiver based on the FPGA.
Multichannel serial ports optical transmitter and receiver includes serial ports sending terminal 1 and serial ports receiving terminal 2, the two passes through optical fiber connection, the serial ports receiving terminal passes through interface chip, convert the serial ports into inside level signal, convert multichannel serial ports into high-speed serial signal of the same kind through FPGA, convert into light signal through photoelectric conversion module 5, light signal passes through optical fiber transmission to the serial ports receiving terminal, photoelectric conversion module 5 of receiving terminal restores the light signal into the signal of telecommunication, use FPGA to restore high-speed serial signal of the same kind into multichannel parallel signal, restore to the serial ports interface chip that corresponds through interface drive module 41, level signal conversion accords with 422/232 level standard through interface chip, thereby realize serial ports signal's reduction output.
The invention provides a multi-path high-speed serial port transparent transmission device based on an FPGA (field programmable gate array), which comprises a sending end and a receiving end, wherein hardware components at the two ends are completely the same, the device comprises an FPGA chip, a high-speed 422/232 interface module and a photoelectric conversion module, and the FPGA chip comprises an interface driving module, a high-speed serial signal driving module and a clock management module. The acquisition end converts the multi-channel serial port information into internal parallel data flow through a high-speed 422/232 interface module, and the internal parallel data flow is transmitted to a high-speed serial signal driving module after high-speed sampling and converted into serial information. The serial information is converted into an optical signal through the photoelectric conversion module and is sent to the reduction end, and the signal is reduced into a high-speed serial signal through the photoelectric conversion module at the reduction end. The high-speed serial signal driving module at the reduction end reduces the signals into parallel signals and outputs the parallel signals to the high-speed 422/232 interface module, so that remote transmission of the multi-path serial signals is realized.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by associated hardware instructed by a program, which may be stored in a computer-readable storage medium, and the storage medium may include: a Read Only Memory (ROM), a Random Access Memory (RAM), a magnetic or optical disk, or the like.
The above detailed description is provided for the multi-path high-speed serial port transparent transmission optical transceiver and the device based on the FPGA, and for those skilled in the art, according to the idea of the embodiment of the present invention, there may be changes in the specific implementation manner and the application scope.
Claims (10)
1. A multi-channel high-speed serial port transparent transmission optical transceiver based on FPGA is characterized by comprising an FPGA chip, a serial interface module and a photoelectric conversion module, the FPGA chip is respectively and electrically connected with the serial interface module and the photoelectric conversion module, the FPGA chip comprises an interface driving module for receiving high-speed serial port information and driving the serial interface module, a high-speed serial driving module for converting multi-path parallel serial port level information into a path of high-speed serial port flow and analyzing the high-speed serial port flow transmitted by the other end into multi-path parallel serial port level information, and a clock management module for clock management and system synchronous reset functions in the FPGA, the interface driving module is respectively electrically connected with the serial interface module and the high-speed serial driving module, the high-speed serial driving module is electrically connected with the clock management module and the photoelectric conversion module respectively.
2. The FPGA-based multi-path high-speed serial port transparent transmission optical transceiver of claim 1, wherein the FPGA chip further comprises an indication signal control module for controlling a signal lamp of the optical transceiver, indicating the on-off state of the current system and indicating whether serial port information exists, and the indication signal control module is electrically connected with the high-speed serial driving module.
3. The optical transceiver based on the multi-path high-speed serial port transparent transmission of the FPGA according to claim 2, further comprising a GTP high-speed serial interface, wherein the high-speed serial driving module comprises a GTP high-speed serial interface driver, the clock management module is electrically connected with the GTP high-speed serial interface driver, and the interface driving module is electrically connected with the GTP high-speed serial interface driver.
4. The FPGA-based multi-path high-speed serial port transparent transmission optical transceiver of claim 1, wherein the photoelectric conversion module comprises an optical fiber connection base, an SFP optical module and an electromagnetic shielding cage, and the optical fiber connection base and the SF optical module are located in the electromagnetic shielding cage.
5. The FPGA-based multi-channel high-speed serial port transparent transmission optical transceiver of claim 3, further comprising a FLASH memory chip for storing a system binary program file, wherein the FLASH memory chip is electrically connected with the GTP high-speed serial interface driver.
6. The FPGA-based multi-channel high-speed serial port transparent transmission optical transceiver of claim 1, further comprising an external clock for providing a reference clock for the clock management module, wherein the external clock is electrically connected to the clock management module.
7. The FPGA-based multi-path high-speed serial port transparent transmission optical transceiver of claim 1, wherein the serial interface module comprises an MDR50 socket, a 422 interface chip, a 232 interface chip and an interface protection chip, and the MDR50 socket is electrically connected with the 422 interface chip and the 232 interface chip respectively.
8. The FPGA-based multi-path high-speed serial port transparent transmission optical transceiver of claim 3, further comprising an LED signal indicator lamp electrically connected with the GTP high-speed serial interface driver.
9. The FPGA-based multi-path high-speed serial port transparent transmission optical transceiver of claim 1, which is a receiving end or a transmitting end.
10. A multi-path high-speed serial port transparent transmission device based on FPGA is characterized by comprising a receiving end and a transmitting end, wherein the receiving end and the transmitting end both adopt the multi-path high-speed serial port transparent transmission optical transceiver based on FPGA according to any one of claims 1 to 9.
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| CN201811329658.1A CN111182276A (en) | 2018-11-09 | 2018-11-09 | Multi-path high-speed serial port transparent transmission optical transceiver and equipment based on FPGA |
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Application publication date: 20200519 |
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| RJ01 | Rejection of invention patent application after publication |