CN111128872B - Contact hole and manufacturing method thereof - Google Patents
Contact hole and manufacturing method thereof Download PDFInfo
- Publication number
- CN111128872B CN111128872B CN201911392053.1A CN201911392053A CN111128872B CN 111128872 B CN111128872 B CN 111128872B CN 201911392053 A CN201911392053 A CN 201911392053A CN 111128872 B CN111128872 B CN 111128872B
- Authority
- CN
- China
- Prior art keywords
- thin film
- film layer
- contact
- layer
- conductive electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
The invention discloses a method for manufacturing a contact hole, which comprises the following steps: s01: providing a substrate, and forming a lower conductive electrode on the substrate; s02: depositing a first thin film layer on the lower conductive electrode, and etching a large contact hole penetrating through the first thin film layer on the first thin film layer; s03: depositing a second thin film layer on the first thin film layer and etching to enable the second thin film layer to form a gradual step on the side wall of the contact large hole; the opening area of the top of the gradual change step is larger than that of the bottom of the gradual change step; s04: depositing a functional layer, and forming a contact small hole penetrating through the functional layer at the bottom of the contact large hole; s05: and depositing an upper conductive electrode, wherein the upper conductive electrode is connected with the lower conductive electrode through the contact small hole. The contact hole and the manufacturing method thereof provided by the invention can ensure that the upper conductive electrode in the contact hole is not broken, so that the yield and the reliability of a device are improved.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuits, in particular to a contact hole and a manufacturing method thereof.
Background
In integrated circuit manufacturing, high aspect ratio holes/trenches are common structures, and how to controllably realize the patterning and filling of the holes/trenches is a key technology of each process node. As the process size continues to shrink, the problem becomes more and more prominent, and thus various advanced patterning and filling techniques are introduced. For the field of MEMS of branch micro-electromechanical systems of integrated circuits, the industry generally adopts the technology behind the advanced CMOS process for research, development and manufacture so as to meet the requirements of micron-scale manufacture and cost reduction.
In the MEMS manufacturing, how to realize reliable contact holes is also a key technology for preparing the devices. For the contact hole for supporting the microbridge/beam structure, in the prior art, as shown in fig. 1, an etching blocking layer 041 and a first thin film layer 042 may be deposited on a substrate 01 in sequence first, where the first thin film layer 42 may specifically be a supporting layer; then, a hole/groove is formed in the first thin film layer 042 by photolithography and etching, and finally, a layer of metal is deposited in the hole/groove to connect the lower conductive electrode 02, which is located in the insulating medium 3, and serve as the upper conductive electrode 09. As shown in fig. 2, since the thickness of the upper conductive electrode 09 is small, the angle of the hole/groove is steep, which causes the upper conductive material to be discontinuous or even broken in the hole/groove, thereby affecting the yield and reliability of the device.
Disclosure of Invention
The invention aims to provide a contact hole and a manufacturing method thereof, which can ensure that an upper conductive electrode in the contact hole is not broken so as to improve the yield and reliability of a device.
In order to achieve the purpose, the invention adopts the following technical scheme: a method for manufacturing a contact hole comprises the following steps:
s01: providing a substrate, and forming a lower conductive electrode on the substrate;
s02: depositing a first thin film layer on the lower conductive electrode, and etching a large contact hole penetrating through the first thin film layer on the first thin film layer;
s03: depositing a second thin film layer on the first thin film layer and etching to enable the second thin film layer to form a gradual step on the side wall of the contact large hole; the opening area of the top of the gradual change step is larger than that of the bottom of the gradual change step;
s04: depositing a functional layer, and forming a contact small hole penetrating through the functional layer at the bottom of the contact large hole;
s05: and depositing an upper conductive electrode, wherein the upper conductive electrode is connected with the lower conductive electrode through the contact small hole.
Further, the step S02 specifically includes: depositing an etching barrier layer and a first thin film layer on the lower conductive electrode, and etching a large contact hole penetrating through the first thin film layer on the first thin film layer;
the step S04 specifically includes: and forming a contact small hole penetrating through the functional layer and the etching barrier layer at the bottom of the contact large hole.
Further, in the step S02, the first thin film layer includes a dielectric material layer and/or an amorphous silicon layer.
Further, the thickness of the first thin film layer is larger than 500nm.
Further, the second thin film layer comprises an insulating medium layer, and the thickness of the second thin film layer is smaller than that of the first thin film layer.
Further, in the step S03, the second thin film layer is etched by dry etching.
Further, the step S03 specifically includes:
s031: depositing a second thin film layer on the first thin film layer;
s032: and removing the second thin film layer on the upper surface of the first thin film layer by adopting optical sheet dry etching, wherein the side wall of the contact macropore is a steep step, and the second thin film layer remained in the contact macropore forms a gradual step on the side wall of the contact macropore.
Further, the step S04 further includes: depositing a functional layer in the contact macropores and on the upper surface of the first thin film layer, and forming contact micropores penetrating through the functional layer at the bottoms of the contact macropores;
further, the functional layer comprises a dielectric layer and a functional material layer, and the dielectric layer and the functional material layer are sequentially deposited inside the contact macropores and on the upper surface of the first thin film layer in the step S04.
A contact hole comprises a substrate, a lower conductive electrode, an upper conductive electrode, a first thin film layer, a gradual step, a functional layer, a large contact hole and a small contact hole, wherein the lower conductive electrode is positioned above the substrate, the first thin film layer is positioned above the lower conductive electrode, the large contact hole is positioned in the first thin film layer and penetrates through the first thin film layer, the gradual step is positioned on the side wall of the large contact hole, and the top opening of the gradual step is larger than the bottom opening; the functional layer is located in the contact macropore and above the first thin film layer, the contact micropore is located at the bottom of the contact macropore and penetrates through the functional layer, and the upper conductive electrode is connected with the lower conductive electrode through the contact micropore.
The invention has the beneficial effects that: according to the invention, the contact macropore is formed firstly, and then the gradual step is formed in the contact macropore, so that the discontinuity and the fracture of the upper conductive electrode on the side wall of the contact macropore are avoided, and the yield and the reliability of the device are improved; the preparation method does not need to add a photomask and advanced hole filling equipment, has simple process and is compatible with a CMOS (complementary metal oxide semiconductor) process, and is favorable for reducing the cost.
Drawings
FIG. 1 is a schematic view of a hole/groove structure formed in the prior art;
FIG. 2 is a schematic illustration of a prior art upper conductive electrode in a via/trench configuration in electrolytic connection with a lower conductive electrode;
FIG. 3 is a flow chart of a method for forming contact holes in accordance with the present invention;
FIG. 4 is a schematic view of forming a lower conductive electrode on a substrate in example 1;
FIG. 5 is a schematic illustration of the formation of a contacting macropore in example 1;
FIG. 6 is a schematic view of forming a graded step in example 1;
FIG. 7 is a schematic illustration of the deposition of a functional layer in example 1;
FIG. 8 is a schematic view showing formation of a contact hole in example 1;
fig. 9 is a schematic view of a contact hole in embodiment 1.
In the figure: 01 substrate, 02 lower layer conductive electrode, 03 insulating medium, 04 contact macropore, 05 gradual change step, 06 dielectric layer, 07 functional material layer, 08 contact pinhole, 09 upper electrode conductive electrode, 041 etching barrier layer and 042 first thin film layer.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in detail below with reference to the accompanying drawings. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
As shown in fig. 3, the method for fabricating a contact hole provided by the present invention comprises the following steps:
s01: a substrate is provided, and an underlying conductive electrode is formed on the substrate.
Specifically, a substrate is provided, the substrate can be a silicon wafer, the substrate can already complete the manufacture of a required processing circuit, and then the manufacture of a contact hole is started, namely a CMOS control circuit is already manufactured in the substrate. Specifically, an insulating medium can be deposited on the substrate, the insulating medium is patterned, and the patterned area is filled with the lower conductive electrode; the lower conductive electrode may be made of various conductive materials such as copper, aluminum, titanium nitride, tantalum nitride, polysilicon, and the like.
S02: and depositing a first thin film layer on the lower conductive electrode, and etching a large contact hole penetrating through the first thin film layer on the first thin film layer.
Specifically, an etching barrier layer can be deposited on the lower conductive electrode and the insulating medium to serve as an etching stop layer when the contact macropore is etched subsequently.
And depositing a first thin film layer on the etching barrier layer, wherein the material of the first thin film layer can be a dielectric material or amorphous silicon, or a combination of more than two of the dielectric material and the amorphous silicon, and the thickness of the first thin film layer is set to be more than 500nm. Patterning the first thin film layer by adopting conventional photoetching and etching processes, and forming a contact large hole penetrating through the first thin film layer by taking the etching barrier layer as a stop layer, wherein the depth of the contact large hole is the same as the thickness of the first thin film layer; and the angle of the formed large hole 04 of the contact hole is larger than 80 degrees, namely the contact hole is contacted with the side wall of the steep step formed in the large hole.
S03: depositing a second thin film layer on the first thin film layer and etching to form a gradual step on the side wall of the second thin film layer contacting the large hole; and the top opening area of the gradual change step is larger than the bottom opening area.
The method specifically comprises the following steps: s031: depositing a second thin film layer on the upper surface of the first thin film layer and in the contact macropore by adopting a global process, wherein the second thin film layer can be an insulating medium layer, and can be a silicon dioxide layer and the like; and the thickness of the second thin film layer is smaller than that of the first thin film layer, so that a gradual step is formed inside the large contact hole.
S032: and then, removing the second thin film layer on the upper surface of the first thin film layer by adopting a light sheet dry etching method, wherein the contact macropore has a steep step at the moment, and a part of the second thin film layer left in the contact macropore forms a gradual step on the side wall of the contact macropore when the second thin film layer on the surface is etched. Because the second film layer adopts the global deposition process, the formed gradual step is positioned on the side wall of the contact macro pore, and the opening area of the top of the gradual step is larger than that of the bottom. It is worth mentioning that: in the invention, when the second thin film layer on the upper surface of the first thin film layer is removed, the second thin film layer contacting the bottom of the large hole is removed by adopting the same dry etching method, and because the etching rate of the second thin film contacting the bottom of the large hole is close to that of the second thin film on the upper surface of the first thin film layer, the second thin film layer contacting the bottom of the large hole and the upper surface of the first thin film layer is completely removed in the etching process, and the residual second thin film layer forms a gradual step on the side wall of the contact large hole.
S04: and depositing a functional layer, and forming a contact small hole penetrating through the functional layer at the bottom of the contact large hole.
Preferably, the dielectric layer and the functional material layer are deposited in the contact macropore and on the upper surface of the first thin film layer in sequence, and at the moment, the side wall of the contact macropore is still a gradual step.
And patterning the dielectric layer, the functional material layer and the etching barrier layer in the large hole of the contact hole by adopting photoetching to form a small hole of the contact hole and expose the lower conductive electrode.
S05: and depositing an upper conductive electrode, and connecting the upper conductive electrode with a lower conductive electrode through the contact small hole.
And depositing an upper conductive electrode on the large contact hole, the small contact hole and the upper surface of the first thin film layer by adopting a global process to realize connection with the lower conductive electrode, wherein the upper conductive electrode can be made of various conductive materials such as copper, aluminum, titanium nitride, tantalum nitride, polysilicon and the like, and the thickness of the upper conductive electrode is 5nm-50nm. The upper conductive electrode has good continuity on the step, and the yield and reliability of the device can be improved.
Example 1
The method for manufacturing the contact hole provided by the embodiment comprises the following steps:
s01: as shown in fig. 4, an 8-inch silicon wafer is used as a substrate 01, and a CMOS control circuit is already completed in the substrate 01, and the CMOS control circuit is connected to a lower conductive electrode 02, wherein the lower conductive electrode 02 is located between insulating media 03, and the lower conductive electrode is aluminum with a thickness of 200 nm.
S02: as shown in fig. 5, an etching stop layer 041 is deposited on the lower conductive electrode 02 and the insulating medium 03, and the etching stop layer is 100nm silicon dioxide and can be used as an etching stop layer when a contact macro hole is subsequently etched. Depositing a first thin film layer 042 on the etching barrier layer 041, wherein the first thin film layer 042 is specifically a 1000nm amorphous silicon layer, patterning the first thin film layer by adopting a conventional photoetching and etching process, taking the etching barrier layer as a stop layer, and forming a contact large hole 04 penetrating through the first thin film layer, wherein the depth of the contact large hole is the same as the thickness of the first thin film layer; and the angle of the formed large hole 04 of the contact hole is 82 degrees, namely the contact hole contacts the side wall of the steep step formed in the large hole.
S03: depositing a second thin film layer on the upper surface of the first thin film layer 042 and in the contact macropore 04 by adopting a global process, wherein the second thin film layer is a 150nm silicon dioxide layer;
as shown in fig. 6, the silicon dioxide layer on the surface of the first thin film layer 042 is removed by dry etching, the silicon dioxide layer remaining in the large hole of the contact hole and the first thin film form a graded step 05, the second thin film layer adopts a global deposition process, the formed graded step is located on the side wall of the contact large hole, and the opening area of the top of the graded step is larger than the opening area of the bottom of the contact large hole. When the second thin film layer on the upper surface of the first thin film layer is removed, the second thin film layer contacting the bottom of the large hole is also removed by adopting the same dry etching method, and because the etching rate of the second thin film contacting the bottom of the large hole is close to that of the second thin film on the upper surface of the first thin film layer, the second thin film layer contacting the bottom of the large hole and the upper surface of the first thin film layer is completely removed in the etching process, and the rest second thin film layer forms a gradual step on the side wall of the large hole.
S04: as shown in fig. 7, a dielectric layer 06 and a functional material layer 07 are sequentially deposited inside the contact macro-hole 04 and on the upper surface of the first thin film layer 042, at this time, the side wall of the contact macro-hole is still a graded step, specifically, 50nm of silicon dioxide can be deposited as the dielectric layer 06, and 100nm of amorphous silicon is deposited as the functional material layer 07.
As shown in fig. 8, the dielectric layer 06, the functional material layer 07 and the etching barrier layer 041 are patterned in the large hole of the contact hole by photolithography etching to form a small hole 08 of the contact hole and expose the lower conductive electrode 02.
S05: as shown in fig. 9, 10 nm titanium nitride is deposited on the contact macro holes, the contact micro holes and the upper surface of the first thin film layer by a global process to serve as an upper conductive electrode, and is connected with a lower conductive electrode 2 through the contact micro holes 08. Because the side wall of the contact macro-pore is a gradual step, the 10-nanometer titanium nitride has good continuity on the step, and the yield and the reliability of the device can be improved.
The invention provides a contact hole which comprises a substrate 01, a lower conductive electrode 02, an upper conductive electrode 09, a first thin film layer 042, a graded step 05, a dielectric layer 06, a functional material layer 07, a contact large hole and a contact small hole, wherein the lower conductive electrode 02 is positioned above the substrate 01, the first thin film layer 042 is positioned above the lower conductive electrode 02, the contact large hole is positioned in the first thin film layer 042 and penetrates through the first thin film layer 042, the graded step 05 is positioned on the side wall of the contact large hole, and the top opening of the graded step 05 is larger than the bottom opening; the small contact holes are positioned at the bottoms of the large contact holes, and the upper conductive electrode 09 is connected with the lower conductive electrode 02 through the small contact holes. In addition, the lower conductive electrode 02 is located in the insulating medium 03, the etching barrier layer 041 is deposited before the first thin film layer is deposited, the dielectric layer 06 and the functional material layer 07 are deposited before the contact hole is etched, and then the contact hole 08 penetrating through the functional material layer 07, the dielectric layer 06 and the etching barrier layer 041 is etched.
According to the invention, the contact macropore is formed firstly, and then the gradual step is formed in the contact macropore, so that the discontinuity and the fracture of the upper conductive electrode on the side wall of the contact macropore are avoided, and the yield and the reliability of the device are improved; the preparation method does not need to add a photomask and advanced hole filling equipment, has simple process and is compatible with a CMOS (complementary metal oxide semiconductor) process, and is favorable for reducing the cost.
The above description is only a preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all equivalent structural changes made by using the contents of the specification and the drawings of the present invention should be included in the scope of the appended claims.
Claims (10)
1. A method for manufacturing a contact hole is characterized by comprising the following steps:
s01: providing a substrate, and forming a lower conductive electrode on the substrate;
s02: depositing a first thin film layer on the lower conductive electrode, and etching a large contact hole penetrating through the first thin film layer on the first thin film layer;
s03: depositing a second thin film layer on the first thin film layer and etching the second thin film layer to form a graded step on the side wall of the contact large hole; the opening area of the top of the gradual change step is larger than that of the bottom of the gradual change step;
s04: depositing a functional layer, and forming a contact small hole penetrating through the functional layer at the bottom of the contact large hole;
s05: and depositing an upper conductive electrode, wherein the upper conductive electrode is connected with the lower conductive electrode through the contact small hole.
2. The method for manufacturing a contact hole according to claim 1, wherein the step S02 specifically comprises: depositing an etching barrier layer and a first thin film layer on the lower conductive electrode, and etching a large contact hole penetrating through the first thin film layer on the first thin film layer;
the step S04 specifically includes: and forming a contact small hole penetrating through the functional layer and the etching barrier layer at the bottom of the contact large hole.
3. The method of claim 1, wherein in step S02, the first thin film layer comprises a dielectric material layer and/or an amorphous silicon layer.
4. The method of claim 1, wherein the first thin film layer has a thickness greater than 500nm.
5. The method of claim 1, wherein the second thin film layer comprises an insulating dielectric layer, and the thickness of the second thin film layer is less than the thickness of the first thin film layer.
6. The method of claim 5, wherein in step S03, the second thin film layer is etched by dry etching.
7. The method of claim 6, wherein the step S03 comprises:
s031: depositing a second thin film layer on the first thin film layer;
s032: and removing the second thin film layer on the upper surface of the first thin film layer by adopting optical sheet dry etching, wherein the side wall of the contact macropore is a steep step, and the second thin film layer remained in the contact macropore forms a gradual step on the side wall of the contact macropore.
8. The method for forming a contact hole according to claim 1, wherein the step S04 further comprises: and depositing a functional layer in the contact macropores and on the upper surface of the first thin film layer, and forming a contact pinhole penetrating through the functional layer at the bottom of the contact macropores.
9. The method for manufacturing a contact hole according to claim 8, wherein the functional layer comprises a dielectric layer and a functional material layer, and the dielectric layer and the functional material layer are sequentially deposited inside the contact macro hole and on the upper surface of the first thin film layer in step S04.
10. A contact hole is characterized by comprising a substrate, a lower conductive electrode, an upper conductive electrode, a first thin film layer, a graded step, a functional layer, a large contact hole and a small contact hole, wherein the lower conductive electrode is positioned above the substrate, the first thin film layer is positioned above the lower conductive electrode, the large contact hole is positioned in the first thin film layer and penetrates through the first thin film layer, the graded step is positioned on the side wall of the large contact hole, and the top opening of the graded step is larger than the bottom opening; the functional layer is located in the contact macropore and above the first thin film layer, the contact micropore is located at the bottom of the contact macropore and penetrates through the functional layer, and the upper conductive electrode is connected with the lower conductive electrode through the contact micropore.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911392053.1A CN111128872B (en) | 2019-12-30 | 2019-12-30 | Contact hole and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911392053.1A CN111128872B (en) | 2019-12-30 | 2019-12-30 | Contact hole and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111128872A CN111128872A (en) | 2020-05-08 |
| CN111128872B true CN111128872B (en) | 2022-11-25 |
Family
ID=70504782
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911392053.1A Active CN111128872B (en) | 2019-12-30 | 2019-12-30 | Contact hole and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111128872B (en) |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0383610B1 (en) * | 1989-02-17 | 1997-10-08 | Matsushita Electronics Corporation | Manufacturing method of semiconductor device |
| JPH0541457A (en) * | 1991-08-06 | 1993-02-19 | Nec Corp | Manufacture of semiconductor device |
| JP4937842B2 (en) * | 2007-06-06 | 2012-05-23 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
| JP5923326B2 (en) * | 2012-02-08 | 2016-05-24 | 株式会社ジャパンディスプレイ | Circuit board, manufacturing method thereof, and electro-optical device |
| CN110574153B (en) * | 2017-11-13 | 2024-02-23 | 富士电机株式会社 | Semiconductor device and method for manufacturing semiconductor device |
-
2019
- 2019-12-30 CN CN201911392053.1A patent/CN111128872B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN111128872A (en) | 2020-05-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9550666B2 (en) | MEMS device with release aperture | |
| US8896136B2 (en) | Alignment mark and method of formation | |
| JP5313903B2 (en) | Formation of through-wafer electrical interconnects and other structures using dielectric thin films | |
| JP2564474B2 (en) | Method for forming deep conductive feedthrough and wiring layer including feedthrough formed according to the method | |
| KR100227771B1 (en) | Method of producing cylinderical storage node of stacked capacitor in memory cell | |
| US20190119105A1 (en) | MEMS Method and Structure | |
| CN108346566A (en) | Semiconductor device and its manufacturing method | |
| US8802990B2 (en) | Self-aligned nano-scale device with parallel plate electrodes | |
| CN111128872B (en) | Contact hole and manufacturing method thereof | |
| KR0156646B1 (en) | Capacitor manufacture of semiconductor device | |
| CN108346570B (en) | Manufacturing method of semiconductor device | |
| CN110690163A (en) | Semiconductor device and method for manufacturing the same | |
| JPH1174476A (en) | Semiconductor device and its manufacture | |
| CN109326558B (en) | Groove filling structure and preparation method thereof | |
| US20070284680A1 (en) | Method for manufacturing semiconductor device and semiconductor device using the same | |
| US20060258144A1 (en) | Method of forming metal interconnect for semiconductor device based on selective damascene process | |
| CN111326511A (en) | Memory device and method of manufacturing the same | |
| KR100319637B1 (en) | Method for fabricating capacitor of memory cell | |
| KR20140028722A (en) | Method for manufacturing hole pattern in semiconductor device | |
| KR20040079836A (en) | Method for manufacturing semiconductor device | |
| KR100825019B1 (en) | Method of fabricating capacitor | |
| CN117637606A (en) | Semiconductor structure, preparation method thereof, wafer and chip manufacturing method | |
| JP2000003883A (en) | Manufacture of semiconductor device | |
| KR20010063707A (en) | Method of manufacturing a capacitor in a semiconductor device | |
| CN111498793A (en) | MEMS device and processing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB03 | Change of inventor or designer information | ||
| CB03 | Change of inventor or designer information |
Inventor after: Zuo Qingyun Inventor after: Jiang Bin Inventor after: Lu Yifei Inventor after: Zhou Wei Inventor before: Zuo Qingyun |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant |