CN111124624B - TriCore architecture processor-based operating system task context management method - Google Patents
TriCore architecture processor-based operating system task context management method Download PDFInfo
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- CN111124624B CN111124624B CN201911350249.4A CN201911350249A CN111124624B CN 111124624 B CN111124624 B CN 111124624B CN 201911350249 A CN201911350249 A CN 201911350249A CN 111124624 B CN111124624 B CN 111124624B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/461—Saving or restoring of program or task context
- G06F9/462—Saving or restoring of program or task context with multiple register sets
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/461—Saving or restoring of program or task context
- G06F9/463—Program control block organisation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/485—Task life-cycle, e.g. stopping, restarting, resuming execution
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a method for managing task context of an operating system based on a TriCore architecture processor, which comprises two steps of task context initialization and task context switching; the task context initializing process fully combines an operating system task hardware supporting mechanism provided by a TriCore processor architecture, and allocates two context storage areas for each task during initializing, and respectively stores task entry function addresses and stack addresses; and calling a TriCore assembly instruction to quickly switch the context storage areas of the current task and the new task in the task context switching process. The method does not need to circularly save and restore the register values related to the operation of the processor in the execution process, greatly reduces the execution time of the task context switching of the operating system and improves the safety of the operating system in operation.
Description
Technical Field
The invention relates to the field of embedded operating systems, in particular to an operating system task context management method based on a TriCore architecture processor.
Background
Tasks are the basic unit of operating system operation, and how task objects are managed is a matter of design of each operating system. The task context refers to a general register of a processor and a plurality of special function registers used during task running, the registers represent the running state of the processor, and when different tasks occupy the processor in turn, the corresponding registers need to be modified according to the task storage value, namely the task context is switched. The operation system can frequently perform task context switching operation in the running process, the task context switching can be performed once when the operation system enters a scheduling point every time, and more important tasks occupy processor resources, so that the speed of task switching has a great influence on the real-time response capability of the operation system.
The TriCore architecture is a core architecture developed by infliximab that is suitable for use in multi-core processors and provides numerous support features for the operating system, particularly for task objects. The TriCore architecture designs a special hardware mechanism for the context switching operation of the task, so that the backup work of software on the task context can be reduced. Different types of operating systems have different implementations and different capabilities with respect to how to efficiently utilize such support mechanisms.
Disclosure of Invention
In order to accelerate the task context switching speed of an operating system, the invention provides an operating system task context management method based on a TriCore architecture processor, and the technical scheme adopted by the method comprises two steps of task context initialization and task context switching:
(1) Task context initialization
Constructing a task context structure body according to a register format of the TriCore architecture processor, dividing 32 registers into two groups of contexts, and storing 16 register data in each group of contexts;
two context storage areas are allocated for each task, and a stack field of a task control block is set to be a base address of a second context storage area; the link word of the second context memory area points to the first context memory area;
when a task is initialized, a task stack address is stored in a first set of contexts, and a return address is stored in a second set of contexts;
(2) The context switching of the current task and the new task is executed, and the specific flow is as follows:
(2.1) automatically saving register data for a first set of contexts to a first context store of a current task when the operating system invokes the task context switch function;
(2.2) executing the svlcx instruction to save register data for a second set of contexts to a second context storage area of the current task;
(2.3) writing the PCXI register data into a task control block stack field of the current task;
(2.4) writing the task control block stack field data of the new task into the PCXI register;
(2.5) executing the rslcx instruction to fetch the register data of the second set of contexts from the second context memory area of the new task, writing into the corresponding registers of the second set of contexts, the PCXI register value becoming the first context memory area base address;
(2.6) executing rfe the instruction fetches the register data of the first set of contexts from the first context memory region of the new task, writes into the corresponding registers of the first set of contexts, reads the return address register, and jumps to the return address to begin executing the new task.
Further, only the PCXI register data needs to be modified by software in the task context switching process, the register stores the task context storage area base address, and the register values required by the running of other tasks are updated by hardware quickly.
Further, the return address of the second set of contexts is set to a task entry function during task context initialization, to store the program run address of the task when the task is preempted, and to jump to the address for continued execution when the task context is restored by executing rfe instructions.
Further, when the task runs, two sets of context register data are written into corresponding processor registers, two context storage areas are released, and the PCXI register value is invalid.
Further, when the task is preempted, two context storage areas are reassigned to store two sets of contexts of the task respectively, and a task control block stack field of the preempted task is set to a base address of the second context storage area.
Further, assembler instructions svlcx, rslcx and rfe complete the saving and restoring of task contexts according to the task context storage area pointed to by the PCXI register.
Further, the first set of contexts of the task may also store the address of a security check function, where the security check function automatically jumps to execute when the task ends, and the function releases the system resources occupied by the task and executes corresponding security check.
Further, the first set of context registers of the task includes a program running state PSW register, which can manage the processor privilege level of the task as required during task switching.
The beneficial effects of the invention are as follows: by adopting the method to manage the task objects of the operating system running on the processor of the English-flying-ice TriCore architecture, the supporting characteristic of the processor for switching the task context of the operating system can be fully utilized, the most efficient task switching operation is realized by using the least task context storage space, the real-time performance of the operating system is improved, and the application occasion with higher real-time requirement can be met.
Drawings
FIG. 1 is an overall flow chart of the method of the present invention;
FIG. 2 is a task control block portion field of the present invention;
FIG. 3 is a task context structure of the present invention;
FIG. 4 is task context switch portion assembly code of the present invention.
Detailed Description
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to the appended drawings.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present invention is not limited to the specific embodiments disclosed below.
As shown in fig. 1, the method for managing task context of an operating system based on a TriCore architecture processor according to the embodiment of the present application includes two steps of task context initialization and task context switching:
(1) Task context initialization
Constructing a task context structure body according to a register format of the TriCore architecture processor, dividing 32 registers into two groups of contexts, and storing 16 register data in each group of contexts;
two context storage areas are allocated for each task, and a stack field of a task control block is set to be a base address of a second context storage area; the link word of the second context memory area points to the first context memory area;
when a task is initialized, a task stack address is stored in a first set of contexts, and a return address is stored in a second set of contexts;
(2) When the operating system enters a task scheduling point, a new task is selected to be subjected to context switching with the current task, and the specific flow is as follows:
(2.1) automatically saving register data for a first set of contexts to a first context store of a current task when the operating system invokes the task context switch function;
(2.2) executing the svlcx instruction to save register data for a second set of contexts to a second context storage area of the current task;
(2.3) writing the PCXI register data into a task control block stack field of the current task;
(2.4) writing the task control block stack field data of the new task into the PCXI register;
(2.5) executing the rslcx instruction to fetch the register data of the second set of contexts from the second context memory area of the new task, writing into the corresponding registers of the second set of contexts, the PCXI register value becoming the first context memory area base address;
(2.6) executing rfe the instruction fetches the register data of the first set of contexts from the first context memory region of the new task, writes into the corresponding registers of the first set of contexts, reads the return address register, and jumps to the return address to begin executing the new task.
In this embodiment, the return address of the second set of contexts is set as a task entry function during the task context initialization process, and is set to store the program running address of the task when the task is preempted, and the execution rfe instruction jumps to the address to continue execution when the task context is restored.
In the embodiment of the application, when the task runs, two sets of context register data are written into corresponding processor registers, two context storage areas are released, and the PCXI register value is invalid. When the task is preempted, the two context storage areas are reassigned to store two groups of contexts of the task respectively, and the task control block stack field of the preempted task is set as the base address of the second context storage area.
As shown in fig. 2, the stack field in the task control block is set at the start address of the task control block structure, and is set as the base address of the second context storage area in the process of initializing the task; the two context memory areas are linked by a link word, and the link word of the second context memory area points to the first context memory area.
As shown in FIG. 3, the two sets of task contexts store processor register data necessary for the execution of a portion of the task, respectively, the first set of contexts stores PCXI, PSW, A, A11, D8, D9, D10, D11, A12, A13, A14, A15, D12, D13, D14 and D15, wherein A10 stores the task stack address, A11 can store the security check function address, and the processor privilege level of the task can be managed by the PSW. The second set of contexts stores PCXI, a11, A2, A3, D0, D1, D2, D3, A4, A5, A6, A7, D4, D5, D6, and D7, where a11 stores the last run-time program address of the task, set to the task entry function address at task initialization.
As shown in fig. 4, the task context switching function is implemented by an assembler instruction, when the operating system needs to perform task switching, a new task is selected according to a preset policy, in this embodiment, a task control block pointer of the new task is written into an A5 register as a parameter, a task control block pointer of a current task is written into an A4 register, and then the current task context is saved according to a flow, and execution of the new task is started.
The following provides an implementation procedure of a specific example of the present application:
1) And modifying the task control block structure body, setting a task stack field as a first field of the structure body, and constructing two groups of task context data structures.
2) Two task context storage areas are respectively allocated for each task in a task context initializing function, a first group of contexts A10 is set as a task stack address, A11 is set as a security check function address, and the function jumps when a return instruction is executed after the task is executed, so that the security detection of an operating system is performed. Setting the task entry function address in the second set of contexts a11, and jumping to the task entry function by the task switch function execution return instruction when the task is first run.
3) Modifying the task switch function according to fig. 4, introducing assembler instructions provided by TriCore: svlcx, rslcx and rfe make full use of the support mechanism of the processor for task switching.
The previous description of the embodiments is provided to facilitate a person of ordinary skill in the art in order to make and use the present invention. It will be apparent to those having ordinary skill in the art that various modifications to the above-described embodiments may be readily made and the generic principles described herein may be applied to other embodiments without the use of inventive faculty. Therefore, the present invention is not limited to the above-described embodiments, and those skilled in the art, based on the present disclosure, should make improvements and modifications within the scope of the present invention.
Claims (8)
1. The method for managing the task context of the operating system based on the TriCore architecture processor is characterized by comprising the following two steps of task context initialization and task context switching:
(1) Task context initialization
Constructing a task context structure body according to a register format of the TriCore architecture processor, dividing 32 registers into two groups of contexts, and storing 16 register data in each group of contexts;
two context storage areas are allocated for each task, and a stack field of a task control block is set to be a base address of a second context storage area; the link word of the second context memory area points to the first context memory area;
when a task is initialized, a task stack address is stored in a first set of contexts, and a return address is stored in a second set of contexts;
(2) The context switching of the current task and the new task is executed, and the specific flow is as follows:
(2.1) automatically saving register data for a first set of contexts to a first context store of a current task when the operating system invokes the task context switch function;
(2.2) executing the svlcx instruction to save register data for a second set of contexts to a second context storage area of the current task;
(2.3) writing the PCXI register data into a task control block stack field of the current task;
(2.4) writing the task control block stack field data of the new task into the PCXI register;
(2.5) executing the rslcx instruction to fetch the register data of the second set of contexts from the second context memory area of the new task, writing into the corresponding registers of the second set of contexts, the PCXI register value becoming the first context memory area base address;
(2.6) executing rfe the instruction fetches the register data of the first set of contexts from the first context memory region of the new task, writes into the corresponding registers of the first set of contexts, reads the return address register, and jumps to the return address to begin executing the new task.
2. A method for managing task context of operating system based on TriCore architecture processor according to claim 1, wherein software only needs to modify PCXI register data, which stores the base address of task context memory area, during task context switching, and the register values needed for the operation of other tasks are updated by hardware quickly.
3. A method of managing operating system task contexts in a triore-based architecture processor of claim 1, wherein the return addresses of the second set of contexts are set to task entry functions during task context initialization, to store program run addresses of tasks when the tasks are preempted, and to jump to the addresses for continued execution when the task context is restored by executing rfe instructions.
4. A method of operating system task context management based on a TriCore architecture processor according to claim 1, wherein two sets of context register data are written into corresponding processor registers during task execution, two context memory areas are released, and PCXI register values are invalidated.
5. A method of managing operating system task contexts in a triore-based architecture processor of claim 1, wherein the two context storage areas are reassigned to store two sets of contexts of the task respectively when the task is preempted, and the PCXI register is set to the second context storage area base address.
6. A method of operating system task context management based on a TriCore architecture processor according to claim 1, wherein assembler instructions svlcx, rslcx and rfe complete the saving and restoring of task contexts in accordance with the task context storage area pointed to by the PCXI register.
7. A method for managing task contexts of an operating system based on a processor of a TriCore architecture according to claim 1, wherein the first set of contexts of the task may further store addresses of security check functions, and the security check functions automatically jump to execute when the task is running, the functions releasing system resources occupied by the task and executing corresponding security checks.
8. The method of claim 1, wherein the first set of context registers includes a program running state PSW register, and wherein the processor privilege level of the task can be managed as needed during task switching.
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| CN1313551A (en) * | 2000-01-07 | 2001-09-19 | 摩托罗拉公司 | Apparatus and method for achieving switching context and high speed and low expenditure |
| CN103049325A (en) * | 2013-01-09 | 2013-04-17 | 浙江大学 | Method for implementing CSA (context save area) node manager on basis of TC1767 platform |
| CN110383773A (en) * | 2017-01-05 | 2019-10-25 | 伽德诺克斯信息技术有限公司 | The computing system and its application method of the dedicated programmed for being configured to implement based on Services Oriented Achitecture centralized service ECU with relevant device |
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| CN1313551A (en) * | 2000-01-07 | 2001-09-19 | 摩托罗拉公司 | Apparatus and method for achieving switching context and high speed and low expenditure |
| CN103049325A (en) * | 2013-01-09 | 2013-04-17 | 浙江大学 | Method for implementing CSA (context save area) node manager on basis of TC1767 platform |
| CN110383773A (en) * | 2017-01-05 | 2019-10-25 | 伽德诺克斯信息技术有限公司 | The computing system and its application method of the dedicated programmed for being configured to implement based on Services Oriented Achitecture centralized service ECU with relevant device |
Non-Patent Citations (1)
| Title |
|---|
| 黄鑫.Reworks上下文切换在Tricore上的实现.计算机工程.2011,第37卷368-370. * |
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