CN111107068B - Efficient rule matching method for FPGA and terminal - Google Patents
Efficient rule matching method for FPGA and terminal Download PDFInfo
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- H04L63/00—Network architectures or network communication protocols for network security
- H04L63/02—Network architectures or network communication protocols for network security for separating internal from external traffic, e.g. firewalls
- H04L63/0227—Filtering policies
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- H04L63/02—Network architectures or network communication protocols for network security for separating internal from external traffic, e.g. firewalls
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- H—ELECTRICITY
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- H04L63/02—Network architectures or network communication protocols for network security for separating internal from external traffic, e.g. firewalls
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- H04L63/0245—Filtering by information in the payload
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- H—ELECTRICITY
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- H04L63/02—Network architectures or network communication protocols for network security for separating internal from external traffic, e.g. firewalls
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- H04L63/0263—Rule management
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Abstract
The invention discloses an efficient rule matching method of an FPGA (field programmable gate array), which is characterized in that a message is filtered at a line speed by using a fixed group delay, a numerical value is added to a key string of a hash collision, and then a hash operation is carried out to solve the problem of the hash collision, data read out by the first hash operation result is taken as a numerical value C or 0 and added to the key string, then the hash operation is carried out again, data read out by the second hash operation result is an index address of a matching rule, and the message which does not meet the requirement in a message cache queue is discarded according to the matching result after comparison with a matching item, and the message which meets the requirement is output, so that the precise filtering output of the message is realized.
Description
Technical Field
The invention relates to the technical field of message filtering, in particular to an efficient rule matching method for an FPGA and a terminal thereof.
Background
The Ethernet firewall realizes message filtering through rule matching, and the realization method of the rule matching determines the efficiency of message filtering and the group delay of messages. However, when the hash operation is performed using the keyword string matched with the rule, the hash value may be the same when the input is different, which is called hash collision. For example, when two different messages are subjected to hash operation, the same value can be obtained, so that the messages which do not need to be filtered can be filtered by mistake, and therefore, how to solve the problem of hash collision is a key technical problem for realizing message filtering.
Disclosure of Invention
The invention aims to solve the technical problems and provides an efficient rule matching method for an FPGA (field programmable gate array).
In order to achieve the purpose, the invention adopts the following technical scheme:
an efficient rule matching method for an FPGA (field programmable gate array) comprises the following steps:
The message resolver resolves a message from an Ethernet, extracts a source MAC address, a destination MAC address, a source IP address, a destination IP address, a source port number and a destination port number in the message as information of an item to be matched, outputs the information of the item to be matched to a cache queue of the item to be matched, and outputs the message to a message cache queue;
the cache queue of the item to be matched outputs the keyword string to a first Hash arithmetic unit for Hash arithmetic, and outputs the information of the item to be matched to a matching comparator; the keyword string is one item of matching information or a combination of a plurality of items of matching information of the information to be matched;
the first Hash arithmetic unit carries out Hash arithmetic on the keyword string, and a Hash result is output to a matching item index reader as an address;
The matching item index reader reads the matching item index RAM by using the address in the step 3, if the read numerical value ID is 1,
then: the keyword string is keyword string + character string;
otherwise: the keyword string is + 0;
outputting the keyword string' to a second hash arithmetic unit;
The second hash arithmetic unit carries out hash arithmetic on the keyword string', and a hash result is output to the matching item index reader as an address;
The matching item index reader reads the matching item index RAM by using the address in the step 5 to obtain a read address of a matching rule and outputs the read address to the matching item RAM;
step 7, obtaining the matching item and sending the matching item to the matching item comparator
The matching item RAM reads the matching item RAM by taking the read address of the step 6 as an index value to obtain a matching item, and sends the matching item to the matching item comparator;
The matching item comparer compares and judges the matching item sent by the step 7 with the matching item sent by the cache queue of the item to be matched in the step 2, and outputs a result to the message cache queue, wherein the result is an output message or a discarded message;
The message caching queue operates the message according to the output result of the step 8, and if the result is a discarded message, the message caching queue discards the message; and if the result is the output message, the message cache queue outputs the message.
Further, the data of the matching item index RAM and the matching item RAM are configured through configuration generation software.
Further, the method also comprises the step 81: the method for counting the data information of the matching comparator comprises the following specific steps: and the statistics device is used for carrying out statistics on the data information of the matching comparator and reading the data information by the upper computer.
The invention also provides an FPGA high-efficiency rule matching terminal, which comprises a memory, wherein the memory stores a plurality of instructions, and the instructions are suitable for an FPGA processor to load and execute:
The message resolver resolves a message from an Ethernet, extracts a source MAC address, a destination MAC address, a source IP address, a destination IP address, a source port number and a destination port number in the message as information of an item to be matched, outputs the information of the item to be matched to a cache queue of the item to be matched, and outputs the message to a message cache queue;
the cache queue of the item to be matched outputs the keyword string to a first Hash arithmetic unit for Hash arithmetic, and outputs the information of the item to be matched to a matching comparator; the keyword string is one item of matching information or a combination of a plurality of items of matching information of the information to be matched;
the first Hash arithmetic unit carries out Hash arithmetic on the keyword string, and a Hash result is output to a matching item index reader as an address;
The matching item index reader reads the matching item index RAM by using the address in the step 3, if the read numerical value ID is 1,
then: the keyword string is keyword string + character string;
otherwise: the keyword string is + 0;
outputting the keyword string' to a second hash arithmetic unit;
The second hash arithmetic unit carries out hash arithmetic on the keyword string', and a hash result is output to the matching item index reader as an address;
The matching item index reader reads the matching item index RAM by using the address in the step 5 to obtain a read address of a matching rule and outputs the read address to the matching item RAM;
step 7, obtaining the matching item and sending the matching item to the matching item comparator
The matching item RAM reads the matching item RAM by taking the read address of the step 6 as an index value to obtain a matching item, and sends the matching item to the matching item comparator;
The matching item comparer compares and judges the matching item sent by the step 7 with the matching item sent by the cache queue of the item to be matched in the step 2, and outputs a result to the message cache queue, wherein the result is an output message or a discarded message;
The message caching queue operates the message according to the output result of the step 8, and if the result is a discarded message, the message caching queue discards the message; and if the result is the output message, the message cache queue outputs the message.
Further, the method also comprises the step of performing statistics on data information of the matching comparator, specifically, the statistics device performs statistics on the data information of the matching comparator and is ready for the upper computer to read.
Further, the data of the matching item index RAM and the matching item RAM are configured through configuration generation software.
The invention uses fixed group delay to filter the message at line speed, adds a numerical value to the key word string of the hash conflict, and then carries out hash operation once to solve the problem of the hash conflict, and discards the message which does not meet the requirement in the message cache queue according to the matching result after comparing with the matching item, and outputs the message which meets the requirement, thereby realizing the accurate filtering of the message.
Drawings
FIG. 1: the invention discloses a work flow diagram of an FPGA efficient rule matching method.
FIG. 2: the invention discloses a work flow diagram of an FPGA efficient rule matching terminal.
Description of numbering:
1: a message parser; 2: caching queues of items to be matched; 3: a first hash operator; 4: a first matching item index reader; 5: matching item index RAM; 6: a second hash operator; 7: a second matching item index reader; 8: a matching item RAM; 9: a matching term comparator; 10: a message buffer queue; 11: a statistics machine; 12: the configuration generation software.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and examples.
The invention configures the matching item index RAM5 and the matching item RAM 8 in advance through the configuration generation software 12, namely, configures the matching rules, which belongs to the prior art, so how to configure is not described in detail herein.
The invention is realized on FPGA, and can also be realized on software or ASIC.
Example one
As shown in fig. 1, an efficient rule matching method for an FPGA includes the following steps:
The message resolver 1 resolves the message from the ethernet, extracts the source MAC address, the destination MAC address, the source IP address, the destination IP address, the source port number, the destination port number, and the like in the message as the information of the item to be matched, and outputs the information of the item to be matched to the item cache queue 2 to be matched, and simultaneously outputs the message to the message cache queue 10;
the cache queue 2 for the item to be matched outputs the keyword string to a first hash arithmetic unit 3 for hash arithmetic, and outputs the information of the item to be matched to a matching item comparator 9; the keyword string is one item of matching item information or a combination of a plurality of items of matching item information of the information to be matched;
the first hash arithmetic unit 3 performs hash arithmetic on the keyword string, and a hash result is output to a first matching item index reader 4 as an address;
The first matching item index reader 4 reads the matching item index RAM5 with the address of step 3, and if the read value ID is 1,
then: the keyword string is keyword string + C;
otherwise: the keyword string is + 0;
and outputs the keyword string' to a second hash arithmetic unit 6;
note that, the keyword string' is a keyword string + C, where C may be any other character string, such as B, D, and C is taken as an example in this embodiment.
The second hash arithmetic unit 6 performs hash arithmetic on the keyword string', and a hash result is output to the second matching item index reader 7 as an address;
The second matching item index reader 7 reads the matching item index RAM5 by using the address in the step 5 to obtain a read address of the matching rule and outputs the read address to the matching item RAM 8;
step 7, obtaining the matching item and sending the matching item to the matching item comparator
The matching item RAM 8 reads the matching item RAM 8 by taking the reading address of the step 6 as an index value to obtain a matching item, and sends the matching item to the matching item comparator 9;
The matching item comparer 9 compares and judges the matching item sent from the step 7 with the matching item sent from the item to be matched cache queue 2 in the step 2, and outputs a result to the message cache queue 10, wherein the result is an output message or a discarded message;
The message cache queue 10 operates the message according to the output result of the step 8, and if the result is a discarded message, the message cache queue 10 discards the message; if the result is an output message, the message buffer queue 10 outputs the message.
Preferably, the method further comprises the step 81: the method for counting the data information of the matching comparator comprises the following specific steps: and the statistics device 11 is used for carrying out statistics on the data information of the matching item comparator for being read by an upper computer.
In this embodiment, the packet is filtered at a line speed by using a fixed group delay (tens of clock cycles of the FPGA), a value is added to a keyword string of the hash collision, and the hash collision is solved by performing a hash operation again. And taking the data read out from the first hash operation result as a numerical value C or 0, adding the numerical value C or 0 with the keyword string, and then performing the hash operation once, wherein the data read out from the second hash operation result is the index address of the matching rule. And discarding the message which does not meet the requirement in the message cache queue according to the matching result after comparing with the matching item, and outputting the message which meets the requirement, thereby realizing the accurate filtering output of the message.
Example two
As shown in fig. 1-2, an FPGA high-efficiency rule matching terminal includes a memory, where the memory stores a plurality of instructions, and the instructions are suitable for being loaded and executed by an FPGA processor, and the execution steps are specifically as follows:
The message resolver 1 resolves the message from the ethernet, extracts the source MAC address, the destination MAC address, the source IP address, the destination IP address, the source port number, the destination port number, and the like in the message as the information of the item to be matched, and outputs the information of the item to be matched to the item cache queue 2 to be matched, and simultaneously outputs the message to the message cache queue 10;
The cache queue 2 for the item to be matched outputs the keyword string to a first hash arithmetic unit 3 for hash arithmetic, and outputs the information of the item to be matched to a matching item comparator 9; the keyword string is one item of matching item information or a combination of a plurality of items of matching item information of the information to be matched;
The first hash arithmetic unit 3 performs hash arithmetic on the keyword string, and a hash result is output to a first matching item index reader 4 as an address;
The first matching item index reader 4 reads the matching item index RAM5 with the address of step 3, and if the read value ID is 1,
then: the keyword string is keyword string + C;
otherwise: the keyword string is + 0;
and outputs the keyword string' to a second hash arithmetic unit 6;
note that, the keyword string' is a keyword string + C, where C may be any other character string, such as B, D, and C is taken as an example in this embodiment.
The second hash arithmetic unit 6 performs hash arithmetic on the keyword string', and a hash result is output to the second matching item index reader 7 as an address;
The second matching item index reader 7 reads the matching item index RAM5 by using the address in the step 5 to obtain a read address of the matching rule and outputs the read address to the matching item RAM 8;
step 7, obtaining the matching item and sending the matching item to the matching item comparator
The matching item RAM 8 reads the matching item RAM 8 by taking the reading address of the step 6 as an index value to obtain a matching item, and sends the matching item to the matching item comparator 9;
The matching item comparer 9 compares and judges the matching item sent from the step 7 with the matching item sent from the item to be matched cache queue 2 in the step 2, and outputs a result to the message cache queue 10, wherein the result is an output message or a discarded message;
The message cache queue 10 operates the message according to the output result of the step 8, and if the result is a discarded message, the message cache queue 10 discards the message; if the result is an output message, the message buffer queue 10 outputs the message.
Preferably, the method further comprises the step 81: the method for counting the data information of the matching comparator comprises the following specific steps: and the statistics device 11 is used for carrying out statistics on the data information of the matching item comparator for being read by an upper computer.
In the above embodiments one and two:
the first hash operator 3 is identical to the second hash operator 6, and the first and second matching index readers 4 and 7 are identical.
The matching item index RAM5 stores two kinds of data, one is the index address of the matching item RAM 8; the other is a value C for avoiding hash collision, the two data are distinguished by a single identification bit ID, the occupied cell in the matching item index RAM5 is identified by a bit with position 1, the unused cell is filled with 0, the depth of the matching item index RAM5 is at least twice as deep as the matching item RAM 8, it is appropriate to have 4 times as deep, if the matching item RAM 8 has 4096 items, 16384 16 bits of the matching item index RAM5 is sufficient.
The matching item RAM 8 is mainly used for storing matching rule data.
The configuration generation software 12 is used for generating and storing matching rule data, searching for a numerical value C with the same hash operation value of the avoided keyword string, and configuring the matching item index RAM5 and the matching item RAM 8.
Finally, it should be noted that: the above embodiments are only used to illustrate the present invention and do not limit the technical solutions described in the present invention; thus, while the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted; all such modifications and variations are intended to be included herein within the scope of this disclosure and the present invention and protected by the following claims.
Claims (6)
1. An efficient rule matching method for an FPGA (field programmable gate array), which is characterized by comprising the following steps of:
step 1, analyzing the message
The message resolver resolves a message from an Ethernet, extracts a source MAC address, a destination MAC address, a source IP address, a destination IP address, a source port number and a destination port number in the message as information of an item to be matched, outputs the information of the item to be matched to a cache queue of the item to be matched, and outputs the message to a message cache queue;
step 2, outputting the keyword strings and the matching items for hash operation:
the cache queue of the item to be matched outputs the keyword string to a first Hash arithmetic unit for Hash arithmetic, and outputs the information of the item to be matched to a matching comparator; the keyword string is one item of matching information or a combination of a plurality of items of matching information of the information to be matched;
step 3, carrying out hash operation for the first time:
the first Hash arithmetic unit carries out Hash arithmetic on the keyword string, and a Hash result is output to a matching item index reader as an address;
step 4, reading the matching item index RAM for the first time
The matching item index reader reads the matching item index RAM by using the address in the step 3, if the read numerical value ID is 1,
then: keyword string' = keyword string + non-0 character string;
otherwise: keyword string' = keyword string + 0;
outputting the keyword string' to a second hash arithmetic unit;
step 5, the second Hash operation
The second hash arithmetic unit carries out hash arithmetic on the keyword string', and a hash result is output to the matching item index reader as an address;
step 6, reading the matching item index RAM for the second time
The matching item index reader reads the matching item index RAM by using the address in the step 5 to obtain a read address of a matching rule and outputs the read address to the matching item RAM;
step 7, obtaining the matching item and sending the matching item to the matching item comparator
The matching item RAM reads the matching item RAM by taking the read address of the step 6 as an index value to obtain a matching item, and sends the matching item to the matching item comparator;
step 8, comparing and judging the matching item data
The matching item comparer compares and judges the matching item sent by the step 7 with the matching item sent by the cache queue of the item to be matched in the step 2, and outputs a result to the message cache queue, wherein the result is an output message or a discarded message;
step 9, filtering and outputting
The message caching queue operates the message according to the output result of the step 8, and if the result is a discarded message, the message caching queue discards the message; and if the result is the output message, the message cache queue outputs the message.
2. The FPGA efficient rule matching method of claim 1, characterized in that: and the data of the matching item index RAM and the matching item RAM are configured through configuration generation software.
3. The FPGA efficient rule matching method of claim 1, further comprising the step of 81: the method for counting the data information of the matching comparator comprises the following specific steps: and the statistics device is used for carrying out statistics on the data information of the matching comparator for being read by an upper computer.
4. The utility model provides a high-efficient rule matching terminal of FPGA which characterized in that: comprising a memory storing a plurality of instructions adapted to be loaded and executed by an FPGA processor:
step 1, analyzing the message
The message resolver resolves a message from an Ethernet, extracts a source MAC address, a destination MAC address, a source IP address, a destination IP address, a source port number and a destination port number in the message as information of an item to be matched, outputs the information of the item to be matched to a cache queue of the item to be matched, and outputs the message to a message cache queue;
step 2, outputting the keyword strings and the matching items for hash operation:
the cache queue of the item to be matched outputs the keyword string to a first Hash arithmetic unit for Hash arithmetic, and outputs the information of the item to be matched to a matching comparator; the keyword string is one item of matching information or a combination of a plurality of items of matching information of the information to be matched;
step 3, carrying out hash operation for the first time:
the first Hash arithmetic unit carries out Hash arithmetic on the keyword string, and a Hash result is output to a matching item index reader as an address;
step 4, reading the matching item index RAM for the first time
The matching item index reader reads the matching item index RAM by using the address in the step 3, if the read numerical value ID is 1,
then: keyword string' = keyword string + non-0 character string;
otherwise: keyword string' = keyword string + 0;
outputting the keyword string' to a second hash arithmetic unit;
step 5, the second Hash operation
The second hash arithmetic unit carries out hash arithmetic on the keyword string', and a hash result is output to the matching item index reader as an address;
step 6, reading the matching item index RAM for the second time
The matching item index reader reads the matching item index RAM by using the address in the step 5 to obtain a read address of a matching rule and outputs the read address to the matching item RAM;
step 7, obtaining the matching item and sending the matching item to the matching item comparator
The matching item RAM reads the matching item RAM by taking the read address of the step 6 as an index value to obtain a matching item, and sends the matching item to the matching item comparator;
step 8, comparing and judging the matching item data
The matching item comparer compares and judges the matching item sent by the step 7 with the matching item sent by the cache queue of the item to be matched in the step 2, and outputs a result to the message cache queue, wherein the result is an output message or a discarded message;
step 9, filtering and outputting
The message caching queue operates the message according to the output result of the step 8, and if the result is a discarded message, the message caching queue discards the message; and if the result is the output message, the message cache queue outputs the message.
5. The FPGA high-efficiency rule matching terminal of claim 4, wherein: the method also comprises the step of performing statistics on data information of the matching comparator, wherein the statistics is specifically performed on the data information of the matching comparator by the statistics device for being read by an upper computer.
6. The FPGA high-efficiency rule matching terminal of claim 4, wherein: and the data of the matching item index RAM and the matching item RAM are configured through configuration generation software.
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