CN111092445B

CN111092445B - Signal reliability detection method, PSE chip, CPU chip and PoE device

Info

Publication number: CN111092445B
Application number: CN201811245367.4A
Authority: CN
Inventors: 杨传枫
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2018-10-24
Filing date: 2018-10-24
Publication date: 2021-10-26
Anticipated expiration: 2038-10-24
Also published as: CN111092445A

Abstract

The embodiment of the application provides a signal reliability detection method, a PSE chip, a CPU chip and PoE equipment, wherein the method comprises the following steps: the method comprises the steps of obtaining a bias current of a target output line pair on a primary coil side of a transformer, wherein the transformer is a transformer corresponding to a target port of the PoE equipment for Ethernet power supply, determining the voltage drop percentage of the target output line pair according to the bias current and the corresponding relation between the bias current and the voltage drop percentage of the target output line pair, and judging whether the target output line can reliably transmit signals or not according to the voltage drop percentage of the target output line pair and a preset voltage drop interval. The technical scheme can judge whether the output line in the system where the PoE equipment is positioned can reliably transmit signals, and improves the signal stability of the PoE system.

Description

Signal reliability detection method, PSE chip, CPU chip and PoE device

Technical Field

The application relates to the technical field of power supply equipment, in particular to a signal reliability detection method, a PSE chip, a CPU chip and PoE equipment.

Background

With the development of power over ethernet (PoE) technology and the improvement of PoE standards, the variety of devices capable of supporting remote power applications is increasing. The PoE system including the Power Sourcing Equipment (PSE) and the power receiving equipment (PD) has the characteristics of large power supply, long transmission distance and high transmission rate. Due to the fact that the PD power in the PoE system is increased, the maximum power which can be output by the PoE switch is correspondingly increased, the current transmitted on an Ethernet line is increased, loss is increased, and the problem of power supply balance is caused.

Currently, for PoE systems, there are the following specifications in the PoE standard: the PSE terminal and the PD terminal require that the unbalance degree of the resistance of the whole PoE system is less than 3 percent. The unbalanced resistance is a requirement for unbalanced resistance of a power supply loop in the whole PoE system, and the unbalanced resistance of the power supply loop is greatly influenced by external configuration, so that the transmission distance of an electric signal and the reliability of a data signal are influenced, and the transmission distance of the electric signal is shortened and the reliability of the data signal is reduced.

In summary, in the PoE system, it is necessary to determine whether the signal can be reliably transmitted.

Disclosure of Invention

The embodiment of the application provides a signal reliability detection method, a PSE chip, a CPU chip and a PoE device, which are used for judging whether a PoE system can reliably transmit signals.

A first aspect of the present application provides a method for detecting signal reliability, including: the PoE equipment firstly acquires the bias current of a target output line pair at the primary coil side of a transformer, wherein the transformer is a transformer corresponding to a target port of the PoE equipment powered by Ethernet; secondly, determining the voltage drop percentage of the target output line pair according to the bias current and the corresponding relation between the bias current and the voltage drop percentage of the target output line pair; and finally, judging whether the target output line can reliably transmit signals or not according to the voltage drop percentage of the target output line pair and a preset voltage drop interval.

The technical scheme can judge whether the output line in the system where the PoE equipment is located can reliably transmit signals, and improves the signal stability of the PoE system.

Optionally, in a possible implementation manner of the first aspect, the obtaining a bias current of a target output line pair on a primary coil side of a transformer includes: and collecting the voltages at two ends of the primary coil side of the transformer, and calculating the bias current of the target output line pair according to the voltages and the collection time points corresponding to the voltages.

Optionally, in the foregoing possible implementation manner of the first aspect, before the calculating, according to the voltage and the acquisition time point corresponding to the voltage, the bias current of the target output line pair, the method further includes:

denoising the voltage by using a wavelet transform method to obtain a denoised voltage;

correspondingly, the calculating the bias current of the target output line pair according to the voltage and the acquisition time point corresponding to the voltage includes:

and calculating the bias current according to the denoised voltage and the acquisition time point.

In this embodiment, the denoised voltage is obtained by a wavelet transform method, and then the denoised voltage is used to calculate the bias current, so as to effectively filter the noise of the system where the PoE device is located, thereby improving the accuracy of voltage acquisition.

Optionally, in another possible implementation manner of the first aspect, before the obtaining the bias current of the target output line pair on the primary coil side of the transformer, the method further includes:

and sending an automatic classification waveform, wherein the automatic classification waveform is used for indicating that the power of a power receiving end device PD in a system where the PoE device is located is increased to the maximum.

In this embodiment, when the PD is at the maximum power, the signal transmitted by the target output line of the target port of the PoE device has the maximum distortion, that is, the power of the PD is indicated to be increased to the maximum by sending the automatic classification waveform, so that when the PoE device evaluates the reliability of the signal transmitted by the target output line under the condition of the most serious signal distortion, the accuracy of the judgment result can be improved.

Optionally, in yet another possible implementation manner of the first aspect, the method further includes:

and acquiring the corresponding relation between the bias current of the target output line pair and the voltage drop percentage.

Optionally, in another possible implementation manner of the first aspect, the determining, according to a voltage drop percentage of the target output line pair and a preset voltage drop interval, whether the target output line pair can reliably transmit a signal includes:

judging whether the voltage drop percentage of the target output line pair is in the preset voltage drop interval or not;

if so, determining that the target output line pair can reliably transmit signals;

and if not, determining that the target output line pair cannot reliably transmit signals.

Optionally, in another possible implementation manner of the first aspect, after the determining that the target output line pair cannot reliably transmit a signal, the method further includes:

and sending alarm information, wherein the alarm information is used for indicating that the target output line pair cannot reliably transmit signals.

In this embodiment, the PoE device determines whether a target output line can reliably transmit a signal, and when it determines that the target output line pair cannot reliably transmit the signal, sends an alarm message, and notifies the network management device that the target output line pair cannot reliably transmit the signal, so that network personnel or the network management device take corresponding measures.

A second aspect of the present application provides a signal reliability detecting apparatus, the apparatus comprising: the device comprises a processing module and a judging module;

the processing module is used for acquiring the bias current of a target output line pair at the primary coil side of a transformer, wherein the transformer is a transformer corresponding to a target port of the PoE equipment for Ethernet power supply, and the voltage drop percentage of the target output line pair is determined according to the bias current and the corresponding relation between the bias current of the target output line pair and the voltage drop percentage;

and the judging module is used for judging whether the target output line can reliably transmit signals or not according to the voltage drop percentage of the target output line pair and a preset voltage drop interval.

Optionally, in a possible implementation manner of the second aspect, the processing module is configured to obtain a bias current of a target output line pair on a primary coil side of the transformer, and specifically, the processing module is configured to:

the processing module is specifically configured to acquire voltages at two ends of a primary coil side of the transformer, and calculate a bias current of the target output line pair according to the voltages and acquisition time points corresponding to the voltages.

Optionally, in the foregoing possible implementation manner of the second aspect, the processing module is further configured to perform denoising processing on the voltage by using a wavelet transform method before calculating the bias current of the target output line pair according to the voltage and the acquisition time point corresponding to the voltage, so as to obtain a denoised voltage;

correspondingly, the processing module is configured to calculate a bias current of the target output line pair according to the voltage and the acquisition time point corresponding to the voltage, specifically:

the processing module is specifically configured to calculate the bias current according to the denoised voltage and the acquisition time point.

Optionally, in another possible implementation manner of the second aspect, the apparatus further includes: an output module;

the output module is configured to send an automatic classification waveform before the processing module obtains the bias current of the target output line pair on the primary coil side of the transformer, where the automatic classification waveform is used to indicate that the power of the power receiving device PD in the system where the PoE device is located is increased to the maximum.

Optionally, in another possible implementation manner of the second aspect, the processing module is further configured to obtain a corresponding relationship between a bias current and a voltage drop percentage of the target output line pair.

Optionally, in another possible implementation manner of the second aspect, the determining module is configured to determine whether the target output line can reliably transmit the signal according to a voltage drop percentage of the target output line pair and a preset voltage drop interval, and specifically includes:

the judging module is specifically configured to judge whether the voltage drop percentage of the target output line pair is within the preset voltage drop interval, and determine that the target output line pair can reliably transmit signals when the voltage drop percentage of the target output line pair is within the preset voltage drop interval, otherwise, determine that the target output line pair cannot reliably transmit signals.

Optionally, in another possible implementation manner of the second aspect, the output module is configured to send alarm information after the determining module determines that the target output line pair cannot reliably transmit the signal, where the alarm information is used to indicate that the target output line pair cannot reliably transmit the signal.

A third aspect of the present application provides a method for detecting signal reliability, which is applicable to a PSE chip of a power supply device disposed in a PoE device for power over ethernet, and the method includes:

obtaining a bias current of a target output line pair at a primary coil side of a transformer, wherein the transformer is a transformer corresponding to a target port of the PoE equipment;

and sending the bias current to a Central Processing Unit (CPU) chip arranged in the PoE equipment, wherein the bias current is used for judging whether the target output line pair can reliably transmit signals by the CPU chip.

Optionally, in a possible implementation manner of the third aspect, the obtaining a bias current of a target output line pair on a primary coil side of a transformer includes:

collecting voltages at two ends of the primary coil side of the transformer;

and calculating the bias current of the target output line pair according to the voltage and the acquisition time point corresponding to the voltage.

Optionally, in another possible implementation manner of the third aspect, before the obtaining the bias current of the target output line pair on the primary coil side of the transformer, the method further includes:

A fourth aspect of the present application provides a method for detecting signal reliability, which is applicable to a CPU chip of a central processing unit disposed in PoE (power over ethernet) equipment, and the method includes:

receiving a bias current sent by a power supply equipment PSE chip arranged in the PoE equipment, wherein the bias current is the current of a target output line pair at the primary coil side of a transformer, and the transformer is a transformer corresponding to a target port of the PoE equipment;

determining the voltage drop percentage of the target output line pair according to the bias current and the corresponding relation between the bias current and the voltage drop percentage of the target output line pair;

and judging whether the target output line can reliably transmit signals or not according to the voltage drop percentage of the target output line pair and a preset voltage drop interval.

Optionally, in a possible implementation manner of the fourth aspect, the method further includes:

Optionally, in another possible implementation manner of the fourth aspect, the determining whether the target output line can reliably transmit the signal according to the voltage drop percentage of the target output line pair and a preset voltage drop interval includes:

Optionally, in the foregoing possible implementation manner of the fourth aspect, after the determining that the target output line pair cannot reliably transmit a signal, the method further includes:

The fifth aspect of the present application provides a signal reliability detecting device, which is suitable for a PSE chip of a power supply end device disposed in a PoE device, the device includes: the device comprises a processing module and an output module;

the processing module is used for acquiring the bias current of a target output line pair at the primary coil side of a transformer, wherein the transformer is a transformer corresponding to a target port of the PoE equipment;

the output module is used for sending the bias current to a Central Processing Unit (CPU) chip arranged in the PoE equipment, and the bias current is used for judging whether the target output line pair can reliably transmit signals by the CPU chip.

Optionally, in a possible implementation manner of the fifth aspect, the processing module is configured to obtain a bias current of a target output line pair on a primary coil side of the transformer, and specifically, the processing module is configured to:

the processing module is used for acquiring the voltages at two ends of the primary coil side of the transformer and calculating the bias current of the target output line pair according to the voltages and the acquisition time points corresponding to the voltages.

Optionally, in another possible implementation manner of the fifth aspect, the output module is further configured to send an automatic classification waveform before the processing module obtains the bias current of the target output line pair on the primary coil side of the transformer, where the automatic classification waveform is used to instruct the power of the power receiving end device PD in the system where the PoE device is located to be increased to the maximum.

A sixth aspect of the present application provides a signal reliability detecting device, which is suitable for a CPU chip of a central processing unit disposed in a PoE device, the device comprising: the device comprises an input/output module, a processing module and a judging module;

the input/output module is used for receiving a bias current sent by a power supply equipment PSE chip arranged in the PoE equipment, wherein the bias current is the current of a target output line pair at the primary coil side of a transformer, and the transformer is a transformer corresponding to a target port of the PoE equipment;

the processing module is used for determining the voltage drop percentage of the target output line pair according to the bias current and the corresponding relation between the bias current and the voltage drop percentage of the target output line pair;

Optionally, in a possible implementation manner of the sixth aspect, the processing module is further configured to obtain a corresponding relationship between a bias current and a voltage drop percentage of the target output line pair.

Optionally, in another possible implementation manner of the sixth aspect, the determining module is configured to determine whether the target output line can reliably transmit the signal according to the voltage drop percentage of the target output line pair and a preset voltage drop interval, and specifically includes:

Optionally, in the foregoing possible implementation manner of the sixth aspect, the input/output module is further configured to send alarm information after the determining module determines that the target output line pair cannot reliably transmit the signal, where the alarm information is used to indicate that the target output line pair cannot reliably transmit the signal.

The seventh aspect of the present application provides a Power Sourcing Equipment (PSE) chip, where the PSE chip is disposed in a PoE device, and the PSE chip includes: a measurement circuit, a processor and an output interface;

the measurement circuit is used for measuring the voltage of a target output line pair at the primary coil side of a transformer at two ends, and the transformer is a transformer corresponding to a target port of the PoE equipment;

the processor is used for calculating the bias current of the target output line pair according to the voltage and the acquisition time point corresponding to the voltage;

the output interface is used for sending the bias current to a Central Processing Unit (CPU) chip, and the bias current is used for judging whether the target output line pair can reliably transmit signals or not by the CPU chip.

Optionally, in a possible implementation manner of the seventh aspect, the output interface is further configured to send an automatic classification waveform before the measurement circuit measures and collects the voltage across the target output line pair on the primary coil side of the transformer, where the automatic classification waveform is used to indicate that the power of the power receiving device PD in the system where the PoE device is located is raised to the maximum.

An eighth aspect of the present application provides a CPU chip, where the CPU chip is disposed in a PoE device, and the CPU chip includes: the method comprises the following steps: an input/output interface and a processor;

the input/output interface is used for receiving a bias current sent by a power supply equipment PSE chip in the PoE equipment, wherein the bias current is the current of a target output line pair at the primary coil side of a transformer, and the transformer is a transformer corresponding to a target port of the PoE equipment;

and the processor is used for determining the voltage drop percentage of the target output line pair according to the bias current and the corresponding relation between the bias current and the voltage drop percentage of the target output line pair, and judging whether the target output line can reliably transmit signals or not according to the voltage drop percentage of the target output line pair and a preset voltage drop interval.

Optionally, in a possible implementation manner of the eighth aspect, the processor is further configured to obtain a corresponding relationship between a bias current and a voltage drop percentage of the target output line pair.

Optionally, in another possible implementation manner of the eighth aspect, the processor is configured to determine whether the target output line can reliably transmit the signal according to the voltage drop percentage of the target output line pair and a preset voltage drop interval, and specifically includes:

the processor is specifically configured to determine whether the voltage drop percentage of the target output line pair is within the preset voltage drop interval, and determine that the target output line pair can reliably transmit signals when the voltage drop percentage of the target output line pair is within the preset voltage drop interval, otherwise, determine that the target output line pair cannot reliably transmit signals.

Optionally, in the foregoing possible implementation manner of the eighth aspect, the input/output interface is further configured to send an alarm message after the processor determines that the target output line pair cannot reliably transmit a signal, where the alarm message is used to indicate that the target output line pair cannot reliably transmit a signal.

The ninth aspect of the present application provides a Power Sourcing Equipment (PSE) chip, PSE chip sets up in Ethernet power supply PoE equipment, PSE chip includes: a measurement circuit and an output interface;

the measurement circuit is used for acquiring the voltage of a target output line pair at the primary coil side of a transformer at two ends, and the transformer is a transformer corresponding to a target port of the PoE equipment;

and the output interface is used for sending the voltage to a Central Processing Unit (CPU) chip, wherein the voltage is used for the CPU chip to calculate the bias current of the target output line pair, and judging whether the target output line pair can reliably transmit signals according to the bias current.

Optionally, in a possible implementation manner of the ninth aspect, the output interface is further configured to send an automatic classification waveform before the measurement circuit measures and collects voltages at two ends of the target output line pair on the primary coil side of the transformer, where the automatic classification waveform is used to indicate that the power of the power receiving device PD in the system where the PoE device is located is raised to the maximum.

A tenth aspect of the present application provides a CPU chip, where the CPU chip is disposed in a PoE device, the CPU chip includes: an input/output interface and a processor;

the input/output interface is used for receiving a voltage sent by a power supply equipment PSE chip in the PoE equipment, wherein the voltage is the voltage of two ends of a target output line pair at the primary coil side of a transformer, and the transformer is a transformer corresponding to a target port of the PoE equipment;

the processor is used for calculating the bias current of the target output line pair according to the voltage and the acquisition time point corresponding to the voltage, determining the voltage drop percentage of the target output line pair according to the bias current and the corresponding relation between the bias current and the voltage drop percentage of the target output line pair, and judging whether the target output line can reliably transmit signals according to the voltage drop percentage of the target output line pair and a preset voltage drop interval.

Optionally, in a possible implementation manner of the tenth aspect, the processor is further configured to perform denoising processing on the voltage by using a wavelet transform method before calculating a bias current of the target output line pair according to the voltage and an acquisition time point corresponding to the voltage, so as to obtain a denoised voltage;

correspondingly, the processor is configured to calculate a bias current of the target output line pair on the primary coil side of the transformer according to the voltage and the acquisition time point corresponding to the voltage, specifically:

the processor is specifically configured to calculate the bias current according to the denoised voltage and the acquisition time point.

Optionally, in another possible implementation manner of the tenth aspect, the processor is further configured to obtain a corresponding relationship between a bias current and a voltage drop percentage of the target output line pair.

Optionally, in another possible implementation manner of the tenth aspect, the processor is configured to determine whether the target output line can reliably transmit the signal according to a voltage drop percentage of the target output line pair and a preset voltage drop interval, and specifically includes:

the processor is specifically configured to determine whether a voltage drop percentage of the target output line pair is within the preset voltage drop interval, determine that the target output line pair can reliably transmit signals if the voltage drop percentage of the target output line pair is within the preset voltage drop interval, and determine that the target output line pair cannot reliably transmit signals if the voltage drop percentage of the target output line pair is not within the preset voltage drop interval.

Optionally, in the foregoing possible implementation manner of the tenth aspect, the input/output interface is further configured to send an alarm message after the processor determines that the target output line pair cannot reliably transmit a signal, where the alarm message is used to indicate that the target output line pair cannot reliably transmit a signal.

An eleventh aspect of the present application provides a PoE device, comprising: at least comprises the following steps: the power supply end equipment comprises a PSE chip and a CPU chip;

the PSE chip is the signal reliability detection device of each implementation manner of the fifth aspect and the fifth aspect or the PSE chip of each implementation manner of the seventh aspect and the seventh aspect, and the CPU chip is the signal reliability detection device of each implementation manner of the sixth aspect and the sixth aspect or the CPU chip of each implementation manner of the eighth aspect and the eighth aspect;

or

The PSE chip is a PSE chip of each implementation manner of the ninth aspect and the ninth aspect, and the CPU chip is a CPU chip of each implementation manner of the tenth aspect and the tenth aspect.

According to the signal reliability detection method, the PSE chip, the CPU chip and the PoE device, by obtaining the bias current of the target output line pair at the primary coil side of the transformer, the transformer is a transformer corresponding to the target port of the PoE device powered by the Ethernet, the voltage drop percentage of the target output line pair is determined according to the bias current and the corresponding relation between the bias current and the voltage drop percentage of the target output line pair, and whether the target output line can reliably transmit signals or not is judged according to the voltage drop percentage of the target output line pair and a preset voltage drop interval. The technical scheme can judge whether the output line in the system where the PoE equipment is located can reliably transmit signals, and improves the signal stability of the PoE system.

Drawings

Fig. 1 is a schematic structural diagram of a PoE system according to an embodiment of the present application;

fig. 2 is a schematic flowchart of a first embodiment of a signal reliability detection method according to an embodiment of the present application;

FIG. 3 is a graph illustrating the relationship between bias current and the ratio of target output line to output voltage;

fig. 4 is an interaction flowchart of a second embodiment of a signal reliability detection method provided in the embodiment of the present application;

fig. 5 is an interaction flowchart of a third embodiment of a signal reliability detection method provided in the embodiment of the present application;

fig. 6 is a schematic structural diagram of a first embodiment of a signal reliability detection apparatus according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of a second embodiment of a signal reliability detection apparatus according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of a third embodiment of a signal reliability detection apparatus according to an embodiment of the present application;

FIG. 9 is a simplified schematic diagram of one possible design structure of a PSE chip involved in an embodiment of the present application;

FIG. 10 is a simplified schematic diagram of one possible design structure of a CPU chip involved in an embodiment of the present application;

FIG. 11 is a simplified schematic diagram of another possible design structure of a PSE chip involved in an embodiment of the present application;

FIG. 12 is a simplified schematic diagram of another possible design structure of a CPU chip involved in an embodiment of the present application;

fig. 13 is a schematic composition diagram of a PoE device according to an embodiment of the present application.

Detailed Description

The signal reliability detection method provided by the following embodiments of the present application is applicable to a PoE system. Fig. 1 is a schematic structural diagram of a PoE system according to an embodiment of the present application. As shown in fig. 1, the PoE system may include: a power sourcing equipment PSE 11 and at least one power receiving equipment PD 12. Fig. 1 exemplarily shows one PSE 11 and three PDs 12. In the PoE system of the embodiment shown in fig. 1, the PSE 11 has a plurality of ports, each port of the PSE 11 is connected to one PD 12 through a network cable, each network cable may include a plurality of pairs of output lines, and each pair of output lines may simultaneously transmit data signals and electrical signals.

It is understood that the PoE system refers to a power over ethernet system that can support 10BASE-T, 100BASE-TX, 1000BASE-T, in which data signals and electrical signals are transmitted over the same network line.

In the embodiment of the present application, the PSE 11 is a device for supplying power to an ethernet client device, and is also a manager of the power over ethernet process in the entire PoE system. In general, the PSE 11 may be classified into two types. One type is an end-spanning device (end PSE), which may be, for example, an ethernet switch, router, hub, or other network switching device that supports PoE functionality; another type is midspan PSE, which is a specialized power management device, usually located with the switch, with two jacks per port, one stub connected to the switch and the other to the remote PD. Optionally, the PSE 11 may be a network device such as a PoE switch, a PoE router, a PoE wireless controller (WLAN product), a wireless baseband processing unit, and a microwave power supply integrity module, and the embodiment of the present application does not specifically limit the specific representation form of the PSE 11.

The PD 12 referred to in the embodiments of the present application is a device that receives power, i.e., a client device in the PoE system, such as an IP phone, a network security camera, an access point and network telephone, a home switch, a mobile phone charger, and many other ethernet devices (in fact, any device with power no more than 13W can obtain corresponding power from an RJ45 socket). For convenience of description, in all embodiments of the present application, the above-mentioned device for receiving power from the PSE 11 is collectively referred to as the PD 12.

In the embodiments of the present application, "a plurality" means two or more.

The embodiment of the application provides a signal reliability detection method, a PSE chip, a CPU chip and PoE equipment aiming at the problems that the transmission distance of an electric signal is shortened and the reliability of a data signal is reduced due to unbalanced resistance in a PoE system, and whether the signal in the PoE system can be reliably transmitted is further required to be judged. The technical solution of the present application will be described in detail below with reference to specific examples.

It should be noted that the following specific embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

Fig. 2 is a schematic flowchart of a first embodiment of a signal reliability detection method according to an embodiment of the present application. The execution main body of the method may be PoE device integrated with PSE chip and CPU chip, or CPU chip of central processing unit with PoE function, or other network device with PoE function, which is not limited in the embodiment of the present application.

For example, the embodiment of the present application is explained by taking a PoE device integrated with a PSE chip and a CPU chip as an execution subject of the signal reliability detection method. In practical applications, the PoE device refers to the above-mentioned power sourcing equipment PSE. Specifically, as shown in fig. 2, the signal reliability detecting method may include the following steps:

step 21: the PoE equipment detects whether a PD exists in a system where the PoE equipment is located.

In this embodiment, when a signal (an electrical signal and a data signal) needs to be transmitted through a certain output line pair in the PoE device, it is first necessary to ensure that a PD exists in the system where the PoE device is located.

For example, when the PoE device starts to operate, a target port is used to output a small voltage, and an impedance value and a capacitance value between any two output line pairs on the target port are obtained, and when the impedance value is within a preset impedance range and the capacitance value meets a preset capacitance condition, it can be determined that a PD exists in a system where the PoE device is located. Wherein the two output line pairs may form a supply loop. The target port is any one of all ports that the PoE device has, and the PoE device can transmit signals over a certain output line pair on the target port.

Illustratively, in this embodiment, the voltage output by the PoE device in the detection phase may be 2.8V to 10V, and the voltage polarity is consistent with the output of-48V. The predetermined impedance range may be 19K to 26.5Kohm and the predetermined capacitance condition may be less than or equal to 150 nF.

Step 22: when a system where PoE equipment is located has a PD, the PoE equipment sends an automatic classification waveform, and the automatic classification waveform is used for indicating that the power of the PD of the receiving end equipment in the system where the PoE equipment is located is increased to the maximum.

Optionally, in this embodiment, after determining that there is a PD in the system where the PoE device is located, the PoE device may classify the PD device, and evaluate a power consumption required by the PD device.

As an example, after determining that there is a PD in the system where the PoE device is located, the PoE device may continuously send an automatic classification waveform to the PD, where the automatic classification waveform is used to indicate that the power of the PD in the system where the PoE device is located is raised to the maximum, so that when the power of the PD in the system where the PoE device is located is at the maximum, it may be determined whether the output line pair of the PoE device is capable of reliably transmitting a signal, that is, when the loss of the data signal in the output line pair is the maximum, the reliability of the output line pair transmitting the signal is determined, which may further improve the accuracy of the result of the signal reliability detection method.

Step 23: the PoE equipment acquires the bias current of a target output line pair at the primary coil side of the transformer.

The transformer is a transformer corresponding to a target port of the Ethernet power supply PoE equipment.

Optionally, in this embodiment, when it is desired to determine whether a certain target output line of the target port of the PoE device is capable of reliably transmitting a signal, the bias current of the target output line pair on the primary coil side may be obtained by using the primary coil of the transformer corresponding to the target port, and then the bias current is further used for determining.

For example, the target output line pair may be any one of all output line pairs on the target port of the PoE device, and the embodiment of the present application is not limited to which one is specific.

As an example, in this embodiment, the step 23 (obtaining the bias current of the target output line pair on the primary coil side of the transformer) can be specifically realized by the following steps:

first, the PoE device collects the voltage across the primary coil side of the transformer.

Optionally, in a possible implementation manner, the PoE device includes a measurement circuit, and the measurement circuit is mainly responsible for measuring the bias current on the primary coil side of the transformer, and may be integrated in the PSE chip or the CPU chip, or may be separately disposed outside the PSE chip and the CPU chip. The present embodiment does not limit the specific existence manner of the measurement circuit as long as it can acquire the voltage across the primary coil side of the transformer.

In another possible implementation manner, an analog-to-digital conversion ADC chip may be included in the PoE device, and the voltage across the primary coil side of the transformer may be collected by using the ADC chip.

Secondly, the PoE equipment calculates the bias current of the target output line pair according to the voltage and the acquisition time point corresponding to the voltage.

In this embodiment, the measurement circuit or the ADC chip records the acquisition time point corresponding to the voltage at the two ends of the primary coil side of the transformer while acquiring the voltage. Optionally, the measurement circuit or the ADC chip may collect at least two voltages, determine collecting time points corresponding to the two voltages, and further use the at least two voltages and the at least two collecting time points corresponding to the at least two voltagesCalculating the bias current of the target output line pair, i.e.

Wherein, I_biasFor example, dV is a voltage variation of at least two collected voltages, dt is a time difference between two collection time points corresponding to the at least two collected voltages (i.e., a time duration corresponding to the voltage variation), and C is a capacitance value on the primary coil side of the transformer.

For example, the collection time point in this embodiment may be a time point determined when the PoE device acquires the voltage, or may be an agreed collection time point when the PoE device acquires the voltage at a specified time point according to a preset policy. The determination scheme of the acquisition time point may be determined according to actual conditions, and this embodiment does not limit this.

Optionally, in this embodiment, before the PoE device calculates the bias current of the target output line pair according to the voltage and the acquisition time point corresponding to the voltage, the PoE device may further perform denoising processing on the acquired voltage at first, for example, perform denoising processing on the voltage by using a wavelet transform method, so as to improve reliability of determining whether the target output line can reliably transmit a signal, specifically:

and the PoE equipment carries out denoising processing on the voltage by using a wavelet transform method to obtain denoised voltage.

Illustratively, this step is actually performed by a CPU chip in the PoE device, that is, the CPU chip may acquire the voltage across the primary coil side of the transformer from the PSE chip through a bus (e.g., an IIC bus) and perform a wavelet transform process on the voltage after acquiring the voltage, and the wavelet transform process is effective in removing white noise and very suitable for processing non-stationary random signals.

For example, if the noise voltage in the system where the PoE device is located is represented by n (t), the actual voltage at both ends of the primary coil of the transformer is represented by u (t), and the collected voltage is represented by u (t), u (t) ═ u (t) + n (t). Using wavelet transform formulas

And performing wavelet transformation on the acquired voltage by using U (t) to obtain a wavelet transformation coefficient small WT (a, tau), wherein a represents a wavelet transformation scale, tau represents a wavelet transformation translation amount, and psi () represents a wavelet function.

Since the wavelet transform is characterized by small wavelet transform coefficient of noise and large wavelet transform coefficient of voltage signal, by setting a proper threshold λ, when the wavelet transform coefficient WT (a, τ) is greater than the threshold λ, the original wavelet transform coefficient can be retained, and if the wavelet transform coefficient WT (a, τ) is less than the threshold λ, the original wavelet transform coefficient is set to zero, so that the wavelet transform coefficient belonging to noise can be effectively filtered by such a threshold selection method.

And then, after the wavelet transform coefficient meeting the condition is extracted, the denoised voltage can be obtained through inverse wavelet transform, the denoised voltage effectively filters the noise of a system where the PoE is positioned, and the precision of voltage collection is improved.

Correspondingly, the step of calculating the bias current of the target output line pair according to the voltage and the acquisition time point corresponding to the voltage may be replaced by the following steps:

Optionally, the method for calculating the bias current according to the denoised voltage and the above-mentioned collection time point is similar to the method for calculating the bias current according to the collection time point corresponding to the voltage and the voltage, and is not described here again.

Step 24: and the PoE equipment acquires the corresponding relation between the bias current of the target output line pair and the voltage drop percentage.

In this embodiment, the storage chip of the PoE device may store a corresponding relationship between a bias current and a voltage drop percentage of an output line pair of a target port of the PoE device, and further, when it is necessary to determine whether a target output line can reliably transmit a signal, the CPU chip may directly receive the storage chip to obtain the corresponding relationship between the bias current and the voltage drop percentage of the target output line pair.

Step 25: and the PoE equipment determines the voltage drop percentage of the target output line pair according to the bias current and the corresponding relation between the bias current of the target output line pair and the voltage drop percentage.

In this embodiment, after the PoE device (actually, a CPU chip) acquires the bias current of the target output line pair on the primary coil side of the transformer, the voltage drop percentage of the target output line pair can be determined according to the corresponding relationship between the bias current of the target output line pair and the voltage drop percentage.

For example, in this embodiment, when the storage chip of the PoE device stores the correspondence between the unbalanced current and the voltage drop percentage of the output line pair, the PoE device may further calculate the unbalanced current of the target output line pair after acquiring the bias current of the target output line pair, and then determine the voltage drop percentage of the target output line pair according to the unbalanced current and the correspondence between the unbalanced current and the voltage drop percentage of the target output line pair.

It will be appreciated that the unbalance current is equal to twice the bias current, since it is used to represent the current between any two pairs of output lines forming the power supply loop, the bias current being the current of each wire in each pair of output lines.

Step 26: and the PoE equipment judges whether the target output line can reliably transmit signals or not according to the voltage drop percentage of the target output line pair and a preset voltage drop interval.

Optionally, a preset voltage drop interval is stored in a memory chip in the PoE device, and whether the target output line pair can reliably transmit the signal is determined according to whether the voltage drop percentage of the target output line pair is in the preset voltage drop interval.

Specifically, this step 26 can be implemented as follows:

firstly, judging whether the voltage drop percentage of the target output line pair is in a preset voltage drop interval, if so, determining that the target output line pair can reliably transmit signals, and if not, determining that the target output line pair cannot reliably transmit signals.

Assuming that the preset voltage drop interval is [0,0.2], that is, when a signal is transmitted by using the target output line pair, the voltage loss corresponding to the signal cannot exceed more than 20%. Therefore, if the determined voltage drop percentage of the target output line pair is less than or equal to 20%, that is, the voltage drop percentage is within the preset voltage drop interval [0,0.2], it may be determined that the target output line pair is capable of reliably transmitting signals, and if the voltage drop percentage of the target output line pair is greater than 20%, that is, the voltage drop percentage exceeds the preset voltage drop interval [0,0.2], it may be determined that the target output line pair is incapable of reliably transmitting signals.

For example, fig. 3 is a graph illustrating the relationship between the bias current and the ratio of the target output line to the output voltage. As shown in fig. 3, the abscissa represents a bias current (mA), the ordinate represents an output voltage ratio of a target output line pair, which is a ratio of an output voltage of the target output line pair to an input voltage, and the output voltage ratio of the target output line pair decreases as the bias current flowing through the target output line pair increases.

Illustratively, when the preset voltage sag interval is [0,0.2], referring to fig. 3, in the schematic diagram shown in fig. 3, the upper threshold and the lower threshold of the preset voltage sag interval are 1 and 0.8, that is, the output voltage ratio of the target output line pair needs to be between 0.8 and 1. That is, when the voltage drop percentage of the target output line pair is 15%, the output voltage ratio of the target output line pair is 0.85, which is between 0.8 and 1, it is determined that the target output line pair can reliably transmit signals, and when the voltage drop percentage of the target output line pair is 25%, the output voltage ratio of the target output line pair is 0.75, which is not in the range of 0.8 to 1, and therefore, it is determined that the target output line pair cannot reliably transmit signals.

It should be noted that the corresponding relationship between the bias current and the output voltage ratio is different for different output line pairs with the same transmission rate, and the corresponding relationship between the bias current and the output voltage ratio is also different for the same output line pair with different transmission rates.

Illustratively, referring to fig. 3, a curve 1 represents a bias current versus output voltage ratio for a first output line pair having a transmission rate of 1000BASE-T, a curve 2 represents a bias current versus output voltage ratio for a second output line pair having a transmission rate of 1000BASE-T, a curve 3 represents a bias current versus output voltage ratio for a third output line pair having a transmission rate of 1000BASE-T, and a curve 4 represents a bias current versus output voltage ratio for a fourth output line pair having a transmission rate of 1000 BASE-T. Curve 5 represents the bias current to output voltage ratio for the second output line pair with a transmission rate of 100BASE-TX, curve 6 represents the bias current to output voltage ratio for the third output line pair with a transmission rate of 100BASE-TX, and line 7 represents the lower limit of the output voltage ratio.

Illustratively, in this embodiment, the method may further include the steps of:

step 27: and if the PoE equipment determines that the target output line pair cannot reliably transmit signals, the PoE equipment sends out alarm information.

Wherein the alarm information is used for indicating that the target output line pair cannot reliably transmit signals.

Optionally, in this embodiment, the CPU chip in the PoE device finally determines whether the target output line can reliably transmit the signal, and when it determines that the target output line pair cannot reliably transmit the signal, sends an alarm message through the input/output interface of the CPU chip, and then notifies the network management device that the target output line pair cannot reliably transmit the signal, so that the network personnel or the network management device take corresponding measures.

In the method for detecting signal reliability provided in the embodiment of the present application, a PoE device first obtains a bias current of a target output line pair on a primary coil side of a transformer, where the transformer is a transformer corresponding to a target port of a PoE device powered by ethernet, determines a voltage drop percentage of the target output line pair according to the bias current and a corresponding relationship between the bias current and the voltage drop percentage of the target output line pair, and finally determines whether the target output line can reliably transmit a signal according to the voltage drop percentage of the target output line pair and a preset voltage drop interval. The technical scheme can judge whether the output line in the system where the PoE equipment is located can reliably transmit signals, and improves the signal stability of the PoE system.

It can be understood that the technical scheme of the embodiment of the application can solve the problem that the signal transmission reliability is influenced by unbalanced power supply in a PoE system, and the early warning information is given when the reliability is low by combining the actual wiring condition of a client, so that the method has a guiding effect on the wiring in a power supply service scene with high power and high port rate combination.

Fig. 4 is an interaction flowchart of a second embodiment of a signal reliability detection method according to the embodiment of the present application. The embodiment is described by information interaction between a PSE chip and a CPU chip in a PoE device. Specifically, as shown in fig. 4, the method may include the following steps:

step 41: the PSE chip detects whether the system of the PoE equipment has the PD.

Step 42: when a PD exists in a system where the PoE equipment is located, the PSE chip sends an automatic classification waveform to the PD.

Wherein the automatic classification waveform is used to indicate that the power of the PD in the system in which the PoE device is located is maximized.

When the PD is at the maximum power, the signal transmitted by the target output line of the target port of the PoE equipment has the maximum distortion, namely, when the reliability of the signal transmitted by the target output line is evaluated under the condition of the most serious signal distortion, the accuracy of the judgment result can be improved.

Step 43: when the PSE chip detects that the power of the PD is increased to the maximum, the PSE chip acquires the bias current of a target output line pair on the primary coil side of the transformer.

The transformer is a transformer corresponding to a target port of the PoE equipment.

As an example, this step 43 can be implemented by the following steps 431 and 432:

step 431: the PSE chip collects the voltage across the primary side of the transformer.

In this embodiment, the target output pair of the target port of the PSE chip may be connected to a transformer. Optionally, in an implementation possible manner, both ends of the primary coil side of the transformer may be connected to a measurement circuit integrated in the PSE chip, and in another implementation possible manner, both ends of the primary coil side of the transformer may also be connected to a measurement circuit independent of the PSE chip.

Step 432: and the PSE chip calculates the bias current of the target output line pair according to the voltage and the acquisition time point corresponding to the voltage.

Optionally, when the PSE chip collects the voltages at the two ends of the primary coil side of the transformer, a collection time point corresponding to each voltage value is also determined, and the bias current of the target output line pair can be calculated according to the relationship between the bias current and the voltages and capacitance values at the two ends of the primary coil side. For a specific calculation method, reference may be made to the content recorded in step 23 in the embodiment shown in fig. 2, and details are not repeated here.

Step 44: the PSE chip sends the bias current to a CPU chip provided in the PoE device.

In this embodiment, the PSE chip sends the bias current to the CPU chip, so that the CPU chip can determine whether the target output line can reliably transmit the signal according to the bias current.

Step 45: and the CPU chip acquires the corresponding relation between the bias current and the voltage drop percentage of the target output line pair.

In this embodiment, when the CPU chip receives the bias current of the target output line pair, the CPU chip may obtain the correspondence between the bias current and the voltage drop percentage of the target output line pair by querying the memory chip storing the correspondence between the bias current and the voltage drop percentage of the output line pair of the target port according to the target output line pair.

Step 46: and the CPU chip determines the voltage drop percentage of the target output line pair according to the bias current and the corresponding relation between the bias current and the voltage drop percentage of the target output line pair.

In this embodiment, after the corresponding relationship between the bias current and the voltage drop percentage of the target output line pair is obtained in step 45, the voltage drop percentage of the target output line pair can be conveniently determined by combining the bias current.

Step 47: and the CPU chip judges whether the target output line can reliably transmit signals according to the voltage drop percentage of the target output line pair and a preset voltage drop interval.

Illustratively, this step 47 may be specifically implemented by the following steps:

the CPU chip judges whether the voltage drop percentage of the target output line pair is within a preset voltage drop interval or not, and if yes, the target output line pair is determined to be capable of reliably transmitting signals; if not, determining that the target output line pair cannot reliably transmit signals.

For the specific determination process, reference may be made to the description in step 26 and the description of fig. 3, which are not described herein again.

And 48: and the CPU chip sends out alarm information when determining that the target output line pair cannot reliably transmit signals.

For example, in this embodiment, when determining that the target output line pair cannot reliably transmit a signal, the CPU chip sends an alarm message through the output interface, and then notifies the network management device that the target output line pair cannot reliably transmit a signal, so that the network personnel or the network management device takes corresponding measures.

For the steps that are not explained in detail in the embodiments of the present application, reference may be made to the description of the embodiment shown in fig. 2, and further description is omitted here.

The signal reliability detection method provided in this embodiment is described by interaction between a PSE chip and a CPU chip in PoE equipment, that is, the PSE chip obtains a bias current of a target output line pair on a primary coil side of a transformer, and sends the bias current to the CPU chip arranged in the PoE equipment, after receiving the bias current, the CPU chip determines a voltage drop percentage of the target output line pair according to the bias current and a corresponding relationship between the bias current and the voltage drop percentage of the target output line pair, and determines whether the target output line can reliably transmit a signal according to the voltage drop percentage of the target output line pair and a preset voltage drop interval. The technical scheme can judge whether the output line in the system where the PoE equipment is located can reliably transmit signals, and reduces the error code probability when the system where the PoE equipment is located transmits signals.

Fig. 5 is an interaction flowchart of a third embodiment of a signal reliability detection method provided in the embodiment of the present application. Similar to fig. 4, the present embodiment is also explained by information interaction between a PSE chip and a CPU chip in a PoE device, and fig. 5 and fig. 4 only differ in that the PSE chip in fig. 4 not only collects voltages at two ends of a primary coil side of a transformer, but also calculates a bias current of a target output line pair, and sends the bias current to the CPU chip, and after collecting the voltages at two ends of the primary coil side of the transformer, the PSE chip in fig. 5 directly sends the voltages to the CPU chip, and the voltages are used for the CPU chip to calculate the bias current.

Specifically, as shown in fig. 5, the method of this embodiment may include the following steps:

step 51: the PSE chip detects whether the system of the PoE equipment has the PD.

Step 52: when a PD exists in a system where the PoE equipment is located, the PSE chip sends an automatic classification waveform to the PD.

Step 53: when detecting that the power of the PD is increased to the maximum, the PSE chip collects the voltage at two ends of the primary coil side of the transformer.

Step 54: the PSE chip sends the voltage to the CPU chip.

In this embodiment, the PSE chip sends the voltage to the CPU chip so that the CPU chip can determine whether the target output line can reliably transmit the signal according to the voltage.

Step 55: and the CPU chip calculates the bias current of the target output line pair according to the voltage and the acquisition time point corresponding to the voltage.

Optionally, before step 55, the method further includes:

the CPU chip utilizes a wavelet transformation method to perform denoising processing on the voltage to obtain denoised voltage.

Accordingly, step 55 may be replaced with: and calculating the bias current according to the denoised voltage and the acquisition time point.

Step 56: and the CPU chip acquires the corresponding relation between the bias current and the voltage drop percentage of the target output line pair.

And 57: and the CPU chip determines the voltage drop percentage of the target output line pair according to the bias current and the corresponding relation between the bias current and the voltage drop percentage of the target output line pair.

Step 58: and the CPU chip judges whether the target output line can reliably transmit signals according to the voltage drop percentage of the target output line pair and a preset voltage drop interval.

Illustratively, this step 58 may be specifically realized by the following steps:

Step 59: and the CPU chip sends out alarm information when determining that the target output line pair cannot reliably transmit signals.

For the steps that are not explained in detail in the embodiments of the present application, reference may be made to the descriptions of the embodiments shown in fig. 2 or fig. 4, which are not described herein again.

In the method for detecting signal reliability provided by this embodiment, a PSE chip disposed in a PoE device collects voltages at two ends of a target output line pair on a primary coil side of a transformer, and sends the voltages to a CPU chip disposed in the PoE device, and after receiving the voltages, the CPU chip calculates a bias current of the target output line pair according to the collection time points corresponding to the voltages and the voltages, determines a voltage drop percentage of the target output line pair according to the bias current and a correspondence between the bias current and the voltage drop percentage of the target output line pair, and determines whether the target output line can reliably transmit signals according to the voltage drop percentage of the target output line pair and a preset voltage drop interval. The technical scheme can also judge whether the output line in the system where the PoE equipment is located can reliably transmit signals, and reduces the error code probability when the system where the PoE equipment is located transmits signals.

Fig. 6 is a schematic structural diagram of a first embodiment of a signal reliability detection apparatus according to an embodiment of the present application. The apparatus may be adapted for use with PoE devices. As shown in fig. 6, the apparatus may include: a processing module 61 and a decision module 62.

The processing module 61 is configured to obtain a bias current of a target output line pair on a primary coil side of the transformer.

Illustratively, the transformer is a transformer corresponding to a target port of the PoE device, and the voltage drop percentage of the target output line pair is determined according to the bias current and a corresponding relationship between the bias current and the voltage drop percentage of the target output line pair.

The judging module 62 is configured to judge whether the target output line can reliably transmit the signal according to the voltage drop percentage of the target output line pair and a preset voltage drop interval.

Optionally, in a possible implementation manner of this embodiment, the processing module 61 is configured to obtain a bias current of a target output line pair on a primary coil side of a transformer, and specifically, the bias current is:

the processing module 61 is specifically configured to acquire voltages at two ends of a primary coil side of the transformer, and calculate a bias current of the target output line pair according to the voltages and acquisition time points corresponding to the voltages.

Optionally, in the foregoing possible implementation manner of this embodiment, the processing module 61 is further configured to perform denoising processing on the voltage by using a wavelet transform method before calculating the bias current of the target output line pair according to the voltage and the acquisition time point corresponding to the voltage, so as to obtain a denoised voltage;

correspondingly, the processing module 61 is configured to calculate a bias current of the target output line pair according to the voltage and the acquisition time point corresponding to the voltage, specifically:

the processing module 61 is specifically configured to calculate the bias current according to the denoised voltage and the acquisition time point.

Optionally, in another possible implementation manner of this embodiment, the apparatus further includes: and an output module.

The output module is configured to send an automatic classification waveform before the processing module 61 obtains the bias current of the target output line pair on the primary coil side of the transformer, where the automatic classification waveform is used to indicate that the power of the power receiving device PD in the system where the PoE device is located is increased to the maximum.

Optionally, in another possible implementation manner of this embodiment, the processing module 61 is further configured to obtain a corresponding relationship between the bias current and the voltage drop percentage of the target output line pair.

Optionally, in another possible implementation manner of this embodiment, the determining module 62 is configured to determine whether the target output line pair can reliably transmit the signal according to the voltage drop percentage of the target output line pair and a preset voltage drop interval, and specifically includes:

the determining module 62 is specifically configured to determine whether the voltage drop percentage of the target output line pair is in the preset voltage drop interval, and determine that the target output line pair can reliably transmit signals when the voltage drop percentage of the target output line pair is in the preset voltage drop interval, otherwise, determine that the target output line pair cannot reliably transmit signals.

Correspondingly, the output module is configured to send out warning information after the determining module 62 determines that the target output line pair cannot reliably transmit the signal, where the warning information is used to indicate that the target output line pair cannot reliably transmit the signal.

The device for detecting reliability of different signals of this embodiment may be used to implement the implementation scheme of the method embodiment shown in fig. 2, and the specific implementation manner and the technical effect are similar and will not be described herein again.

Fig. 7 is a schematic structural diagram of a second embodiment of a signal reliability detection apparatus according to an embodiment of the present application. The apparatus may be applied to a Power Sourcing Equipment (PSE) chip disposed in a power over Ethernet (PoE) device, and as shown in FIG. 6, the apparatus may include: a processing module 71 and an output module 72.

The processing module 71 is configured to obtain a bias current of a target output line pair on a primary coil side of a transformer, where the transformer is a transformer corresponding to a target port of the PoE device.

The output module 72 is configured to send the bias current to a CPU chip disposed in the PoE device, where the bias current is used for the CPU chip to determine whether the target output line pair can reliably transmit a signal.

Optionally, in a possible implementation manner of this embodiment, the processing module 71 is configured to obtain a bias current of a target output line pair on a primary coil side of a transformer, and specifically, the bias current is:

the processing module 71 is configured to acquire voltages at two ends of the primary coil side of the transformer, and calculate a bias current of the target output line pair according to the voltages and acquisition time points corresponding to the voltages.

Optionally, in another possible implementation manner of this embodiment, the output module 72 is further configured to send an automatic classification waveform before the processing module obtains the bias current of the target output line pair on the primary coil side of the transformer, where the automatic classification waveform is used to instruct the power of the power receiving end device PD in the system where the PoE device is located to be increased to the maximum.

The device provided by this embodiment may be used to implement the technical scheme of the PSE chip in the method embodiment shown in fig. 4, and the specific implementation manner and technical effect are similar and will not be described herein again.

Fig. 8 is a schematic structural diagram of a third embodiment of a signal reliability detection apparatus according to an embodiment of the present application. The device can be applied to a Central Processing Unit (CPU) chip arranged in a power over Ethernet (PoE) device. As shown in fig. 8, the apparatus may include: an input-output module 81, a processing module 82 and a decision module 83.

The input/output module 81 is configured to receive a bias current sent by a PSE chip of a power supply device in the PoE device, where the bias current is a current of a target output line pair on a primary coil side of a transformer, and the transformer is a transformer corresponding to a target port of the PoE device;

the processing module 82 is configured to determine a voltage drop percentage of the target output line pair according to the bias current and a corresponding relationship between the bias current and the voltage drop percentage of the target output line pair;

the judging module 83 is configured to judge whether the target output line can reliably transmit the signal according to the voltage drop percentage of the target output line pair and a preset voltage drop interval.

Optionally, in a possible implementation manner of this embodiment, the processing module 82 is further configured to obtain a corresponding relationship between the bias current and the voltage drop percentage of the target output line pair.

Optionally, in another possible implementation manner of this embodiment, the determining module 83 is configured to determine whether the target output line can reliably transmit the signal according to the voltage drop percentage of the target output line pair and a preset voltage drop interval, and specifically includes:

the determining module 83 is specifically configured to determine whether the voltage drop percentage of the target output line pair is in the preset voltage drop interval, and determine that the target output line pair can reliably transmit signals when the voltage drop percentage of the target output line pair is in the preset voltage drop interval, otherwise, determine that the target output line pair cannot reliably transmit signals.

Optionally, in the foregoing possible implementation manner of this embodiment, the input/output module 81 is further configured to send alarm information after the determining module determines that the target output line pair cannot reliably transmit the signal, where the alarm information is used to indicate that the target output line pair cannot reliably transmit the signal.

The apparatus provided in this embodiment may be used to execute the technical solution of the CPU chip in the method embodiment shown in fig. 4, and the specific implementation manner and the technical effect are similar and will not be described herein again.

It should be noted that the division of the modules of the above apparatus is only a logical division, and the actual implementation may be wholly or partially integrated into one physical entity, or may be physically separated. And these modules can be realized in the form of software called by processing element; or may be implemented entirely in hardware; and part of the modules can be realized in the form of calling software by the processing element, and part of the modules can be realized in the form of hardware. For example, the determining module may be a processing element separately set up, or may be implemented by being integrated in a chip of the apparatus, or may be stored in a memory of the apparatus in the form of program code, and the function of the determining module is called and executed by a processing element of the apparatus. Other modules are implemented similarly. In addition, all or part of the modules can be integrated together or can be independently realized. The processing element described herein may be an integrated circuit having signal processing capabilities. In implementation, each step of the above method or each module above may be implemented by an integrated logic circuit of hardware in a processor element or an instruction in the form of software.

For example, the above modules may be one or more integrated circuits configured to implement the above methods, such as: one or more Application Specific Integrated Circuits (ASICs), or one or more microprocessors (DSPs), or one or more Field Programmable Gate Arrays (FPGAs), among others. For another example, when some of the above modules are implemented in the form of a processing element scheduler code, the processing element may be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor that can call program code. As another example, these modules may be integrated together, implemented in the form of a system-on-a-chip (SOC).

In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the application to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a readable storage medium or transmitted from one readable storage medium to another readable storage medium, for example, the computer instructions may be transmitted from one website site, computer, server, or data center to another website site, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The readable storage medium may be any available medium that can be accessed by a computer or a data storage device including one or more available media integrated servers, data centers, and the like. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.

FIG. 9 is a simplified schematic diagram of one possible design structure of a PSE chip involved in an embodiment of the present application. The PSE chip is disposed in a PoE device, as shown in fig. 9, and may include: measurement circuitry 91, processor 82 and output interface 93.

The measurement circuit 91 is configured to measure voltages at two ends of a target output line pair on a primary coil side of a transformer, where the transformer is a transformer corresponding to a target port of the PoE device;

the processor 92 is configured to calculate a bias current of the target output line pair according to the voltage and the acquisition time point corresponding to the voltage;

the output interface 93 is configured to send the bias current to a CPU chip of a central processing unit, where the bias current is used for the CPU chip to determine whether the target output line pair can reliably transmit a signal.

Optionally, in a possible implementation manner of this embodiment, the output interface 93 is further configured to send an automatic classification waveform before the measurement circuit 91 measures and collects the voltage across the target output line pair on the primary coil side of the transformer, where the automatic classification waveform is used to indicate that the power of the power receiving device PD in the system where the PoE device is located is raised to the maximum.

The PSE chip provided in this embodiment may be used to implement the technical scheme of the PSE chip in the method embodiment shown in fig. 4, and the specific implementation and technical effects are similar and will not be described herein again.

Fig. 10 is a simplified schematic diagram of a possible design structure of a CPU chip according to an embodiment of the present application. The CPU chip is disposed in the PoE device, as shown in fig. 10, and may include: input/output interface 101, processor 102.

The input/output interface 101 is configured to receive a bias current sent by a PSE chip of a power source device in PoE equipment, where the bias current is a current of a target output line pair on a primary coil side of a transformer, and the transformer is a transformer corresponding to a target port of the PoE equipment;

the processor 102 is configured to determine a voltage drop percentage of the target output line pair according to the bias current and a corresponding relationship between the bias current and the voltage drop percentage of the target output line pair, and determine whether the target output line can reliably transmit a signal according to the voltage drop percentage of the target output line pair and a preset voltage drop interval.

Optionally, in a possible implementation manner of this embodiment, the processor 102 is further configured to obtain a corresponding relationship between the bias current and the voltage drop percentage of the target output line pair.

Optionally, in another possible implementation manner of this embodiment, the processor 102 is configured to determine whether the target output line pair can reliably transmit the signal according to the voltage drop percentage of the target output line pair and a preset voltage drop interval, and specifically includes:

the processor 102 is specifically configured to determine whether the voltage drop percentage of the target output line pair is within the preset voltage drop interval, and determine that the target output line pair can reliably transmit signals when the voltage drop percentage of the target output line pair is within the preset voltage drop interval, otherwise, determine that the target output line pair cannot reliably transmit signals.

Optionally, in the foregoing possible implementation manner of this embodiment, the input/output interface 101 is further configured to send an alarm message after the processor 102 determines that the target output line pair cannot reliably transmit a signal, where the alarm message is used to indicate that the target output line pair cannot reliably transmit a signal.

The CPU chip provided in this embodiment may be used to execute the technical solution of the CPU chip in the method embodiment shown in fig. 4, and the specific implementation manner and the technical effect are similar and will not be described herein again.

FIG. 11 is a simplified schematic diagram of another possible design structure of a PSE chip involved in an embodiment of the present application. The PSE chip is disposed in a PoE device, as shown in fig. 11, and may include: a measurement circuit 111 and an output interface 112.

The measurement circuit 111 is configured to collect voltages at two ends of a target output line pair on a primary coil side of a transformer, where the transformer is a transformer corresponding to a target port of the PoE device;

the output interface 112 is configured to send the voltage to a CPU chip, where the voltage is used for the CPU chip to calculate a bias current of the target output line pair, and determine whether the target output line pair can reliably transmit a signal according to the bias current.

Optionally, in a possible implementation manner of this embodiment, the output interface 112 is further configured to send an automatic classification waveform before the measurement circuit 111 measures and collects the voltage across the target output line pair on the primary coil side of the transformer, where the automatic classification waveform is used to indicate that the power of the power receiving device PD in the system where the PoE device is located is raised to the maximum.

The PSE chip provided in this embodiment may be used to implement the technical scheme of the PSE chip in the method embodiment shown in fig. 5, and the specific implementation and technical effects are similar and will not be described here again.

Fig. 12 is a simplified schematic diagram of another possible design structure of the CPU chip according to the embodiment of the present application. The CPU chip is disposed in the PoE device, as shown in fig. 12, and may include: input/output interface 121, processor 122.

The input/output interface 121 is configured to receive a voltage sent by a PSE chip of a power supply device in the PoE device, where the voltage is a voltage at two ends of a target output line pair on a primary coil side of a transformer, and the transformer is a transformer corresponding to a target port of the PoE device;

the processor 122 is configured to calculate a bias current of the target output line pair according to the voltage and the acquisition time point corresponding to the voltage, determine a voltage drop percentage of the target output line pair according to the bias current and a corresponding relationship between the bias current and the voltage drop percentage of the target output line pair, and determine whether the target output line can reliably transmit a signal according to the voltage drop percentage of the target output line pair and a preset voltage drop interval.

Optionally, in a possible implementation manner of this embodiment, the processor 122 is further configured to perform denoising processing on the voltage by using a wavelet transform method before calculating the bias current of the target output line pair according to the voltage and the acquisition time point corresponding to the voltage, so as to obtain a denoised voltage;

correspondingly, the processor 122 is configured to calculate a bias current of the target output line pair on the primary coil side of the transformer according to the voltage and the acquisition time point corresponding to the voltage, specifically:

the processor 122 is specifically configured to calculate the bias current according to the denoised voltage and the acquisition time point.

Optionally, in another possible implementation manner of this embodiment, the processor 122 is further configured to obtain a corresponding relationship between the bias current and the voltage drop percentage of the target output line pair.

Optionally, in another possible implementation manner of this embodiment, the processor 122 is configured to determine whether the target output line pair can reliably transmit the signal according to the voltage drop percentage of the target output line pair and a preset voltage drop interval, and specifically includes:

the processor 122 is specifically configured to determine whether a voltage drop percentage of the target output line pair is within the preset voltage drop interval, determine that the target output line pair can reliably transmit signals if the voltage drop percentage is within the preset voltage drop interval, and determine that the target output line pair cannot reliably transmit signals if the voltage drop percentage is not within the preset voltage drop interval.

Optionally, in the foregoing possible implementation manner of this embodiment, the input/output interface 121 is further configured to send an alarm message after the processor 122 determines that the target output line pair cannot reliably transmit a signal, where the alarm message is used to indicate that the target output line pair cannot reliably transmit a signal.

The CPU chip provided in this embodiment may be used to execute the technical solution of the CPU chip in the method embodiment shown in fig. 5, and the specific implementation manner and the technical effect are similar and will not be described herein again.

Fig. 13 is a schematic composition diagram of a PoE device according to an embodiment of the present application. As shown in fig. 13, the PoE device may include at least: PSE chip 131 and CPU chip 132.

As an example, the PSE chip 131 may be the PSE chip shown in fig. 9 and the CPU chip 132 may be the CPU chip shown in fig. 10.

As another example, the PSE chip 131 may be the PSE chip shown in fig. 11 and the CPU chip 132 may be the CPU chip shown in fig. 12.

For example, the PSE chip 131 and the CPU chip 132 may exchange data via an IIC bus.

The PoE device of this embodiment may include: a measurement circuit. The measurement circuit may be independent of the PSE chip 131 and the CPU chip 132, or may be integrated in the PSE chip 131 or in the CPU chip 132. The measurement circuit is used for collecting voltages at two ends of a primary coil side of a transformer corresponding to a target port of the PoE equipment.

Optionally, the PoE device may further include: a memory chip. The memory chip may be provided in the PoE device separately from the PSE chip 131 and the CPU chip 132, or may be integrated in the CPU chip 132. The storage chip is used for storing the corresponding relation between the bias current and the voltage drop percentage of an output line pair at the side of a primary coil of a transformer corresponding to a PoE device port.

It is to be understood that the various numerical references referred to in the embodiments of the present application are merely for descriptive convenience and are not intended to limit the scope of the embodiments of the present application.

It should be understood that, in the embodiment of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiment of the present application.

Claims

1. A method for signal reliability detection, the method comprising:

2. The method of claim 1, wherein obtaining the bias current of the target output line pair on the primary winding side of the transformer comprises:

collecting voltages at two ends of the primary coil side of the transformer;

3. The method of claim 2, wherein prior to said calculating a bias current for said target output line pair based on said voltage and a collection time point corresponding to said voltage, said method further comprises:

4. The method of any of claims 1-3, wherein prior to said obtaining a bias current for a target output line pair on a primary side of a transformer, the method further comprises:

5. The method according to any one of claims 1-3, further comprising:

6. The method according to any one of claims 1-3, wherein said determining whether the target output line pair can reliably transmit the signal according to the voltage drop percentage of the target output line pair and a preset voltage drop interval comprises:

7. The method of claim 6, wherein after said determining that the target output line pair is not capable of reliably transmitting signals, the method further comprises:

8. A signal reliability detection method is characterized in that the method is suitable for a power supply equipment PSE chip arranged in a power over Ethernet (PoE) device, and the method comprises the following steps:

sending the bias current to a Central Processing Unit (CPU) chip arranged in the PoE equipment, so that the CPU chip determines the voltage drop percentage of the target output line pair according to the bias current and the corresponding relation between the bias current and the voltage drop percentage of the target output line pair; and judging whether the target output line can reliably transmit signals or not according to the voltage drop percentage of the target output line pair and a preset voltage drop interval.

9. The method of claim 8, wherein obtaining the bias current of the target output line pair on the primary winding side of the transformer comprises:

collecting voltages at two ends of the primary coil side of the transformer;

10. The method of claim 8 or 9, wherein prior to said obtaining a bias current of a target output line pair on a primary winding side of a transformer, the method further comprises:

11. A signal reliability detection method is characterized in that the method is suitable for a Central Processing Unit (CPU) chip arranged in a power over Ethernet (PoE) device, and the method comprises the following steps:

12. The method of claim 11, further comprising:

13. The method according to claim 11 or 12, wherein said determining whether the target output line pair can reliably transmit the signal according to the voltage drop percentage of the target output line pair and a preset voltage drop interval comprises:

14. The method of claim 13, wherein after said determining that the target output line pair is not capable of reliably transmitting signals, the method further comprises:

15. A Power Sourcing Equipment (PSE) chip is arranged in a power over Ethernet (PoE) device, and is characterized by comprising: a measurement circuit, a processor and an output interface;

the output interface is used for sending the bias current to a Central Processing Unit (CPU) chip so that the CPU chip determines the voltage drop percentage of the target output line pair according to the bias current and the corresponding relation between the bias current and the voltage drop percentage of the target output line pair; and judging whether the target output line can reliably transmit signals or not according to the voltage drop percentage of the target output line pair and a preset voltage drop interval.

16. The PSE chip of claim 15, wherein the output interface is further configured to send an auto-classification waveform to instruct a power-receiving device PD in the system of the PoE device to maximize power before the measurement circuit measures and collects a voltage across the target output pair on the primary winding side of the transformer.

17. A Central Processing Unit (CPU) chip, the CPU chip is arranged in a power over Ethernet (PoE) device, and the CPU chip comprises: an input/output interface and a processor;

18. The CPU chip of claim 17, wherein the processor is further configured to obtain a correspondence between a bias current and a voltage drop percentage of the target output line pair.

19. The CPU chip according to claim 17 or 18, wherein the processor is configured to determine whether the target output line pair can reliably transmit a signal according to a voltage drop percentage of the target output line pair and a preset voltage drop interval, and specifically:

20. The CPU chip of claim 19, wherein the input/output interface is further configured to issue an alarm message after the processor determines that the target output line pair cannot reliably transmit a signal, the alarm message indicating that the target output line pair cannot reliably transmit a signal.

21. A Power Sourcing Equipment (PSE) chip is arranged in a power over Ethernet (PoE) device, and is characterized by comprising: a measurement circuit and an output interface;

the output interface is used for sending the voltage to a Central Processing Unit (CPU) chip so that the CPU chip determines the voltage drop percentage of the target output line pair according to the bias current and the corresponding relation between the bias current and the voltage drop percentage of the target output line pair; and judging whether the target output line can reliably transmit signals or not according to the voltage drop percentage of the target output line pair and a preset voltage drop interval.

22. The PSE chip of claim 21, wherein the output interface is further configured to send an auto-classification waveform to instruct a power-receiving device PD in the system of the PoE device to maximize power before the measurement circuit measures and collects a voltage across the target output pair on the primary winding side of the transformer.

23. A Central Processing Unit (CPU) chip, the CPU chip is arranged in a power over Ethernet (PoE) device, and the CPU chip comprises: an input/output interface and a processor;

24. The CPU chip of claim 23, wherein the processor is further configured to perform denoising processing on the voltage by using a wavelet transform method before calculating the bias current of the target output line pair according to the voltage and the acquisition time point corresponding to the voltage, so as to obtain a denoised voltage;

25. The CPU chip of claim 23 or 24, wherein the processor is further configured to obtain a correspondence between a bias current and a voltage drop percentage of the target output line pair.

26. The CPU chip according to claim 23 or 24, wherein the processor is configured to determine whether the target output line pair can reliably transmit a signal according to a voltage drop percentage of the target output line pair and a preset voltage drop interval, and specifically:

27. The CPU chip of claim 26, wherein the input/output interface is further configured to issue an alarm message after the processor determines that the target output line pair cannot reliably transmit signals, the alarm message indicating that the target output line pair cannot reliably transmit signals.

28. A power over ethernet, PoE, device, comprising: at least comprises the following steps: the power supply end equipment comprises a PSE chip and a CPU chip;

the PSE chip is the PSE chip of claim 15 or 16, the CPU chip is the CPU chip of any one of claims 17 to 20;

or

The PSE chip is the PSE chip of claim 21 or 22, and the CPU chip is the CPU chip of any one of claims 23 to 27.