CN111078618A - Electronic device and communication method of dual processors - Google Patents
Electronic device and communication method of dual processors Download PDFInfo
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- CN111078618A CN111078618A CN201911288986.6A CN201911288986A CN111078618A CN 111078618 A CN111078618 A CN 111078618A CN 201911288986 A CN201911288986 A CN 201911288986A CN 111078618 A CN111078618 A CN 111078618A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
Abstract
The invention discloses an electronic device, comprising a first processor; the first processor is connected with the second processor through a signal wire; the internal memory comprises an input/output port, and the first processor and the second processor are connected with the input/output port through a connection bus. The invention also discloses a communication method of the dual-processor. The invention realizes the communication between the double processors by simple line connection relation and adopting the single-port RAM with low price, and the processor is communicated with the channel between the processor and the internal memory to read the target data and write the associated data after receiving the interrupt signal of the other processor, thereby effectively avoiding the communication conflict caused by the two processors simultaneously accessing the internal memory and reducing the production cost of the electronic equipment.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to an electronic device and a communication method for dual processors.
Background
In the field of industrial control, if a single CPU is difficult to meet the high-speed real-time communication requirement of large-scale industrial equipment, the functions are usually decomposed on two CPUs, but because the two CPUs access a memory simultaneously, communication conflict exists, and equipment failure is caused.
The above is only for the purpose of assisting understanding of the technical aspects of the present invention, and does not represent an admission that the above is prior art.
Disclosure of Invention
The embodiment of the invention mainly aims to provide electronic equipment, and aims to solve the technical problem that in the prior art, two CPUs (central processing units) access a memory simultaneously, communication conflict exists, and equipment failure is caused.
To solve the above problem, an embodiment of the present invention provides an electronic device, including:
a first processor;
the first processor is connected with the second processor through a signal wire;
the internal memory comprises an input/output port, and the first processor and the second processor are connected with the input/output port through a connection bus.
Optionally, the signal line is a unidirectional signal line.
Optionally, the electronic device comprises 3 or more than 3 processors.
In addition, to solve the above problem, an embodiment of the present invention further provides a communication method for dual processors, including the following steps:
after receiving an interrupt signal sent by a second processor, a first processor reads target data in a data writing area corresponding to the second processor in an internal memory;
and writing the associated data of the target data into a data writing area corresponding to the first processor in the internal memory.
Optionally, after the step of writing the associated data of the target data into the data writing area corresponding to the first processor in the internal memory, the method further includes:
the first processor disconnects a path with an input/output port of the internal memory.
Optionally, the step of writing the associated data corresponding to the target data into a data writing area corresponding to a first processor in the internal memory includes:
the first processor processes the target data to obtain the associated data;
and the first processor writes the associated data into a data writing area corresponding to the first processor in the internal memory.
Optionally, after the step of reading the target data in the data writing area corresponding to the second processor in the internal memory, the method further includes:
and deleting the target data on the data writing area corresponding to the second processor in the internal memory.
The communication method of the dual processors provided by the embodiment of the invention is characterized in that after receiving an interrupt signal sent by the second processor, the first processor communicates a path between the first processor and the internal memory, reads target data in a data writing area corresponding to the second processor of the internal memory, writes related data of the target data into the internal memory, and sends the interrupt signal to the second processor so that the second processor can read the related data on the internal memory, thereby completing the communication between the dual processors at one time, the communication between the dual processors is realized by adopting a single-port RAM through a simple connection relation, the high-impedance state of the processors is kept through an input/output port, the path between the first processor and the internal memory is communicated under the condition of receiving the interrupt signal, and the communication conflict caused by the two processors accessing the internal memory at the same time can be effectively avoided, meanwhile, the beneficial effects of high-speed and real-time communication can be realized.
Drawings
Fig. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating a dual-processor communication method according to a first embodiment of the present invention;
FIG. 3 is a flowchart illustrating a dual-processor communication method according to a second embodiment of the present invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the detailed description and specific examples, while indicating the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention.
As shown in fig. 1, fig. 1 is a schematic terminal structure diagram of a hardware operating environment according to an embodiment of the present invention.
The execution main body of the embodiment of the invention is electronic equipment.
As shown in fig. 1, the electronic device may include: a first processor 1001, a second processor 1002, and an internal memory 1003. The first processor 1001 is a CPU, such as an ARM, an FPGA (Field-Programmable Gate Array), a DSP (Field-Programmable Gate Array), and the like; the second processor 1002 is a CPU such as an ARM, an FPGA, a DSP, and the like.
The first processor 1001 and the second processor 1002 are connected by a signal line 1005. Further, the signal line 1005 is unidirectional, and thus, the first processor 1001 transmits an interrupt signal to the second processor 1002 through the signal line 1005 to cause the second processor 1002 to read data written by the first processor 1001 on the internal memory 1003. Similarly, the second processor 1002 sends an interrupt signal to the first processor 1001 through another signal line 1005, so that the first processor 1001 reads data written by the second processor 1002 on the internal memory 1003. It is understood that, in practical applications, the first processor 1001 and the second processor 1002 may process the same task or may process different tasks. For example, in an electronic device, one processor is used to process communications and communications-related algorithms, and another processor is used to process applications on the electronic device. Further, the first processor 1001 and the second processor 1002 are not in a master-slave relationship, but are relatively independent, and can send an interrupt signal through the signal line 1005 to prompt the other side to perform a data reading operation.
The internal processor is provided with an input/output port and is respectively connected with the first processor 1001 and the second processor 1002 through the input/output port, wherein the internal processor is an SRAM and is a single-port random access memory; the Input/Output port may be a GPIO (General Purpose Input/Output) port. The internal memory 1003 is provided with two storage areas, which are a data writing area corresponding to the first processor 1001 and a data writing area corresponding to the second processor 1002. It should be noted that the data writing area corresponding to the first processor 1001 can be read by the second processor 1002; the data writing area corresponding to the second processor 1002 can be read by the first processor 1001.
The first processor 1001 and the second processor 1002 are substantially the same in configuration, and in the present embodiment, the first processor 1001 is taken as an example for further limitation. The first processor 1001 is also provided with an input/output port, and is connected with the internal memory 1003 through a connection bus 1005 connected with the input/output port, wherein the input/output port may be a GPIO port; connection bus 1005 includes control lines, bottom lines, and signal lines 1005. The first processor 1001 may be set to an input mode, such as GPIO-IN, via the input/output port and may also be set to an output mode, such as GPIO-OUT, and the first processor 1001 may be kept IN a high impedance state by setting the input/output port to the input mode. When the first processor 1001 is kept in the high impedance state, the second processor 1002 can access the internal memory 1003 at any time, and the problem that the dual processors simultaneously access the internal memory 1003, which causes communication conflict and causes failure of the electronic device, is avoided.
In an embodiment, the electronic device further includes three or more processors, and the multiple processors share the same internal memory 1003 to reduce the production cost and meet the requirement of the large industrial control that requires high performance operation capability.
Those skilled in the art will appreciate that the configuration of the terminal device shown in fig. 1 does not constitute a limitation of the terminal, and may include more or fewer components than those shown, or some components may be combined, or a different arrangement of components.
Based on the structure of the electronic device, a first embodiment of the present invention is proposed, and referring to fig. 2, fig. 2 is a schematic flow chart of a first embodiment of a dual-processor communication method according to the present invention, where the dual-processor communication method includes the following steps:
step S10, after receiving the interrupt signal sent by the second processor, the first processor reads the target data in the data writing area corresponding to the second processor in the internal memory;
in a large electronic control, the performance of a central processing unit is not enough to support the running requirements of multiple functions and multiple tasks, so that the problems of communication delay, low reaction speed and the like easily occur. One processor is used for processing communication and algorithms thereof, the other processor is used for processing application programs of the electronic equipment, and the electronic equipment achieves the best system performance and meets the requirements of real-time and high-speed communication through the mutual cooperation of the two processors.
In the embodiment, the operation principle is different from Serial communication, such as SPI (Serial Peripheral Interface), UART (Universal Asynchronous Receiver/Transmitter), and also different from the operation principle of the dual-port RAM. The dual-port RAM comprises two mailbox used for triggering interrupt between two processors, wherein one mailbox is used for triggering interrupt from the processor 1 to the processor 2, and the other mailbox is used for triggering interrupt from the processor 2 to the processor 1, namely the two processors are independent and have no connection relation, and the interrupt needs to be performed through the dual-port RAM when an interrupt signal needs to be sent. The internal memory in this embodiment is a single-port RAM, and at the same time, the first processor and the second processor trigger another processor to interrupt through the signal line. Compared with the prior art, the embodiment provides the communication method of the dual processors, which has the advantages of simple connection relation, no complex logic gate structure and low cost.
The first processor receives an interrupt signal sent by the second processor through a signal line, wherein the interrupt signal can be transmitted in a high-level, low-level or edge-triggered mode. Because the processor executes instructions in a fixed bus cycle, including fetching, decoding, and executing. The first processor checks for an external interrupt signal, i.e., an interrupt signal sent by the second processor, at the end of the last clock cycle of executing an instruction. The first processor is responsive to an interrupt signal if the interrupt is enabled.
After receiving the interrupt signal sent by the second processor, the first processor further includes:
and after the first processor receives the interrupt signal sent by the second processor, the first processor is communicated with a path between the first processor and an input/output port of the internal memory.
The first processor is provided with an input/output port, and when the input/output port on the first processor is set to an input mode, the first processor is in a high impedance state. When the first processor is in the high impedance state, no connection relation with the internal memory is established, that is, the first processor is in the state of "0". The high impedance state means that the processor does not issue signaling to the outside, or the first processor does not affect the internal memory.
After receiving the interrupt signal sent by the second processor, the first processor communicates with the path between the input/output port of the internal processor through the connection bus, that is, the first processor changes from the state of "0" to the state of "1", and converts the input mode to the output mode. It should be noted that, in general, no effective connection is established between the first processor and the internal memory, and the high impedance state of the first processor results. Similarly, the second processor is in a high impedance state when the second processor is not reading or writing data on the internal storage area. Because the processor does not access the internal memory under the normal condition, the dual-processor can be effectively ensured not to access the internal memory simultaneously to generate communication conflict.
And after the first processor establishes an effective connection relation with the internal memory, the first processor reads the target data of the data writing area corresponding to the second processor in the internal processor according to the interrupt signal. The interrupt signal may be a trigger signal to cause the first processor to read data from the internal memory after execution of an execution instruction is completed.
It can be understood that the internal processor is provided with two storage areas, which are a data writing area corresponding to the first processor and a data writing area corresponding to the second processor, respectively, wherein the first processor writes data into the data writing area corresponding to the first processor; and the second processor writes the data into the data writing area corresponding to the second processor. It should be noted that the first processor may read data on the data writing area corresponding to the second processor; the second processor can read the data on the data writing area corresponding to the first processor.
Further, after the first processor reads the target data on the internal memory, the method further includes:
and deleting the target data on the data writing area corresponding to the second processor in the internal memory.
Once processed, the target data loses value, and if the target data is stored in the internal memory, the internal memory is occupied, so that the running speed of the whole electronic equipment is reduced. And after the first processor reads the target data, deleting the target data on the data writing area corresponding to the second processor in the internal memory to release the resource occupation space on the internal memory, thereby improving the running speed of the whole electronic equipment. Meanwhile, after the first processor receives the interrupt signal sent by the second processor again, the situation that the first processor reads the data which is read again or introduces a flag bit to increase the flow and influence the communication speed between the two processors can be avoided.
Step S20, writing the relevant data of the target data into the data writing area corresponding to the first processor in the internal memory.
After the first processor reads the target data in the internal memory, the first processor may process the target data to obtain the associated data. The related data may be data obtained by processing the data read last time by the processor, and thus may be transmitted synchronously. For example, the target data may be a request of a user, and the associated data may be reply information made according to the request of the user. Further, there may be a logical relationship between the target data and the associated data.
The second processor may deliver the acquired data or information to the first processor for processing, and obtain a result fed back by the first processor after the processing by the first processor.
After the step of writing the associated data into the data writing area corresponding to the first processor in the internal memory by the first processor, the method further includes:
the first processor disconnects a path with an input/output port of the internal memory.
After the first processor writes the associated data in the internal memory, the first processor opens a path to an input/output port of the internal memory, that is, converts the state of "1" to the state of "0", and converts the output mode to the input mode.
The first processor and the second processor are not in a master-slave mode but in a cooperative relationship with each other. Furthermore, after the first processor disconnects the path with the internal memory, the first processor sends an interrupt signal to the second processor, so that the second processor communicates the path with the internal memory after receiving the interrupt signal, and reads the associated data on the data writing area corresponding to the first processor of the internal memory, thereby completing one-time communication between the first processor and the second processor.
It should be noted that the first processor reads the target data on the internal memory in a very short time (ns level), writes the associated data in a very short time, and sends an interrupt signal to the second processor. And after receiving the interrupt signal sent by the first processor, the second processor reads the associated data on the internal memory in a very short time to complete one-time communication. Therefore, the communication between the first processor and the second processor is high-speed and timely.
In this embodiment, after receiving an interrupt signal sent by the second processor, the first processor communicates with the path between the first processor and the internal memory, reads the target data in the data writing area corresponding to the second processor of the internal memory, writes the associated data of the target data into the internal memory, and sends the interrupt signal to the second processor, so that the second processor can read the associated data on the internal memory, thereby completing the communication between the dual processors, the communication between the dual processors is realized by a simple connection relationship and using a single-port RAM, the high-impedance state of the processors is maintained by the input/output ports, the path between the first processor and the internal memory is communicated only when receiving the interrupt signal, the communication conflict caused by the two processors accessing the internal memory at the same time can be effectively avoided, and meanwhile, the processors read the target data on the internal memory in a very short time, meanwhile, the associated data is written in a very short time, so that the beneficial effect of high-speed and real-time communication can be realized.
Referring to fig. 3, fig. 3 is a flowchart illustrating a second embodiment of the dual-processor communication method according to the present invention, and based on the first embodiment, step S20 includes:
step S21, the first processor processes the target data to obtain the associated data;
after reading the target data, the first processor processes the target data, wherein how to process the target data specifically may be a reply to the request, an analysis and summarization of scattered data, or an analysis and summarization of the data, and is not limited herein. The first processor processes the target data to obtain associated data, wherein the associated data may be result data obtained by processing the target data or data obtained by analyzing the target data.
The target data and the associated data have a certain logical relationship, and similarly, the target data is equivalent to flour pulled by the second processor, and the associated data such as bread is obtained after being processed by the first processor. It is also understood that the second processor writes "123" on the internal memory, writes "456" after the first processor reads, and writes "789" after the second processor processes.
The first processor processes the target data to obtain associated data so as to quickly respond to an instruction to be executed by the second processor, so that the electronic equipment can quickly respond after receiving the instruction of a user, delay is reduced, and the overall running speed of the electronic equipment is improved.
Step S22, the first processor writes the associated data into a data writing area corresponding to the first processor in the internal memory.
The first processor writes the associated data into a data writing area corresponding to the first processor of the internal memory and sends an interrupt signal to the second processor to prompt the second processor to read the data written in the internal memory so as to complete one communication cycle between the first processor and the second processor.
In this embodiment, after the first processor processes the read target data, the associated data is obtained, so as to quickly respond to the instruction to be executed by the second processor, improve the communication rate between the dual processors, and further improve the working efficiency of the whole electronic device.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a computer-readable storage medium (such as ROM/RAM, magnetic disk, optical disk) as described above, and includes several instructions for enabling a terminal device (such as a mobile phone, a computer, a server, an air conditioner, or a network device) to execute the method according to the embodiments of the present invention.
The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (8)
1. An electronic device, characterized in that the electronic device comprises:
a first processor;
the first processor is connected with the second processor through a signal wire;
the internal memory comprises an input/output port, and the first processor and the second processor are connected with the input/output port through a connection bus.
2. The electronic device of claim 1, wherein the signal line connected between the first processor and the second processor is a unidirectional signal line.
3. The electronic device of claim 1, wherein the electronic device comprises 3 or more than 3 processors.
4. A communication method of a dual processor, which is applied to the electronic device according to claims 1 to 3, characterized in that the communication method of the dual processor comprises the steps of:
after receiving an interrupt signal sent by a second processor, a first processor reads target data in a data writing area corresponding to the second processor in an internal memory;
and writing the associated data of the target data into a data writing area corresponding to the first processor in the internal memory.
5. The dual-processor communication method of claim 4, wherein the dual-processor communication method further comprises:
and after the first processor receives the interrupt signal sent by the second processor, the first processor is communicated with a path between the first processor and an input/output port of the internal memory.
6. The dual-processor communication method according to claim 4, wherein after the step of writing the data associated with the target data into the data writing area corresponding to the first processor in the internal memory, the method further comprises:
the first processor disconnects a path with an input/output port of the internal memory.
7. The dual-processor communication method according to claim 4, wherein the step of writing the associated data corresponding to the target data into the data writing area corresponding to the first processor in the internal memory comprises:
the first processor processes the target data to obtain the associated data;
and the first processor writes the associated data into a data writing area corresponding to the first processor in the internal memory.
8. The dual-processor communication method according to claim 4, wherein after the step of reading the target data in the data writing area corresponding to the second processor in the internal memory, the method further comprises:
and deleting the target data on the data writing area corresponding to the second processor in the internal memory.
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