CN111047005A

CN111047005A - Operation method, operation device, computer equipment and storage medium

Info

Publication number: CN111047005A
Application number: CN201910623290.8A
Authority: CN
Inventors: 不公告发明人
Original assignee: Shanghai Cambricon Information Technology Co Ltd
Current assignee: Shanghai Cambricon Information Technology Co Ltd
Priority date: 2018-10-11
Filing date: 2019-07-11
Publication date: 2020-04-21

Abstract

The present disclosure relates to an arithmetic method, an apparatus, a computer device, and a storage medium. Wherein the combined processing device comprises: a machine learning arithmetic device, a universal interconnection interface and other processing devices; the machine learning arithmetic device interacts with other processing devices to jointly complete the calculation operation designated by the user, wherein the combined processing device further comprises: and the storage device is respectively connected with the machine learning arithmetic device and the other processing devices and is used for storing the data of the machine learning arithmetic device and the other processing devices. The volume operation method, the volume operation device, the computer equipment and the storage medium provided by the embodiment of the disclosure have wide application range, high operation processing efficiency and high processing speed.

Description

Operation method, operation device, computer equipment and storage medium

Technical Field

The present disclosure relates to the field of computer technologies, and in particular, to an operation method, an operation device, a computer device, and a storage medium.

Background

With the continuous development of science and technology, machine learning, especially neural network algorithms, are more and more widely used. The method is well applied to the fields of image recognition, voice recognition, natural language processing and the like. However, as the complexity of neural network algorithms is higher and higher, the types and the number of involved data operations are increasing. In the related art, the convolution operation of data is inefficient and slow.

Disclosure of Invention

In view of the above, the present disclosure provides an operation method, an operation device, a computer device, and a storage medium to improve efficiency and speed of performing convolution operation on data.

According to a first aspect of the present disclosure, there is provided a convolution instruction processing apparatus, the apparatus comprising:

the control module is used for analyzing the obtained convolution instruction to obtain an operation code and an operation domain of the convolution instruction, and obtaining data to be operated, a convolution kernel and a target address which are required by the execution of the convolution instruction according to the operation code and the operation domain;

the operation module is used for carrying out convolution operation on the data to be operated according to the convolution core to obtain an operation result and storing the operation result into the target address,

the operation code is used for indicating that the operation performed on the data by the convolution instruction is convolution operation, and the operation domain comprises a data address to be operated, a convolution kernel address and the target address.

According to a second aspect of the present disclosure, there is provided a machine learning arithmetic device, the device including:

one or more convolution instruction processing devices according to the first aspect described above, configured to acquire data to be operated and control information from another processing device, execute a specified machine learning operation, and transmit an execution result to the other processing device through an I/O interface;

when the machine learning arithmetic device comprises a plurality of convolution instruction processing devices, the plurality of convolution instruction processing devices can be connected through a specific structure and transmit data;

the convolution instruction processing devices are interconnected through a PCIE bus of a fast peripheral equipment interconnection bus and transmit data so as to support operation of larger-scale machine learning; a plurality of convolution instruction processing devices share the same control system or own respective control systems; the convolution instruction processing devices share a memory or own memories; the interconnection mode of the convolution instruction processing devices is any interconnection topology.

According to a third aspect of the present disclosure, there is provided a combined processing apparatus, the apparatus comprising:

the machine learning arithmetic device, the universal interconnect interface, and the other processing device according to the second aspect;

and the machine learning arithmetic device interacts with the other processing devices to jointly complete the calculation operation designated by the user.

According to a fourth aspect of the present disclosure, there is provided a machine learning chip including the machine learning network operation device of the second aspect or the combination processing device of the third aspect.

According to a fifth aspect of the present disclosure, there is provided a machine learning chip package structure, which includes the machine learning chip of the fourth aspect.

According to a sixth aspect of the present disclosure, a board card is provided, which includes the machine learning chip packaging structure of the fifth aspect.

According to a seventh aspect of the present disclosure, there is provided an electronic device, which includes the machine learning chip of the fourth aspect or the board of the sixth aspect.

According to an eighth aspect of the present disclosure, there is provided a convolution instruction processing method, which is applied to a convolution instruction processing apparatus, the method including:

analyzing the obtained convolution instruction to obtain an operation code and an operation domain of the convolution instruction, and obtaining data to be operated, a convolution kernel and a target address which are required by the execution of the convolution instruction according to the operation code and the operation domain;

carrying out convolution operation on the data to be operated according to the convolution core to obtain an operation result, storing the operation result into the target address,

According to a ninth aspect of the present disclosure, there is provided a non-transitory computer readable storage medium having stored thereon computer program instructions which, when executed by a processor, implement the above convolution instruction processing method.

In some embodiments, the electronic device comprises a data processing apparatus, a robot, a computer, a printer, a scanner, a tablet, a smart terminal, a cell phone, a tachograph, a navigator, a sensor, a camera, a server, a cloud server, a camera, a camcorder, a projector, a watch, a headset, a mobile storage, a wearable device, a vehicle, a household appliance, and/or a medical device.

In some embodiments, the vehicle comprises an aircraft, a ship, and/or a vehicle; the household appliances comprise a television, an air conditioner, a microwave oven, a refrigerator, an electric cooker, a humidifier, a washing machine, an electric lamp, a gas stove and a range hood; the medical equipment comprises a nuclear magnetic resonance apparatus, a B-ultrasonic apparatus and/or an electrocardiograph.

The device comprises a control module and an operation module, wherein the control module is used for analyzing the obtained convolution instruction to obtain an operation code and an operation domain of the convolution instruction, and obtaining data to be operated, a convolution kernel and a target address which are required by executing the convolution instruction according to the operation code and the operation domain; the operation module is used for carrying out convolution operation on the data to be operated according to the convolution core to obtain an operation result and storing the operation result into the target address. The convolution instruction processing method, the convolution instruction processing device, the computer equipment and the storage medium provided by the embodiment of the disclosure have wide application range, high convolution instruction processing efficiency and high convolution operation processing speed.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

Fig. 1 shows a block diagram of a convolution instruction processing apparatus according to an embodiment of the present disclosure.

Fig. 2 a-2 f show block diagrams of a convolution instruction processing apparatus according to an embodiment of the present disclosure.

Fig. 3 is a schematic diagram illustrating an application scenario of a convolution instruction processing apparatus according to an embodiment of the present disclosure.

Fig. 4a, 4b show block diagrams of a combined processing device according to an embodiment of the present disclosure.

Fig. 5 shows a schematic structural diagram of a board card according to an embodiment of the present disclosure.

FIG. 6 shows a flow diagram of a convolution instruction processing method according to an embodiment of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present disclosure will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are some, not all embodiments of the present disclosure. All other embodiments, which can be derived by one skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the scope of protection of the present disclosure.

It should be understood that the terms "zero," "first," "second," and the like in the claims, the description, and the drawings of the present disclosure are used for distinguishing between different objects and not for describing a particular order. The terms "comprises" and "comprising," when used in the specification and claims of this disclosure, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only, and is not intended to be limiting of the disclosure. As used in the specification and claims of this disclosure, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the term "and/or" as used in the specification and claims of this disclosure refers to any and all possible combinations of one or more of the associated listed items and includes such combinations.

As used in this specification and claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to a determination" or "in response to a detection". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".

Due to the wide use of neural network algorithms, the computing man power of computer hardware is continuously improved, and the types and the number of data operations involved in practical application are continuously improved. The convolution operation is a mathematical operator that generates a third function by two functions f and g, characterizing the area of the overlapping part of the functions f and g through flipping and translation. Because the variety of programming languages is various, in order to realize the operation process of the convolution operation under different language environments, in the related art, as the convolution instruction which can be widely applied to various programming languages is not available at the present stage, technicians need to self-define a plurality of instructions corresponding to the programming language environments to realize the convolution operation, and the efficiency of the convolution operation is low and the speed is low. The present disclosure provides a convolution instruction processing method, apparatus, computer device, and storage medium, which can realize convolution operation with only one instruction, and can significantly improve the efficiency and speed of performing convolution operation.

Fig. 1 shows a block diagram of a convolution instruction processing apparatus according to an embodiment of the present disclosure. As shown in fig. 1, the apparatus includes a control module 11 and an operation module 12.

And the control module 11 is configured to analyze the obtained convolution instruction to obtain an operation code and an operation domain of the convolution instruction, and obtain data to be operated, a convolution kernel, and a target address required for executing the convolution instruction according to the operation code and the operation domain. The operation code is used for indicating that the operation of the convolution instruction on the data is convolution operation, and the operation domain comprises a data address to be operated, a convolution kernel address and a target address.

The operation module 12 is configured to perform convolution operation (convolution operation) on data to be operated according to a convolution kernel to obtain an operation result, and store the operation result in a target address.

In this embodiment, the control module may obtain the data to be operated and the convolution kernel from the data address to be operated and the convolution kernel address, respectively.

In this embodiment, the operation code may be a part of an instruction or a field (usually indicated by a code) specified in the computer program to perform an operation, and is an instruction sequence number used to inform a device executing the instruction which instruction needs to be executed specifically. The operation domain may be a source of all data required for executing the corresponding instruction, and all data required for executing the corresponding instruction includes parameters such as data to be operated on, a convolution kernel, and a corresponding operation method. For a convolution instruction, it must include operation code and operation field, in which the operation field at least includes data address to be calculated, convolution kernel address and target address

It should be understood that the instruction format of the convolution instruction and the contained opcode and operation field may be set as desired by those skilled in the art, and are not limited by the present disclosure.

In this embodiment, the apparatus may include one or more control modules and one or more operation modules, and the number of the control modules and the number of the operation modules may be set according to actual needs, which is not limited in this disclosure. When the device comprises a control module, the control module can receive convolution instructions and control one or more operation modules to carry out convolution operation. When the device comprises a plurality of control modules, the control modules can respectively receive convolution instructions and control one or more corresponding operation modules to carry out convolution operation.

The convolution instruction processing device provided by the embodiment of the disclosure comprises a control module and an operation module, wherein the control module is used for analyzing the obtained convolution instruction to obtain an operation code and an operation domain of the convolution instruction, and obtaining data to be operated, a convolution kernel and a target address which are required by executing the convolution instruction according to the operation code and the operation domain; and the operation module is used for carrying out convolution operation on the data to be operated according to the convolution core to obtain an operation result and storing the operation result into the target address. The convolution instruction processing device provided by the embodiment of the disclosure has a wide application range, and is high in processing efficiency and processing speed of convolution instructions, and high in processing efficiency and speed of convolution operation.

Fig. 2a shows a block diagram of a convolution instruction processing apparatus according to an embodiment of the present disclosure. In one possible implementation, as shown in fig. 2a, the operation module 12 may include a plurality of multipliers 120 and a plurality of adders 120'. A plurality of multipliers 120 for performing multiplication operations in the convolution operations. And a plurality of adders 120' for performing addition operations among the convolution operations.

In this implementation, the operation module may further include an adder and a multiplier, or include an adder and multiple multipliers, or further include multiple adders and a multiplier. The number of multipliers and adders may be set according to the data amount of the convolution operation required to be performed, the processing speed of the convolution operation, the processing efficiency, and other requirements, which is not limited by the present disclosure.

Fig. 2b shows a block diagram of a convolution instruction processing apparatus according to an embodiment of the present disclosure. In one possible implementation, as shown in fig. 2b, the operation module 12 may include a master operation sub-module 121 and a plurality of slave operation sub-modules 122, and the slave operation sub-modules 122 include a plurality of multipliers 120 and a plurality of adders 120' (not shown in the figure).

The control module 11 is further configured to analyze the convolution instruction to obtain a plurality of operation instructions, and send the data to be operated, the convolution kernel, and the plurality of operation instructions to the main operation submodule 121.

The primary operation sub-module 121 is configured to perform preamble processing on data to be operated and a convolution kernel, and transmit data and operation instructions with the plurality of secondary operation sub-modules 122.

And the slave operation sub-module 122 is configured to perform an intermediate operation in parallel according to the data and the operation instruction transmitted from the master operation sub-module 121 to obtain a plurality of intermediate results based on the plurality of multipliers 120 and the plurality of adders 120', and transmit the plurality of intermediate results to the master operation sub-module 122.

The main operation sub-module 121 is further configured to perform subsequent processing on the plurality of intermediate results to obtain an operation result, and store the operation result in the target address.

In a possible implementation manner, the control module 11 is further configured to analyze the obtained calculation instruction to obtain an operation domain and an operation code of the calculation instruction, and obtain data to be operated, which is required for executing the calculation instruction, according to the operation domain and the operation code. The operation module 12 is further configured to perform an operation on the data to be operated according to the calculation instruction to obtain a calculation result of the calculation instruction. The operation module may include a plurality of operators for performing operations corresponding to operation types of the calculation instructions.

In this implementation, the calculation instruction may be other instructions for performing arithmetic operations, logical operations, and the like on data such as scalars, vectors, matrices, tensors, and the like, and those skilled in the art may set the calculation instruction according to actual needs, which is not limited by the present disclosure.

In this implementation, the arithmetic unit may include an adder, a divider, a multiplier, a comparator, and the like, which are capable of performing arithmetic operations, logical operations, and the like on data. The type and number of the arithmetic units may be set according to the requirements of the size of the data amount of the arithmetic operation to be performed, the type of the arithmetic operation, the processing speed and efficiency of the arithmetic operation on the data, and the like, which is not limited by the present disclosure.

In a possible implementation manner, the control module 11 is further configured to analyze the calculation instruction to obtain a plurality of operation instructions, and send the data to be operated and the plurality of operation instructions to the main operation sub-module 121.

The master operation sub-module 121 is configured to perform preamble processing on data to be operated, and transmit data and operation instructions with the plurality of slave operation sub-modules 122.

The slave operation submodule 122 is configured to execute an intermediate operation in parallel according to the data and the operation instruction transmitted from the master operation submodule 121 to obtain a plurality of intermediate results, and transmit the plurality of intermediate results to the master operation submodule 122.

The main operation sub-module 121 is further configured to perform subsequent processing on the plurality of intermediate results to obtain a calculation result of the calculation instruction, and store the calculation result in the corresponding address.

In this implementation, when the computation instruction is an operation performed on scalar or vector data, the apparatus may control the main operation sub-module to perform an operation corresponding to the computation instruction by using an operator therein. When the calculation instruction is to perform an operation on data having a dimension greater than or equal to 2, such as a matrix, a tensor, or the like, the device may control the slave operation submodule to perform an operation corresponding to the calculation instruction by using an operator therein.

It should be noted that, a person skilled in the art may set the connection manner between the master operation submodule and the plurality of slave operation submodules according to actual needs to implement the configuration setting of the operation module, for example, the configuration of the operation module may be an "H" configuration, an array configuration, a tree configuration, and the like, which is not limited in the present disclosure.

Fig. 2c shows a block diagram of a convolution instruction processing apparatus according to an embodiment of the present disclosure. In one possible implementation, as shown in fig. 2c, the operation module 12 may further include one or more branch operation sub-modules 123, and the branch operation sub-module 123 is configured to forward data and/or operation instructions between the master operation sub-module 121 and the slave operation sub-module 122. The main operation sub-module 121 is connected to one or more branch operation sub-modules 123. Therefore, the main operation sub-module, the branch operation sub-module and the slave operation sub-module in the operation module are connected by adopting an H-shaped structure, and data and/or operation instructions are forwarded by the branch operation sub-module, so that the resource occupation of the main operation sub-module is saved, and the instruction processing speed is further improved.

Fig. 2d shows a block diagram of a convolution instruction processing apparatus according to an embodiment of the present disclosure. In one possible implementation, as shown in FIG. 2d, a plurality of slave operation sub-modules 122 are distributed in an array.

Each slave operation submodule 122 is connected to another adjacent slave operation submodule 122, the master operation submodule 121 is connected to k slave operation submodules 122 of the plurality of slave operation submodules 122, and the k slave operation submodules 122 are: n slave operator sub-modules 122 of row 1, n slave operator sub-modules 122 of row m, and m slave operator sub-modules 122 of column 1.

As shown in fig. 2d, the k slave operator modules include only the n slave operator modules in the 1 st row, the n slave operator modules in the m th row, and the m slave operator modules in the 1 st column, that is, the k slave operator modules are slave operator modules directly connected to the master operator module among the plurality of slave operator modules. The k slave operation submodules are used for forwarding data and instructions between the master operation submodules and the plurality of slave operation submodules. Therefore, the plurality of slave operation sub-modules are distributed in an array, the speed of sending data and/or operation instructions to the slave operation sub-modules by the master operation sub-module can be increased, and the instruction processing speed is further increased.

Fig. 2e shows a block diagram of a convolution instruction processing apparatus according to an embodiment of the present disclosure. In one possible implementation, as shown in fig. 2e, the operation module may further include a tree sub-module 124. The tree submodule 124 includes a root port 401 and a plurality of branch ports 402. The root port 401 is connected to the master operation submodule 121, and the plurality of branch ports 402 are connected to the plurality of slave operation submodules 122, respectively. The tree sub-module 124 has a transceiving function, and is configured to forward data and/or operation instructions between the master operation sub-module 121 and the slave operation sub-module 122. Therefore, the operation modules are connected in a tree-shaped structure under the action of the tree-shaped sub-modules, and the speed of sending data and/or operation instructions from the main operation sub-module to the auxiliary operation sub-module can be increased by utilizing the forwarding function of the tree-shaped sub-modules, so that the instruction processing speed is increased.

In one possible implementation, the tree submodule 124 may be an optional result of the apparatus, which may include at least one level of nodes. The nodes are line structures with forwarding functions, and the nodes do not have operation functions. The lowest level node is connected to the slave operation sub-module to forward data and/or operation instructions between the master operation sub-module 121 and the slave operation sub-module 122. In particular, if the tree submodule has zero level nodes, the apparatus does not require the tree submodule.

In one possible implementation, the tree submodule 124 may include a plurality of nodes of an n-ary tree structure, and the plurality of nodes of the n-ary tree structure may have a plurality of layers.

For example, fig. 2f shows a block diagram of a convolution instruction processing device according to an embodiment of the present disclosure. As shown in FIG. 2f, the n-ary tree structure may be a binary tree structure with tree-type sub-modules including 2 levels of nodes 01. The lowest level node 01 is connected with the slave operation sub-module 122 to forward data and/or operation instructions between the master operation sub-module 121 and the slave operation sub-module 122.

In this implementation, the n-ary tree structure may also be a ternary tree structure or the like, where n is a positive integer greater than or equal to 2. The number of n in the n-ary tree structure and the number of layers of nodes in the n-ary tree structure may be set by those skilled in the art as needed, and the disclosure is not limited thereto.

In one possible implementation, the operation field may further include an input height and an input width.

The control module is further used for acquiring the data to be operated corresponding to the input width and the input height from the data address to be operated.

In this implementation, the input height and the input width may define the data amount and size of the obtained data to be operated on. The input height and the input width included in the operation field may be specific numerical values, or may be storage addresses storing the input height and the input width. When a specific numerical value of the input height and the input width is directly included in the operation field, the specific numerical value is determined as the corresponding input height and input width. When the storage addresses of the input height and the input width are included in the operation field, the input height and the input width may be obtained from the storage addresses of the input height and the input width, respectively.

In one possible implementation manner, when the input height and/or the input width are not included in the operation domain, the data to be operated may be acquired according to a preset default input height and default input width.

By the mode, the data size and the size of the data to be operated can be limited, the accuracy of an operation result is ensured, and the device can execute the convolution instruction.

In one possible implementation, the operation domain may further include a convolution kernel height and a convolution kernel width. The control module 11 is further configured to obtain a convolution kernel from the convolution kernel address according to the height of the convolution kernel and the width of the convolution kernel.

In one possible implementation, the operation domain may further include a first stride. The operation module 12 is further configured to move the convolution kernel in the X direction of the data to be operated according to the first step.

In one possible implementation, the operation domain may further include a second stride. The operation module 12 is further configured to move the convolution kernel in the Y direction of the data to be operated according to the second step size.

In one possible implementation, when one or more of the height of the convolution kernel, the width of the convolution kernel, and the first step and the second step of the convolution kernel are not included in the operation domain, a preset default height of the convolution kernel, a default width of the convolution kernel, a default first step and a default second step of the convolution kernel may be obtained, so that the control module and the operation module may execute the convolution instruction.

In one possible implementation, the operation domain may also include the number of convolution kernels. The operation module 12 is further configured to perform convolution operation on the data to be operated through a plurality of convolution kernels, the number of which is the number of convolution kernels.

In this implementation, the number of convolution kernels corresponds to the data to be computed. For example, when the number of convolution kernels is 5, it may be determined that the data to be operated may be divided into five parts, and 5 convolution kernels are required to perform convolution operations on the five parts of the data to be operated, respectively.

In this implementation manner, when the operation domain does not include the number of convolution kernels, it may be determined that only one convolution kernel is needed for the data to be operated to implement the convolution operation.

In one possible implementation, the operation domain may further include a channel number. The operation module 12 is further configured to perform convolution operation on the data to be operated through the corresponding channel according to the number of the channels, so as to obtain an operation result.

For example, when the number of channels is 3, convolution operation may be performed on the data to be operated on the three channels to obtain an operation result.

In one possible implementation, as shown in fig. 2 a-2 f, the apparatus may further include a storage module 13. The storage module 13 is used for storing data to be operated and convolution kernels.

In this implementation, the storage module may include one or more of a cache and a register, and the cache may include a temporary cache and may further include at least one NRAM (Neuron Random Access Memory). The cache is used for storing data to be operated and the convolution kernel, and the register is used for storing scalar data in the data to be operated.

In one possible implementation, the cache may include a neuron cache. The neuron buffer is used for storing neuron data in data to be operated, and the neuron data comprises neuron vector data.

In one possible implementation, as shown in fig. 2 a-2 f, the control module 11 may include an instruction storage sub-module 111, an instruction processing sub-module 112, and a queue storage sub-module 113.

The instruction storage submodule 111 is used to store convolution instructions.

The instruction processing sub-module 112 is configured to parse the convolution instruction to obtain an operation code and an operation domain of the convolution instruction.

The queue storage submodule 113 is configured to store an instruction queue, where the instruction queue includes a plurality of instructions to be executed that are sequentially arranged according to an execution order, and the plurality of instructions to be executed may include a convolution instruction.

In this implementation manner, the execution order of the multiple instructions to be executed may be arranged according to the receiving time, the priority level, and the like of the instructions to be executed to obtain an instruction queue, so that the multiple instructions to be executed are sequentially executed according to the instruction queue.

In one possible implementation, as shown in fig. 2 a-2 f, the control module 11 may further include a dependency processing sub-module 114.

The dependency relationship processing submodule 114 is configured to, when it is determined that a first to-be-executed instruction in the multiple to-be-executed instructions is associated with a zeroth to-be-executed instruction before the first to-be-executed instruction, cache the first to-be-executed instruction in the instruction storage submodule 111, and after the zeroth to-be-executed instruction is executed, extract the first to-be-executed instruction from the instruction storage submodule 111 and send the first to-be-executed instruction to the operation module 12.

The method for determining the zero-th instruction to be executed before the first instruction to be executed has an incidence relation with the first instruction to be executed comprises the following steps: the first storage address interval for storing the data required by the first to-be-executed instruction and the zeroth storage address interval for storing the data required by the zeroth to-be-executed instruction have an overlapped area. On the contrary, there is no association relationship between the first to-be-executed instruction and the zeroth to-be-executed instruction before the first to-be-executed instruction, which may be that there is no overlapping area between the first storage address interval and the zeroth storage address interval.

By the method, according to the dependency relationship between the first to-be-executed instruction and the zeroth to-be-executed instruction before the first to-be-executed instruction, the subsequent first to-be-executed instruction is executed after the execution of the previous zeroth to-be-executed instruction is finished, and the accuracy of the operation result is ensured.

In one possible implementation, the instruction format of the convolution instruction may be:

conv dst src0kernel srcChannel srcHeigh srcWidth kernelHeightkernelWidth strideX strideY dstChannel

wherein conv is the operation code of the convolution instruction, dst, src0, kernel, src channel, src height, src width, kernel height, kernel width, strideX, strideY, dstChannel are the operation domain of the convolution instruction. Wherein dst is a target address, src0 is a data address to be operated, kernel is a convolution kernel or a convolution kernel address, src channel is the number of convolution kernels, src height is an input height of data to be operated, src width is an input width of data to be operated, kernelHeight is a convolution kernel height, kernelWidth is a convolution kernel width, strideX is a first step, strideY is a second step, and dstChannel is a channel number.

It should be understood that the position of the operation code of the convolution instruction, the operation code and the operation field in the instruction format can be set by those skilled in the art according to the needs, and the disclosure does not limit this.

In one possible implementation manner, the apparatus may be disposed in one or more of a Graphics Processing Unit (GPU), a Central Processing Unit (CPU), and an embedded Neural Network Processor (NPU).

It should be noted that, although the convolution instruction processing apparatus has been described above by taking the above-described embodiment as an example, those skilled in the art will understand that the present disclosure should not be limited thereto. In fact, the user can flexibly set each module according to personal preference and/or actual application scene, as long as the technical scheme of the disclosure is met.

Application example

An application example according to the embodiment of the present disclosure is given below in conjunction with "performing convolution operation with a convolution instruction processing apparatus" as one exemplary application scenario to facilitate understanding of the flow of the convolution instruction processing apparatus. It is understood by those skilled in the art that the following application examples are merely for the purpose of facilitating understanding of the embodiments of the present disclosure and should not be construed as limiting the embodiments of the present disclosure

Fig. 3 is a schematic diagram illustrating an application scenario of a convolution instruction processing apparatus according to an embodiment of the present disclosure. As shown in fig. 3, the convolution instruction processing apparatus processes the convolution instruction as follows:

the control module 11 analyzes the obtained convolution instruction 1 (for example, the convolution instruction 1 is conv 5001002005643221233), and obtains an operation code and an operation domain of the convolution instruction 1. The operation code of the convolution instruction 1 is conv, the target address is 500, the address of the data to be calculated is 100, the address of the convolution kernel is 200, the number of the convolution kernels is 5, the input height is 64, the input width is 32, the height of the convolution kernel is 2, the width of the convolution kernel is 1, the first step is 2, the second step is 3, and the number of channels is 3. The control module 11 obtains 64 × 32 data to be operated from the data address 100 to be operated, and obtains 2 × 1 convolution kernel from the convolution kernel address 200.

The operation module 12 performs convolution operation on the data to be operated according to the number of convolution kernels 5, the first step 2, the second step 3 and the number of channels 3 to obtain an operation result, and stores the operation result in the target address 500.

The working process of the above modules can refer to the above related description.

Thus, the convolution instruction processing device can efficiently and quickly process convolution instructions, and the convolution operation processing efficiency is high and the convolution operation speed is high.

The present disclosure provides a machine learning arithmetic device, which may include one or more of the above convolution instruction processing devices, and is configured to acquire data to be operated and control information from other processing devices and execute a specified machine learning operation. The machine learning arithmetic device can obtain a convolution instruction from other machine learning arithmetic devices or non-machine learning arithmetic devices, and transmit an execution result to peripheral equipment (also called other processing devices) through an I/O interface. Peripheral devices such as cameras, displays, mice, keyboards, network cards, wifi interfaces, servers. When more than one convolution command processing device is included, the convolution command processing devices can be linked and transmit data through a specific structure, for example, a PCIE bus is used for interconnection and data transmission, so as to support larger-scale operation of the neural network. At this time, the same control system may be shared, or there may be separate control systems; the memory may be shared or there may be separate memories for each accelerator. In addition, the interconnection mode can be any interconnection topology.

The machine learning arithmetic device has high compatibility and can be connected with various types of servers through PCIE interfaces.

Fig. 4a shows a block diagram of a combined processing device according to an embodiment of the present disclosure. As shown in fig. 4a, the combined processing device includes the machine learning arithmetic device, the universal interconnection interface, and other processing devices. The machine learning arithmetic device interacts with other processing devices to jointly complete the operation designated by the user.

Other processing devices include one or more of general purpose/special purpose processors such as Central Processing Units (CPUs), Graphics Processing Units (GPUs), neural network processors, and the like. The number of processors included in the other processing devices is not limited. The other processing devices are used as interfaces of the machine learning arithmetic device and external data and control, and comprise data transportation to finish basic control of starting, stopping and the like of the machine learning arithmetic device; other processing devices may cooperate with the machine learning computing device to perform computing tasks.

And the universal interconnection interface is used for transmitting data and control instructions between the machine learning arithmetic device and other processing devices. The machine learning arithmetic device acquires required input data from other processing devices and writes the input data into a storage device on the machine learning arithmetic device; control instructions can be obtained from other processing devices and written into a control cache on a machine learning arithmetic device chip; the data in the storage module of the machine learning arithmetic device can also be read and transmitted to other processing devices.

Fig. 4b shows a block diagram of a combined processing device according to an embodiment of the present disclosure. In a possible implementation manner, as shown in fig. 4b, the combined processing device may further include a storage device, and the storage device is connected to the machine learning operation device and the other processing device respectively. The storage device is used for storing data stored in the machine learning arithmetic device and the other processing device, and is particularly suitable for data which is required to be calculated and cannot be stored in the internal storage of the machine learning arithmetic device or the other processing device.

The combined processing device can be used as an SOC (system on chip) system of equipment such as a mobile phone, a robot, an unmanned aerial vehicle and video monitoring equipment, the core area of a control part is effectively reduced, the processing speed is increased, and the overall power consumption is reduced. In this case, the generic interconnect interface of the combined processing device is connected to some component of the apparatus. Some parts are such as camera, display, mouse, keyboard, network card, wifi interface.

The present disclosure provides a machine learning chip, which includes the above machine learning arithmetic device or combined processing device.

The present disclosure provides a machine learning chip package structure, which includes the above machine learning chip.

Fig. 5 shows a schematic structural diagram of a board card according to an embodiment of the present disclosure. As shown in fig. 5, the board includes the above-mentioned machine learning chip package structure or the above-mentioned machine learning chip. The board may include, in addition to the machine learning chip 389, other kits including, but not limited to: memory device 390, interface device 391 and control device 392.

The memory device 390 is coupled to a machine learning chip 389 (or a machine learning chip within a machine learning chip package structure) via a bus for storing data. Memory device 390 may include multiple sets of memory cells 393. Each group of memory cells 393 is coupled to a machine learning chip 389 via a bus. It is understood that each group 393 may be a DDR SDRAM (Double Data Rate SDRAM).

DDR can double the speed of SDRAM without increasing the clock frequency. DDR allows data to be read out on the rising and falling edges of the clock pulse. DDR is twice as fast as standard SDRAM.

In one embodiment, memory device 390 may include 4 groups of memory cells 393. Each group of memory cells 393 may include a plurality of DDR4 particles (chips). In one embodiment, the machine learning chip 389 may include 4 72-bit DDR4 controllers therein, where 64bit is used for data transmission and 8bit is used for ECC check in the 72-bit DDR4 controller. It is appreciated that when DDR4-3200 particles are used in each group of memory cells 393, the theoretical bandwidth of data transfer may reach 25600 MB/s.

In one embodiment, each group 393 of memory cells includes a plurality of double rate synchronous dynamic random access memories arranged in parallel. DDR can transfer data twice in one clock cycle. A controller for controlling DDR is provided in the machine learning chip 389 for controlling data transfer and data storage of each memory unit 393.

Interface device 391 is electrically coupled to machine learning chip 389 (or a machine learning chip within a machine learning chip package). The interface device 391 is used to implement data transmission between the machine learning chip 389 and an external device (e.g., a server or a computer). For example, in one embodiment, the interface device 391 may be a standard PCIE interface. For example, the data to be processed is transmitted to the machine learning chip 289 by the server through the standard PCIE interface, so as to implement data transfer. Preferably, when PCIE 3.0X 16 interface transmission is adopted, the theoretical bandwidth can reach 16000 MB/s. In another embodiment, the interface device 391 may also be another interface, and the disclosure does not limit the specific representation of the other interface, and the interface device can implement the switching function. In addition, the calculation result of the machine learning chip is still transmitted back to the external device (e.g., server) by the interface device.

The control device 392 is electrically connected to a machine learning chip 389. The control device 392 is used to monitor the state of the machine learning chip 389. Specifically, the machine learning chip 389 and the control device 392 may be electrically connected through an SPI interface. The control device 392 may include a single chip Microcomputer (MCU). For example, machine learning chip 389 may include multiple processing chips, multiple processing cores, or multiple processing circuits, which may carry multiple loads. Therefore, the machine learning chip 389 can be in different operation states such as a multi-load and a light load. The control device can regulate and control the working states of a plurality of processing chips, a plurality of processing circuits and/or a plurality of processing circuits in the machine learning chip.

The present disclosure provides an electronic device, which includes the above machine learning chip or board card.

The electronic device may include a data processing apparatus, a computer device, a robot, a computer, a printer, a scanner, a tablet, a smart terminal, a cell phone, a tachograph, a navigator, a sensor, a camera, a server, a cloud server, a camera, a camcorder, a projector, a watch, an earphone, a mobile storage, a wearable device, a vehicle, a household appliance, and/or a medical device.

The vehicle may include an aircraft, a ship, and/or a vehicle. The household appliances may include televisions, air conditioners, microwave ovens, refrigerators, electric rice cookers, humidifiers, washing machines, electric lamps, gas cookers, and range hoods. The medical device may include a nuclear magnetic resonance apparatus, a B-mode ultrasound apparatus and/or an electrocardiograph.

FIG. 6 shows a flow diagram of a convolution instruction processing method according to an embodiment of the present disclosure. The method can be applied to computer equipment and the like comprising a memory and a processor, wherein the memory is used for storing data used in the process of executing the method; the processor is used for executing relevant processing and operation steps, such as the steps S51 and S52. As shown in fig. 6, the method is applied to the convolution instruction processing apparatus described above, and includes step S51 and step S52.

In step S51, the control module is used to analyze the obtained convolution instruction to obtain an operation code and an operation domain of the convolution instruction, and obtain data to be operated, a convolution kernel, and a target address required for executing the convolution instruction according to the operation code and the operation domain. The operation code is used for indicating that the operation of the convolution instruction on the data is convolution operation, and the operation domain comprises a data address to be operated, a convolution kernel address and a target address.

In step S52, the operation module performs convolution operation on the data to be operated according to the convolution kernel to obtain an operation result, and stores the operation result in the target address.

In one possible implementation, performing a convolution operation on data to be operated according to a convolution kernel may include:

the multiplication operation in the convolution operation is performed using a plurality of multipliers, and the addition operation in the convolution operation is performed using a plurality of adders.

In one possible implementation, the operation module comprises a master operation submodule and a plurality of slave operation submodules, the slave operation submodules comprise a plurality of multipliers and a plurality of adders,

wherein, the method can also comprise: and analyzing the convolution instruction to obtain a plurality of operation instructions.

Wherein, the step S52 may include:

performing preorder processing on data to be operated and a convolution kernel by using a main operation submodule, and transmitting data and an operation instruction;

based on a plurality of multipliers and a plurality of adders in the slave operation submodule, performing intermediate operation in parallel according to transmitted data and an operation instruction to obtain a plurality of intermediate results;

and performing subsequent processing on the plurality of intermediate results by using the main operation sub-module to obtain operation results, and storing the operation results into the target address.

In one possible implementation, the operation field may further include a read input height and an input width. Acquiring data to be operated, a convolution kernel and a target address required for executing a convolution instruction according to an operation code and an operation domain may include:

and acquiring the data to be operated corresponding to the input width and the input height from the data address to be operated.

In one possible implementation, the operation domain may further include a convolution kernel height and a convolution kernel width. Acquiring data to be operated, a convolution kernel and a target address required for executing a convolution instruction according to an operation code and an operation domain may include: and acquiring the convolution kernel from the convolution kernel address according to the height and the width of the convolution kernel.

In a possible implementation manner, the operation domain may further include a first stride, where performing convolution operation on data to be operated according to a convolution kernel to obtain an operation result includes: the convolution kernel is moved in a first step in the X direction of the data to be computed.

In a possible implementation manner, the operation domain may further include a second stride, where performing convolution operation on the data to be operated on according to the convolution kernel to obtain an operation result includes: the convolution kernel is shifted by a second step in the Y direction of the data to be computed.

In one possible implementation, the operation domain may also include the number of convolution kernels. The performing convolution operation on the data to be operated according to the convolution kernel to obtain an operation result may include:

and carrying out convolution operation on the data to be operated through a plurality of convolution kernels with the number being the number of the convolution kernels.

In one possible implementation, the operation domain may further include a channel number. The performing convolution operation on the data to be operated according to the convolution kernel to obtain an operation result may include:

and performing convolution operation on the data to be operated through the corresponding channel according to the number of the channels to obtain an operation result.

In one possible implementation, the method may further include: the storage module of the device is used for storing the data to be operated and the convolution kernel,

wherein the memory module comprises at least one of a register and a cache,

the cache is used for storing data to be operated and a convolution kernel and comprises at least one neuron cache NRAM;

the register is used for storing scalar data in the data to be operated;

and the neuron cache is used for storing neuron data in the data to be operated, wherein the neuron data comprises neuron vector data.

In a possible implementation manner, parsing the obtained convolution instruction to obtain an operation code and an operation domain of the convolution instruction may include:

storing the convolution instruction;

analyzing the convolution instruction to obtain an operation code and an operation domain of the convolution instruction;

and storing an instruction queue, wherein the instruction queue comprises a plurality of instructions to be executed which are sequentially arranged according to an execution sequence, and the plurality of instructions to be executed can comprise convolution instructions.

In one possible implementation, the method may further include:

when determining that the first to-be-executed instruction in the plurality of to-be-executed instructions has an association relation with a zeroth to-be-executed instruction before the first to-be-executed instruction, caching the first to-be-executed instruction, after the zeroth to-be-executed instruction is executed, executing the first to-be-executed instruction,

the method for determining the zero-th instruction to be executed before the first instruction to be executed has an incidence relation with the first instruction to be executed comprises the following steps:

the first storage address interval for storing the data required by the first to-be-executed instruction and the zeroth storage address interval for storing the data required by the zeroth to-be-executed instruction have an overlapped area.

It should be noted that, although the convolution instruction processing method is described above by taking the above-described embodiment as an example, those skilled in the art will understand that the present disclosure should not be limited thereto. In fact, the user can flexibly set each step according to personal preference and/or actual application scene, as long as the technical scheme of the disclosure is met.

The convolution instruction processing method provided by the embodiment of the disclosure has the advantages of wide application range, high convolution instruction processing efficiency, high convolution instruction processing speed, and high convolution operation processing efficiency and speed.

The present disclosure also provides a non-transitory computer-readable storage medium having stored thereon computer program instructions that, when executed by a processor, implement the above-described convolution instruction processing method.

It is noted that while for simplicity of explanation, the foregoing method embodiments have been described as a series of acts or combination of acts, it will be appreciated by those skilled in the art that the present disclosure is not limited by the order of acts, as some steps may, in accordance with the present disclosure, occur in other orders and concurrently. Further, those skilled in the art will also appreciate that the embodiments described in the specification are exemplary embodiments and that acts and modules referred to are not necessarily required by the disclosure.

It should be further noted that, although the steps in the flowchart of fig. 6 are shown in sequence as indicated by the arrows, the steps are not necessarily executed in sequence as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a portion of the steps in fig. 6 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

It should be understood that the above-described apparatus embodiments are merely exemplary, and that the apparatus of the present disclosure may be implemented in other ways. For example, the division of the units/modules in the above embodiments is only one logical function division, and there may be another division manner in actual implementation. For example, multiple units, modules, or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented.

In addition, unless otherwise specified, each functional unit/module in the embodiments of the present disclosure may be integrated into one unit/module, each unit/module may exist alone physically, or two or more units/modules may be integrated together. The integrated units/modules may be implemented in the form of hardware or software program modules.

If the integrated unit/module is implemented in hardware, the hardware may be digital circuits, analog circuits, etc. Physical implementations of hardware structures include, but are not limited to, transistors, memristors, and the like. Unless otherwise specified, the storage module may be any suitable magnetic storage medium or magneto-optical storage medium, such as resistive Random Access Memory rram (resistive Random Access Memory), Dynamic Random Access Memory dram (Dynamic Random Access Memory), Static Random Access Memory SRAM (Static Random-Access Memory), enhanced Dynamic Random Access Memory edram (enhanced Dynamic Random Access Memory), High-Bandwidth Memory HBM (High-Bandwidth Memory), hybrid Memory cubic hmc (hybrid Memory cube), and so on.

The integrated units/modules, if implemented in the form of software program modules and sold or used as a stand-alone product, may be stored in a computer readable memory. Based on such understanding, the technical solution of the present disclosure may be embodied in the form of a software product, which is stored in a memory and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present disclosure. And the aforementioned memory comprises: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments. The technical features of the embodiments may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The foregoing may be better understood in light of the following clauses:

clause a1, a convolution instruction processing apparatus, the apparatus comprising:

Clause a2, the apparatus of clause a1, the computing module comprising:

a plurality of multipliers for performing multiplication operations of the convolution operations;

a plurality of adders for performing addition operations among the convolution operations.

Clause A3, the apparatus of clause a2, the arithmetic module comprising a master arithmetic sub-module and a plurality of slave arithmetic sub-modules, the slave arithmetic sub-modules comprising the plurality of multipliers and the plurality of adders,

the control module is further configured to analyze the convolution instruction to obtain a plurality of operation instructions, and send the data to be operated, the convolution kernel, and the plurality of operation instructions to the main operation sub-module;

the main operation submodule is used for executing preorder processing on the data to be operated and the convolution kernel and transmitting data and operation instructions with the plurality of slave operation submodules;

the slave operation submodule is used for executing intermediate operation in parallel according to the data and the operation instruction transmitted from the master operation submodule based on the multipliers and the adders to obtain a plurality of intermediate results and transmitting the intermediate results to the master operation submodule;

and the main operation sub-module is also used for executing subsequent processing on the plurality of intermediate results to obtain operation results and storing the operation results into the target address.

Clause a4, the apparatus of clause a1, the operation field further comprising an input height and an input width,

the control module is further configured to obtain data to be operated corresponding to the input width and the input height from the data address to be operated.

Clause a5, the apparatus of clause a1, the operation domain further comprising a convolution kernel height and a convolution kernel width,

the control module is further configured to obtain the convolution kernel from the convolution kernel address according to the convolution kernel height and the convolution kernel width.

Clause a6, the apparatus of clause a1, the operational domain further comprising a first stride,

the operation module is further configured to move the convolution kernel in the X direction of the data to be operated according to the first step.

Clause a7, the apparatus of clause a1, the operational domain further comprising a second stride,

and the operation module is also used for moving the convolution kernel in the Y direction of the data to be operated according to a second step.

Clause A8, the apparatus of clause a1, the operation domain further comprising a number of convolution kernels,

the operation module is further configured to perform convolution operation on the data to be operated through a plurality of convolution kernels, the number of which is the number of the convolution kernels.

Clause a9, the apparatus of clause a1, the operation domain further comprising a number of lanes,

the operation module is further configured to perform convolution operation on the data to be operated through the corresponding channel according to the number of the channels to obtain an operation result.

Clause a10, the apparatus of clause a1, further comprising:

a storage module for storing the data to be operated and the convolution kernel,

wherein the storage module comprises at least one of a register and a cache,

the cache is used for storing the data to be operated and the convolution kernel, and comprises at least one neuron cache NRAM;

the register is used for storing scalar data in the data to be operated;

the neuron cache is used for storing neuron data in the data to be operated, wherein the neuron data comprises neuron vector data.

Clause a11, the apparatus of clause a1, the control module comprising:

the instruction storage submodule is used for storing the convolution instruction;

the instruction processing submodule is used for analyzing the convolution instruction to obtain an operation code and an operation domain of the convolution instruction;

and the queue storage submodule is used for storing an instruction queue, the instruction queue comprises a plurality of instructions to be executed which are sequentially arranged according to an execution sequence, and the plurality of instructions to be executed comprise the convolution instructions.

Clause a12, the apparatus of clause a11, the control module further comprising:

the dependency relationship processing submodule is used for caching a first instruction to be executed in the instruction storage submodule when the fact that the first instruction to be executed in the plurality of instructions to be executed is associated with a zeroth instruction to be executed before the first instruction to be executed is determined, extracting the first instruction to be executed from the instruction storage submodule after the zeroth instruction to be executed is executed, and sending the first instruction to be executed to the operation module,

wherein the association relationship between the first to-be-executed instruction and a zeroth to-be-executed instruction before the first to-be-executed instruction comprises:

and a first storage address interval for storing the data required by the first instruction to be executed and a zeroth storage address interval for storing the data required by the zeroth instruction to be executed have an overlapped area.

Clause a13, a machine learning computing device, the device comprising:

one or more convolution instruction processing devices as described in any of clauses a 1-clause a12, configured to obtain data to be operated and control information from other processing devices, execute a specified machine learning operation, and transmit an execution result to other processing devices through an I/O interface;

Clause a14, a combination processing device, comprising:

the machine learning computing device, universal interconnect interface, and other processing device of clause a 13;

the machine learning arithmetic device interacts with the other processing devices to jointly complete the calculation operation designated by the user,

wherein the combination processing apparatus further comprises: and a storage device connected to the machine learning arithmetic device and the other processing device, respectively, for storing data of the machine learning arithmetic device and the other processing device.

Clause a15, a machine learning chip, the machine learning chip comprising:

the machine learning computing device of clause a13 or the combined processing device of clause a 14.

Clause a16, an electronic device, comprising:

the machine learning chip of clause a 15.

Clause a17, a card, comprising: a memory device, an interface device and a control device and a machine learning chip as described in clause a 15;

wherein the machine learning chip is connected with the storage device, the control device and the interface device respectively;

the storage device is used for storing data;

the interface device is used for realizing data transmission between the machine learning chip and external equipment;

and the control device is used for monitoring the state of the machine learning chip.

Clause a18, a convolution instruction processing method, applied to a convolution instruction processing apparatus including a control module and an operation module, the method comprising:

analyzing the obtained convolution instruction by using a control module to obtain an operation code and an operation domain of the convolution instruction, and obtaining data to be operated, a convolution kernel and a target address required by executing the convolution instruction according to the operation code and the operation domain;

performing convolution operation on the data to be operated according to the convolution core by using an operation module to obtain an operation result, storing the operation result into the target address,

Clause a19, the method of clause a18, performing convolution operation on the data to be operated according to the convolution kernel, including:

performing a multiplication operation of the convolution operations with a plurality of multipliers and performing an addition operation of the convolution operations with a plurality of adders.

Clause a20, the method of clause a19, the arithmetic module comprising a master arithmetic sub-module and a plurality of slave arithmetic sub-modules, the slave arithmetic sub-modules comprising the plurality of multipliers and the plurality of adders,

wherein the method further comprises:

analyzing the convolution instruction by using a control module to obtain a plurality of operation instructions;

performing convolution operation on the data to be operated according to the convolution core to obtain an operation result, and storing the operation result in the target address, wherein the method comprises the following steps:

performing preorder processing on the data to be operated and the convolution kernel by using the main operation submodule, and transmitting data and an operation instruction;

based on the multipliers and the adders in the slave operation submodule, performing intermediate operation in parallel according to transmitted data and operation instructions to obtain a plurality of intermediate results;

and utilizing the main operation sub-module to execute subsequent processing on the plurality of intermediate results to obtain an operation result, and storing the operation result into the target address.

Clause a21, the method of clause a18, the operation field further comprising a read input height and an input width,

acquiring data to be operated, a convolution kernel and a target address required by executing the convolution instruction according to the operation code and the operation domain, wherein the method comprises the following steps:

Clause a22, the method of clause a18, the operation domain further comprising a convolution kernel height and a convolution kernel width,

and acquiring the convolution kernel from the convolution kernel address according to the height of the convolution kernel and the width of the convolution kernel.

Clause a23, the method of clause a18, the operational domain further comprising a first stride,

performing convolution operation on the data to be operated according to the convolution kernel to obtain an operation result, including:

and moving the convolution kernel according to the first step in the X direction of the data to be operated.

Clause a24, the method of clause a18, the operational domain further comprising a second stride,

and moving the convolution kernel in the Y direction of the data to be operated according to a second step.

Clause a25, the method of clause a18, the operation domain further comprising a number of convolution kernels,

Clause a26, the method of clause a18, the operation domain further comprising a number of lanes,

Clause a27, the method of clause a18, the method further comprising:

storing the data to be operated and the convolution kernel by utilizing a storage module of the device,

wherein the storage module comprises at least one of a register and a cache,

the register is used for storing scalar data in the data to be operated;

Clause a28, parsing the obtained convolution instruction according to the method described in clause a18 to obtain the operation code and the operation domain of the convolution instruction, including:

storing the convolution instruction;

and storing an instruction queue, wherein the instruction queue comprises a plurality of instructions to be executed which are sequentially arranged according to an execution sequence, and the plurality of instructions to be executed comprise the convolution instructions.

Clause a29, the method of clause a28, the method further comprising:

when determining that the first to-be-executed instruction in the plurality of to-be-executed instructions is associated with a zeroth to-be-executed instruction before the first to-be-executed instruction, caching the first to-be-executed instruction, and after determining that the zeroth to-be-executed instruction is completely executed, controlling to execute the first to-be-executed instruction,

Clause a30, a non-transitory computer readable storage medium having computer program instructions stored thereon that, when executed by a processor, implement the method of any of clauses a 18-a 29.

The foregoing detailed description of the embodiments of the present application has been presented to illustrate the principles and implementations of the present application, and the above description of the embodiments is only provided to help understand the method and the core concept of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims

1. A convolution instruction processing apparatus, characterized in that the apparatus comprises:

2. The apparatus of claim 1, wherein the computing module comprises:

3. The apparatus of claim 2, wherein the operation module comprises a master operation submodule and a plurality of slave operation submodule, the slave operation submodule comprising the plurality of multipliers and the plurality of adders,

4. A machine learning arithmetic device, the device comprising:

one or more convolution instruction processing devices according to any one of claims 1 to 3, configured to acquire data to be operated on and control information from other processing devices, execute a specified machine learning operation, and transmit an execution result to the other processing devices through the I/O interface;

5. A combined processing apparatus, characterized in that the combined processing apparatus comprises:

the machine learning computing device, the universal interconnect interface, and the other processing device of claim 4;

6. A machine learning chip, the machine learning chip comprising:

the machine learning arithmetic device according to claim 4 or the combined processing device according to claim 5.

7. An electronic device, characterized in that the electronic device comprises:

the machine learning chip of claim 6.

8. The utility model provides a board card, its characterized in that, the board card includes: a memory device, an interface device and a control device and a machine learning chip according to claim 6;

the storage device is used for storing data;

9. A convolution instruction processing method is applied to a convolution instruction processing device, the device comprises a control module and an operation module, and the method comprises the following steps:

10. A non-transitory computer readable storage medium having computer program instructions stored thereon, wherein the computer program instructions, when executed by a processor, implement the method of claim 9.