CN111027057A - Detection method and device for chip hidden hardware and storage medium - Google Patents
Detection method and device for chip hidden hardware and storage medium Download PDFInfo
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Abstract
The embodiment of the invention discloses a method and a device for detecting hidden hardware of a chip and a storage medium, which relate to the technical field of chip safety and can effectively judge whether the hidden hardware exists in the chip. The method comprises the following steps: setting scan-related configuration parameters, including: address range of scanning, operation type of scanning; scanning the address space of the SoC to be tested based on the configuration parameters; capturing and analyzing the internal state of the SoC to be tested in the scanning process; the internal states include: hardware resource access states of the system environment and associated variable values or register values; capturing and analyzing the external state of the tested SoC in the scanning process; the external states include: the state of the chip output signal, the chip power consumption, or the chip thermal characteristics.
Description
Technical Field
The invention relates to the technical field of chip security, in particular to a method and a device for detecting hidden hardware of a chip and a storage medium.
Background
With the development of microelectronic technology, the number of transistors on a single integrated circuit chip can reach billions or even higher, and the complexity of chip functions and logic is very high. For a chip with a certain size and complexity, the design, verification and manufacturing workload of the chip is often completed by cooperation of a plurality of upstream and downstream companies in the whole industry. From an information security perspective, an integrated circuit chip may be maliciously tampered with in various stages of design and manufacture, such as by embedding malicious logic circuits for changing circuit functions in certain subtle situations or by revealing information under certain triggering conditions. As a highly complex system, malicious logic is highly covert, and detection and identification are very difficult.
Disclosure of Invention
In view of this, embodiments of the present invention provide a method, an apparatus, and a storage medium for detecting chip hidden hardware, which perform a large-scale scan operation on an address space of a SoC to be detected, and further observe an internal state and an external state of the SoC, so as to finally effectively determine whether a hardware hidden logic exists.
In a first aspect, an embodiment of the present invention provides a method for detecting a chip hidden hardware, including:
setting scan-related configuration parameters, including: address range of scanning, operation type of scanning;
scanning the address space of the SoC to be tested based on the configuration parameters;
capturing and analyzing the internal state of the SoC to be tested in the scanning process; the internal states include: hardware resource access states of the system environment and associated variable values or register values;
capturing and analyzing the external state of the tested SoC in the scanning process; the external states include: the state of the chip output signal, the chip power consumption, or the chip thermal characteristics.
According to a specific implementation manner of the embodiment of the present invention, the operation types of the scanning include: read operations, write operations, or a combination of read and write operations.
According to a specific implementation manner of the embodiment of the present invention, the scanning operation of the address space of the SoC to be tested based on the configuration parameters specifically includes: and performing Fuzzing test operation on the address space of the SoC to be tested based on the configuration parameters.
In a second aspect, an embodiment of the present invention provides an apparatus for detecting a hidden hardware on a chip, including:
the configuration generation module is used for setting configuration parameters related to scanning, and comprises: address range of scanning, operation type of scanning;
the upper computer control module is deployed on an upper computer and used for loading configuration parameters to the bus operation execution module;
the bus operation execution module is positioned in the tested SoC and used for scanning the address space of the tested SoC based on the configuration parameters;
the internal state capturing and analyzing module is used for capturing and analyzing the internal state of the SoC to be tested in the scanning process; the internal states include: hardware resource access states of the system environment and associated variable values or register values;
the external state capturing and analyzing module is used for capturing and analyzing the external state of the SoC to be tested in the scanning process; the external states include: the state of the chip output signal, the chip power consumption, or the chip thermal characteristics.
According to a specific implementation manner of the embodiment of the present invention, the operation types of the scanning include: read operations, write operations, or a combination of read and write operations.
According to a specific implementation manner of the embodiment of the invention, the bus operation execution module is specifically a tested SoC processor and an embedded software module thereon.
According to a specific implementation manner of the embodiment of the present invention, the internal state capturing and analyzing module is an embedded software module on the SoC processor under test, and is configured to perform a local analysis operation on the internal state in the SoC under test.
According to a specific implementation manner of the embodiment of the present invention, the bus operation execution module is specifically a JTAG controlled bus master device.
According to a specific implementation manner of the embodiment of the present invention, the internal state capturing and analyzing module is a software module running on an upper computer, and is configured to perform an internal state analyzing operation according to the original captured data returned by the bus operation executing module; wherein the raw capture data comprises: the operational process and the internal state captured by the Fuzzing process.
In a third aspect, embodiments of the present invention also provide a computer-readable storage medium storing one or more programs, which are executable by one or more processors to implement a method according to any one of the foregoing implementation manners.
According to the detection method, the detection device and the storage medium for the chip hidden hardware provided by the embodiment of the invention, the address space of the SoC to be detected is scanned based on the configuration parameters, the internal state and the external state of the chip in the scanning process are captured, and then whether the hidden hardware exists in the current chip is comprehensively analyzed and judged. The embodiment of the invention can not only avoid data leakage possibly caused by using an unsafe chip, but also avoid other more serious consequences.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of an address bus and various device modules thereon according to the present invention;
FIG. 2 is a flowchart illustrating a method for detecting hidden hardware on a chip according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an embodiment 1 of a detection apparatus for hidden hardware on a chip according to the present invention;
fig. 4 is a schematic structural diagram of an embodiment 2 of a detection apparatus for hidden hardware on a chip according to the present invention;
fig. 5 is a schematic structural diagram of an embodiment 3 of a detection apparatus for hidden hardware on a chip according to the present invention.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
There are often large reserved sections of chip processor memory address space. The address space is not accessed when the system is operating normally. These reserved address spaces are hidden from view and the user cannot learn the address space or what functional logic is present. These hidden spaces may have an implanted trojan logic access portal that, in some cases outside of the normal system function, enforces a secret fetch or attack.
In terms of hardware, as shown in fig. 1, each device module connected to the bus decodes a bus address of a certain segment, and enables a chip select signal when a read/write address on the bus hits its range; if the system has hidden malicious logic hardware connected to the bus, the system will decode the address of some section, and when the address hits the range, the system will enable its chip select signal to activate the function of the functional module. Therefore, when the scan hits the address range of the hidden logic, the result of the read/write operation is different from that of the normal reserved address, and the power consumption or the chip heat may be changed due to the activation of additional hardware circuits. These internal and external state feature changes can be used as clues to the discovery of hidden logic. Based on this, the present invention proposes the following embodiments for efficiently identifying and discovering the hidden hardware logic of a chip.
In a first aspect, an embodiment of the present invention provides a method for detecting a hidden hardware on a chip, which can effectively determine whether the hidden hardware exists on the chip.
Fig. 2 is a flowchart of an embodiment of a method for detecting a hidden hardware on a chip according to the present invention, including:
s101: setting configuration parameters related to scanning; the configuration parameters include, but are not limited to: address range of scan, operation type of scan.
Wherein the operation types of the scanning include: read operations, write operations, or a combination of read and write operations. More specifically, the write operation also needs to determine the data content of the write operation, and the read-write combination operation also needs to determine the repeated and alternate combination mode of each operation.
S102: and scanning the address space of the SoC to be tested based on the configuration parameters.
More preferably, the scanning operation of the address space of the SoC under test based on the configuration parameters specifically includes: and performing Fuzzing test operation on the address space of the SoC to be tested based on the configuration parameters.
Step S102 may be performed by the SoC processor under test and embedded software thereon, or may be performed by a JTAG-controlled bus master device.
S103: and capturing and analyzing the internal state of the tested SoC in the scanning process. The internal states include: hardware resource access states of the system environment and associated variable values or register values. Wherein, the related variable value refers to the variable involved in the interaction with the hardware; the register value refers to an SoC internal register resource and is used for completing functions of configuration, communication, data exchange and the like of an application layer and a hardware resource.
Step S103 may be performed by embedded software on the SoC processor under test or software on the upper computer.
S104: and capturing and analyzing the external state of the tested SoC in the scanning process. The external states include: the state of the chip output signal, the chip power consumption, or the chip thermal characteristics.
According to the method and the device, the large-scale scanning operation is performed on the SoC to be tested, the internal state and the external state of the SoC chip to be tested during the scanning period are obtained in real time, whether a hardware Trojan exists in the current chip is finally judged based on the internal state and the external state, and serious consequences such as data leakage possibly caused by the use of the chip with the abnormal state are avoided.
In a second aspect, an embodiment of the present invention provides a device for detecting a hidden hardware on a chip, which can effectively determine whether the hidden hardware exists on the chip.
Fig. 3 is a schematic structural diagram of an embodiment 1 of a detection apparatus for hidden hardware on a chip according to the present invention, where the apparatus of this embodiment may include:
the configuration generating module 301 is configured to set configuration parameters related to scanning, including: address range of scan, operation type of scan. Wherein the operation types of the scanning include: read operations, write operations, or a combination of read and write operations.
The upper computer control module 302 is deployed on an upper computer and used for loading configuration parameters to the bus operation execution module 303;
a bus operation execution module 303, located inside the SoC to be tested, for performing a scanning operation on an address space of the SoC to be tested based on the configuration parameters;
an internal state capturing and analyzing module 304, configured to capture and analyze an internal state of the SoC to be tested in the scanning process; the internal states include: hardware resource access states of the system environment and associated variable values or register values;
an external state capturing and analyzing module 305, configured to capture and analyze an external state of the SoC to be tested in the scanning process; the external states include: the state of the chip output signal, the chip power consumption, or the chip thermal characteristics.
According to the method and the device, the large-scale scanning operation is performed on the SoC to be detected, the internal state and the external state of the SoC to be detected during the scanning period are obtained in real time, the hardware Trojan horse of the chip is finally detected based on the internal state and the external state, and serious consequences such as data leakage possibly caused by the use of the chip with the abnormal state are avoided.
Fig. 4 is a schematic structural diagram of an embodiment 2 of a detection apparatus for hidden hardware on a chip, which is suitable for a situation where a processor on the chip is controllable and a scanning operation does not interfere with execution of the processor, where the apparatus of this embodiment may include:
the configuration generation module is used for setting configuration parameters related to scanning, and comprises: address range of scan, operation type of scan. Wherein the operation types of the scanning include: read operations, write operations, or a combination of read and write operations.
And the upper computer control module is deployed on the upper computer and used for loading configuration parameters to the bus operation execution module. The upper computer control module is also used for loading configuration parameters, a test execution program and a software program of the internal state capture analysis module into the SoC processor to be tested.
And the bus operation execution module is a tested SoC processor and an embedded software module on the tested SoC processor and is used for scanning the address space of the tested SoC based on the configuration parameters. The bus operation execution module is used as a main device on the bus and has the capability of initiating read-write operation to any address space on the bus.
The internal state capturing and analyzing module is an embedded software module on the SoC processor to be tested and is used for capturing and analyzing the internal state of the SoC to be tested in the scanning process; the internal states include: hardware resource access states of the system environment and associated variable values or register values.
The external state capturing and analyzing module is used for capturing and analyzing the external state of the SoC to be tested in the scanning process; the external states include: the state of the chip output signal, the chip power consumption, or the chip thermal characteristics.
The present embodiment is applicable in situations where the on-chip processor is controllable and the scan operation does not interfere with the processor execution. The present embodiment performs the scan operation and the capture and analysis of the internal state by the SoC processor under test and the embedded software module thereon, and at the same time, the capture and analysis of the external state is realized by the external state capture and analysis module. And finally, judging whether hidden hardware exists in the tested SoC or not by combining the analysis results of the internal state and the external state.
Fig. 5 is a schematic structural diagram of an embodiment 3 of a detection apparatus for hidden hardware on a chip according to the present invention, which is suitable for a situation where a processor on the chip is unavailable or a scan test process may affect a normal execution procedure of the processor, where the apparatus of the embodiment may include:
the configuration generation module is used for setting configuration parameters related to scanning, and comprises: address range of scanning, operation type of scanning; the operation types of the scanning include: read operations, write operations, or a combination of read and write operations.
The upper computer control module is deployed on an upper computer and used for loading configuration parameters to the bus operation execution module;
the bus operation execution module is positioned in the tested SoC, is specifically a JTAG controlled bus master device and is used for scanning the address space of the tested SoC based on the configuration parameters; the bus operation execution module as a master device on the bus has the capability of initiating read-write operation to any address space on the bus, can perform read-write operation according to configuration parameters issued by the upper computer control module, and returns original captured data in the scanning operation process to the upper computer control module.
The internal state capturing and analyzing module is a software module running on an upper computer and is used for performing internal state analyzing operation according to the original capturing data returned by the bus operation executing module; the internal states include: hardware resource access states of the system environment and associated variable values or register values; wherein the raw capture data comprises: the operational process and the internal state captured by the Fuzzing process.
The external state capturing and analyzing module is used for capturing and analyzing the external state of the SoC to be tested in the scanning process; the external states include: the state of the chip output signal, the chip power consumption, or the chip thermal characteristics.
This embodiment is applicable in situations where the on-chip processor is not controllable or where scan operations may interfere with the processor's execution. In the embodiment, the DAP controller controlled by the JTAG test interface on the SoC to be tested specifically executes the scan test operation, feeds back the data of the internal state change in the scan test to the upper computer, performs the analysis operation of the internal state data by the internal state capture analysis module positioned on the upper computer, and simultaneously realizes the capture and analysis of the external state by the external state capture analysis module. And finally, judging whether hidden hardware exists in the tested SoC or not by combining the analysis results of the internal state and the external state.
In a third aspect, embodiments of the present invention also provide a computer-readable storage medium storing one or more programs, which are executable by one or more processors to implement a method according to any one of the foregoing implementation manners.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments.
In particular, as for the apparatus embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
For convenience of description, the above devices are described separately in terms of functional division into various units/modules. Of course, the functionality of the units/modules may be implemented in one or more software and/or hardware implementations of the invention.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A method for detecting chip hidden hardware is characterized by comprising the following steps:
setting scan-related configuration parameters, including: address range of scanning, operation type of scanning;
scanning the address space of the SoC to be tested based on the configuration parameters;
capturing and analyzing the internal state of the SoC to be tested in the scanning process; the internal states include: hardware resource access states of the system environment and associated variable values or register values;
capturing and analyzing the external state of the tested SoC in the scanning process; the external states include: the state of the chip output signal, the chip power consumption, or the chip thermal characteristics.
2. The detection method of claim 1, wherein the operation type of the scanning comprises: read operations, write operations, or a combination of read and write operations.
3. The detection method according to claim 1, wherein the scanning operation is performed on the address space of the SoC under test based on the configuration parameters, specifically: and performing Fuzzing test operation on the address space of the SoC to be tested based on the configuration parameters.
4. An apparatus for detecting a hidden hardware on a chip, comprising:
the configuration generation module is used for setting configuration parameters related to scanning, and comprises: address range of scanning, operation type of scanning;
the upper computer control module is deployed on an upper computer and used for loading configuration parameters to the bus operation execution module;
the bus operation execution module is positioned in the tested SoC and used for scanning the address space of the tested SoC based on the configuration parameters;
the internal state capturing and analyzing module is used for capturing and analyzing the internal state of the SoC to be tested in the scanning process; the internal states include: hardware resource access states of the system environment and associated variable values or register values;
the external state capturing and analyzing module is used for capturing and analyzing the external state of the SoC to be tested in the scanning process; the external states include: the state of the chip output signal, the chip power consumption, or the chip thermal characteristics.
5. The detection apparatus as claimed in claim 4, wherein the operation type of the scanning includes: read operations, write operations, or a combination of read and write operations.
6. The detection apparatus according to claim 4, wherein the bus operation execution module is specifically a SoC processor under test and an embedded software module thereon.
7. The detection apparatus of claim 6, wherein the internal state capture analysis module is an embedded software module on a SoC processor under test to perform local analysis operations on internal states within the SoC under test.
8. The detection apparatus according to claim 4, wherein the bus operation execution module is specifically a JTAG controlled bus master.
9. The detection device according to claim 8, wherein the internal state capturing and analyzing module is a software module running on an upper computer and configured to perform an internal state analyzing operation according to the raw captured data returned by the bus operation executing module; wherein the raw capture data comprises: the operational process and the internal state captured by the Fuzzing process.
10. A computer readable storage medium, characterized in that the computer readable storage medium stores one or more programs which are executable by one or more processors to implement the method of any preceding claim.
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| CN112685241A (en) * | 2021-01-27 | 2021-04-20 | 中国科学院微电子研究所 | Multi-granularity memory detection method, memory device and electronic device |
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