CN111026571B - Processor down-conversion processing method and device and electronic equipment - Google Patents
Processor down-conversion processing method and device and electronic equipment Download PDFInfo
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0709—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a distributed system consisting of a plurality of standalone computer nodes, e.g. clusters, client-server systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
- G06F11/0724—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU] in a multiprocessor or a multi-core unit
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The embodiment of the disclosure provides a method and a device for processing down frequency of a processor and electronic equipment, belonging to the technical field of data processing, wherein the method comprises the following steps: determining an actual operating frequency of the target processor based on the acquired TSC frequency, the actual frequency variable and the reference frequency variable; determining a frequency deviation value of the target processor based on the actual operating frequency and a desired operating frequency of the target processor; when the frequency deviation value is larger than a first threshold value, further acquiring an actual power consumption value of the target processor; and when the actual power consumption value is smaller than a second threshold value, filtering the target processor. Through the scheme of the disclosure, the fault processor can be identified and processed rapidly and accurately.
Description
Technical Field
The disclosure relates to the technical field of data processing, and in particular relates to a method and a device for processing down frequency of a processor and electronic equipment.
Background
A data center is a worldwide collaboration of specific equipment networks used to communicate, accelerate, expose, calculate, store data information over the internet infrastructure. Most of the electronic components of the data center are driven to operate by a low-DC power supply. The generation of data centers has led to the recognition of people from the quantitative, structural world into the uncertainty and unstructured world, which will gradually become part of the modern social infrastructure as well as traffic, network communications, and thus have a positive impact on many industries.
The data center is composed of innumerable computer hardware, and problems occur in the hardware, so that part of functions cannot be normally exerted or operated. The data center often has some complicated reasons to cause dynamic change of the running frequency of the CPU, so that performance of a single machine and the performance of the same-configuration machines of the cluster are different, and the processing efficiency of the whole data center is affected.
Disclosure of Invention
In view of this, embodiments of the present disclosure provide a method, an apparatus, and an electronic device for processing down-conversion of a processor, which at least partially solve the problems in the prior art.
In a first aspect, an embodiment of the present disclosure provides a method for performing a frequency-down processing on a processor, including:
determining an actual operating frequency of the target processor based on the acquired TSC frequency, the actual frequency variable and the reference frequency variable;
determining a frequency deviation value of the target processor based on the actual operating frequency and a desired operating frequency of the target processor;
when the frequency deviation value is larger than a first threshold value, further acquiring an actual power consumption value of the target processor;
and when the actual power consumption value is smaller than a second threshold value, filtering the target processor.
According to a specific implementation manner of the embodiment of the present disclosure, the determining the actual operating frequency of the target processor based on the acquired TSC frequency, the actual frequency variable and the reference frequency variable includes:
dividing the actual frequency variable and the reference frequency variable to obtain a frequency ratio;
and determining the product of the frequency ratio and the TSC frequency as the actual operating frequency of the target processor.
According to a specific implementation manner of the embodiment of the present disclosure, the determining the actual operating frequency of the target processor based on the acquired TSC frequency, the actual frequency variable and the reference frequency variable includes:
and acquiring the TSC frequency, the actual frequency variable and the reference frequency variable of the target processor in real time at intervals of a preset time period.
According to a specific implementation manner of the embodiment of the present disclosure, the determining, based on the actual operating frequency and the expected operating frequency of the target processor, a frequency deviation value of the target processor includes:
calculating a frequency difference between the actual operating frequency and the desired operating frequency;
and determining the absolute value of the frequency difference value and determining a frequency deviation value for the target processor.
According to a specific implementation manner of the embodiment of the present disclosure, before the determining, based on the actual operating frequency and the expected operating frequency of the target processor, the frequency deviation value of the target processor, the method further includes:
sending a request for acquiring expected operating frequency to a target server;
analyzing a response request sent by the target server aiming at the expected operating frequency acquisition request to obtain an analysis result;
and determining the expected operating frequency of the target processor based on the analysis result.
According to a specific implementation manner of the embodiment of the present disclosure, before further obtaining the actual power consumption value of the target processor when the frequency deviation value is greater than the first threshold, the method further includes:
acquiring a first threshold corresponding to the target processor;
and judging whether the frequency deviation value is larger than the first threshold value.
According to a specific implementation manner of the embodiment of the present disclosure, the obtaining the actual power consumption value of the target processor includes:
acquiring an ID (identity) of a target processor;
the ID identification and the power query request are sent to a target server;
an actual power consumption value of the target processor is determined based on the power response of the target server.
According to a specific implementation manner of the embodiment of the present disclosure, when the actual power consumption value is smaller than a second threshold, filtering processing is performed on the target processor, including:
deleting the identification of the target processor in a data center processor cluster;
and stopping the operation of the target processor after the identification of the target processor is deleted.
In a second aspect, an embodiment of the present disclosure provides a processor down-conversion processing apparatus, including:
the first determining module is used for determining the actual running frequency of the target processor based on the acquired TSC frequency, the actual frequency variable and the reference frequency variable;
a second determining module, configured to determine a frequency deviation value of the target processor based on the actual operating frequency and a desired operating frequency of the target processor;
the acquisition module is used for further acquiring an actual power consumption value of the target processor when the frequency deviation value is larger than a first threshold value;
and the execution module is used for executing filtering processing on the target processor when the actual power consumption value is smaller than a second threshold value.
In a third aspect, embodiments of the present disclosure further provide an electronic device, including:
at least one processor; the method comprises the steps of,
a memory communicatively coupled to the at least one processor; wherein, the liquid crystal display device comprises a liquid crystal display device,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the processor downscaling method of any one of the foregoing Ren Di or first aspect implementations.
In a fourth aspect, embodiments of the present disclosure also provide a non-transitory computer readable storage medium storing computer instructions for causing the computer to perform the method of down-converting a processor in the foregoing first aspect or any implementation of the first aspect.
In a fifth aspect, embodiments of the present disclosure also provide a computer program product comprising a computer program stored on a non-transitory computer readable storage medium, the computer program comprising program instructions which, when executed by a computer, cause the computer to perform the processor down-conversion processing method of the first aspect or any implementation manner of the first aspect.
The processor frequency-reducing processing scheme in the embodiment of the disclosure comprises the steps of determining the actual running frequency of a target processor based on the acquired TSC frequency, the actual frequency variable and the reference frequency variable; determining a frequency deviation value of the target processor based on the actual operating frequency and a desired operating frequency of the target processor; when the frequency deviation value is larger than a first threshold value, further acquiring an actual power consumption value of the target processor; and when the actual power consumption value is smaller than a second threshold value, filtering the target processor. Through the scheme disclosed by the invention, the fault processor can be automatically identified and processed.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to a person of ordinary skill in the art.
Fig. 1 is a schematic diagram of a down-conversion processing flow of a processor according to an embodiment of the disclosure;
fig. 2 is a schematic diagram of another down-conversion processing flow of a processor according to an embodiment of the disclosure;
fig. 3 is a schematic diagram of another down-conversion processing flow of a processor according to an embodiment of the disclosure;
fig. 4 is a schematic diagram of another down-conversion processing flow of a processor according to an embodiment of the disclosure;
fig. 5 is a schematic structural diagram of a frequency-reducing processing device of a processor according to an embodiment of the disclosure;
fig. 6 is a schematic diagram of an electronic device according to an embodiment of the disclosure.
Detailed Description
Embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.
Other advantages and effects of the present disclosure will become readily apparent to those skilled in the art from the following disclosure, which describes embodiments of the present disclosure by way of specific examples. It will be apparent that the described embodiments are merely some, but not all embodiments of the present disclosure. The disclosure may be embodied or practiced in other different specific embodiments, and details within the subject specification may be modified or changed from various points of view and applications without departing from the spirit of the disclosure. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict. All other embodiments, which can be made by one of ordinary skill in the art without inventive effort, based on the embodiments in this disclosure are intended to be within the scope of this disclosure.
It is noted that various aspects of the embodiments are described below within the scope of the following claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the present disclosure, one skilled in the art will appreciate that one aspect described herein may be implemented independently of any other aspect, and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented and/or a method practiced using any number of the aspects set forth herein. In addition, such apparatus may be implemented and/or such methods practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.
It should also be noted that the illustrations provided in the following embodiments merely illustrate the basic concepts of the disclosure by way of illustration, and only the components related to the disclosure are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
In addition, in the following description, specific details are provided in order to provide a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects may be practiced without these specific details.
The embodiment of the disclosure provides a frequency-reducing processing method for a processor. The method for processing down-conversion of a processor provided in this embodiment may be performed by a computing device, which may be implemented as software, or as a combination of software and hardware, and the computing device may be integrally provided in a server, a terminal device, or the like.
Referring to fig. 1, a method for processing down-conversion of a processor according to an embodiment of the present disclosure includes the following steps:
s101, determining the actual running frequency of the target processor based on the acquired TSC frequency, the actual frequency variable and the reference frequency variable.
Data centers typically contain a large number of processors that can be subject to failure of some of the processors during long periods of operation. Since the processors are distributed in an array or the like, when a certain processor fails, it is difficult to check out in time.
For this purpose, real-time operation data of each processor (for example, the target processor) of the data center may be periodically acquired, and whether the processor fails may be further determined by whether the operation data of each processor is abnormal.
As one embodiment, the TSC frequency, the actual frequency number, and the reference frequency number of the target processor may be acquired, and the actual operating frequency of the target processor may be determined by the TSC frequency, the actual frequency number, and the reference frequency number.
Specifically, the actual frequency variable may be divided by the reference frequency variable to obtain a frequency ratio, and then the frequency ratio is multiplied by the TSC frequency to obtain the actual operating frequency of the target processor.
S102, determining a frequency deviation value of the target processor based on the actual operating frequency and the expected operating frequency of the target processor.
The target processor may develop a desired operating frequency during long-term operation, the desired operating frequency indicating a frequency value of the target processor in a normal operating state. To this end, the desired operating frequency of the target processor may be obtained by sending a request to the target server. The target server is a server of the data center for managing all processors, and frequency values of all the processors in a period of time are recorded on the target server, and expected operating frequencies of the target processors can be calculated through the frequency values.
After the expected operating frequency of the target processor is obtained, a difference operation may be performed between the actual operating frequency and the expected operating frequency, and an absolute value of a result of the difference operation may be used as a frequency deviation value of the target processor. The difference between the actual operating condition and the expected operating condition of the target processor can be characterized by the frequency deviation value.
And S103, when the frequency deviation value is larger than a first threshold value, further acquiring an actual power consumption value of the target processor.
In the actual running process of the target processor, the frequency of the processor can fluctuate due to different working contents. However, at the same time, the data center can perform load balancing processing on tasks on massive processors, so that the deviation value of each processor is not too large.
Based on this, the first threshold value may be set for the deviation value, and by comparing whether the frequency deviation value of the target processor is greater than the first threshold value, it may be determined whether or not the target processor has an abnormality.
When the frequency deviation value is greater than the first threshold value, in order to further assist in judging whether the target processor is abnormal, the actual power consumption value of the target processor may be further acquired. The actual power consumption value of the target processor can characterize the operating state of the target processor from the other side. Generally, the smaller the frequency deviation value of the target processor, the larger the actual power consumption value of the target processor.
And S104, when the actual power consumption value is smaller than a second threshold value, filtering processing is executed on the target processor.
Different processors have different power consumption values, for which purpose the model of the target processor may be acquired based on the ID of the target processor, thereby further acquiring a second threshold value corresponding to the power consumption value of the target processor. The second threshold may be set according to the actual situation to indicate whether the processor is in a normal power consumption operation state.
When the actual power consumption value of the target processor is found to be smaller than the second threshold value through comparison, the target processor can be identified to have abnormality, and filtering processing can be performed on the target processor. For example, a target processor with an exception may be directly culled in the data center.
By the scheme in the embodiment, whether the target processor is abnormal or not can be judged based on the frequency deviation value and the actual power consumption value of the target processor, so that the abnormal processor can be removed timely.
Referring to fig. 2, according to a specific implementation manner of the embodiment of the disclosure, the determining, based on the acquired TSC frequency, the actual frequency variable, and the reference frequency variable, an actual operating frequency of the target processor includes:
s201, dividing the actual frequency variable and the reference frequency variable to obtain a frequency ratio;
s202, determining the product of the frequency ratio and the TSC frequency as the actual operating frequency of the target processor.
In this way, the actual operating frequency of the target processor can be rapidly calculated.
According to a specific implementation manner of the embodiment of the present disclosure, the determining the actual operating frequency of the target processor based on the acquired TSC frequency, the actual frequency variable and the reference frequency variable includes: and acquiring the TSC frequency, the actual frequency variable and the reference frequency variable of the target processor in real time at intervals of a preset time period. The state of the target processor can be monitored in real time by periodically acquiring the relevant parameters of the target processor.
According to a specific implementation manner of the embodiment of the present disclosure, the determining, based on the actual operating frequency and the expected operating frequency of the target processor, a frequency deviation value of the target processor includes: calculating a frequency difference between the actual operating frequency and the desired operating frequency; and determining the absolute value of the frequency difference value and determining a frequency deviation value for the target processor. By calculating the frequency deviation value of the target processor, it can be further judged whether the target processor has an abnormality.
Referring to fig. 3, before determining the frequency deviation value of the target processor based on the actual operating frequency and the desired operating frequency of the target processor, according to a specific implementation of the embodiment of the present disclosure, the method further includes:
s301, sending a request for acquiring expected operation frequency to a target server.
The target processor may develop a desired operating frequency during long-term operation, the desired operating frequency indicating a frequency value of the target processor in a normal operating state. To this end, the desired operating frequency of the target processor may be obtained by sending a request to the target server.
S302, analyzing a response request sent by the target server aiming at the expected operating frequency acquisition request to obtain an analysis result.
S303, determining the expected operating frequency of the target processor based on the analysis result.
By means of the method, the expected operating frequency of the target processor can be obtained rapidly.
According to a specific implementation manner of the embodiment of the present disclosure, before further obtaining the actual power consumption value of the target processor when the frequency deviation value is greater than the first threshold, the method further includes: acquiring a first threshold corresponding to the target processor; and judging whether the frequency deviation value is larger than the first threshold value. By judging whether the frequency deviation value is larger than the first threshold value, whether the target processor has an abnormality can be further judged.
Referring to fig. 4, according to a specific implementation manner of the embodiment of the disclosure, the obtaining the actual power consumption value of the target processor includes:
s401, obtaining an ID identification of a target processor.
Different processors have different power consumption values, for which the model of the target processor can be obtained based on the ID of the target processor, for which the model of the target processor can be identified by reading the ID identification of the target processor.
S402, the ID identification and the power query request are sent to a target server.
By transmitting the ID identification and the power inquiry request to the target server, the actual power consumption value corresponding to the target processor can be inquired in the target server.
S403, determining an actual power consumption value of the target processor based on the power response of the target server.
By means of the scheme of the embodiment, the actual power consumption value of the target processor can be quickly inquired.
According to a specific implementation manner of the embodiment of the present disclosure, when the actual power consumption value is smaller than a second threshold, filtering processing is performed on the target processor, including: deleting the identification of the target processor in a data center processor cluster; and stopping the operation of the target processor after the identification of the target processor is deleted. By the method, the processor in the abnormal state can be removed timely.
Corresponding to the above method embodiment, referring to fig. 5, the embodiment of the present disclosure further provides a processor down-conversion processing device 50, including:
the first determining module 501 is configured to determine an actual operating frequency of the target processor based on the acquired TSC frequency, the actual frequency number and the reference frequency number.
Data centers typically contain a large number of processors that can be subject to failure of some of the processors during long periods of operation. Since the processors are distributed in an array or the like, when a certain processor fails, it is difficult to check out in time.
For this purpose, real-time operation data of each processor (for example, the target processor) of the data center may be periodically acquired, and whether the processor fails may be further determined by whether the operation data of each processor is abnormal.
As one embodiment, the TSC frequency, the actual frequency number, and the reference frequency number of the target processor may be acquired, and the actual operating frequency of the target processor may be determined by the TSC frequency, the actual frequency number, and the reference frequency number.
Specifically, the actual frequency variable may be divided by the reference frequency variable to obtain a frequency ratio, and then the frequency ratio is multiplied by the TSC frequency to obtain the actual operating frequency of the target processor.
A second determining module 502 is configured to determine a frequency deviation value of the target processor based on the actual operating frequency and the expected operating frequency of the target processor.
The target processor may develop a desired operating frequency during long-term operation, the desired operating frequency indicating a frequency value of the target processor in a normal operating state. To this end, the desired operating frequency of the target processor may be obtained by sending a request to the target server. The target server is a server of the data center for managing all processors, and frequency values of all the processors in a period of time are recorded on the target server, and expected operating frequencies of the target processors can be calculated through the frequency values.
After the expected operating frequency of the target processor is obtained, a difference operation may be performed between the actual operating frequency and the expected operating frequency, and an absolute value of a result of the difference operation may be used as a frequency deviation value of the target processor. The difference between the actual operating condition and the expected operating condition of the target processor can be characterized by the frequency deviation value.
An obtaining module 503, configured to further obtain an actual power consumption value of the target processor when the frequency deviation value is greater than a first threshold value.
In the actual running process of the target processor, the frequency of the processor can fluctuate due to different working contents. However, at the same time, the data center can perform load balancing processing on tasks on massive processors, so that the deviation value of each processor is not too large.
Based on this, the first threshold value may be set for the deviation value, and by comparing whether the frequency deviation value of the target processor is greater than the first threshold value, it may be determined whether or not the target processor has an abnormality.
When the frequency deviation value is greater than the first threshold value, in order to further assist in judging whether the target processor is abnormal, the actual power consumption value of the target processor may be further acquired. The actual power consumption value of the target processor can characterize the operating state of the target processor from the other side. Generally, the smaller the frequency deviation value of the target processor, the larger the actual power consumption value of the target processor.
An execution module 504, configured to execute a filtering process on the target processor when the actual power consumption value is smaller than a second threshold value.
Different processors have different power consumption values, for which purpose the model of the target processor may be acquired based on the ID of the target processor, thereby further acquiring a second threshold value corresponding to the power consumption value of the target processor. The second threshold may be set according to the actual situation to indicate whether the processor is in a normal power consumption operation state.
When the actual power consumption value of the target processor is found to be smaller than the second threshold value through comparison, the target processor can be identified to have abnormality, and filtering processing can be performed on the target processor. For example, a target processor with an exception may be directly culled in the data center.
By the scheme in the embodiment, whether the target processor is abnormal or not can be judged based on the frequency deviation value and the actual power consumption value of the target processor, so that the abnormal processor can be removed timely.
The apparatus shown in fig. 5 may correspondingly execute the content in the foregoing method embodiment, and the portions not described in detail in this embodiment refer to the content described in the foregoing method embodiment, which are not described herein again.
Referring to fig. 6, an embodiment of the present disclosure also provides an electronic device 60, comprising:
at least one processor; the method comprises the steps of,
a memory communicatively coupled to the at least one processor; wherein, the liquid crystal display device comprises a liquid crystal display device,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the processor downscaling method of the foregoing method embodiments.
The disclosed embodiments also provide a non-transitory computer readable storage medium storing computer instructions for causing the computer to perform the foregoing method embodiments.
The disclosed embodiments also provide a computer program product comprising a computer program stored on a non-transitory computer readable storage medium, the computer program comprising program instructions which, when executed by a computer, cause the computer to perform the processor down-conversion processing method of the foregoing method embodiments.
Referring now to fig. 6, a schematic diagram of an electronic device 60 suitable for use in implementing embodiments of the present disclosure is shown. The electronic devices in the embodiments of the present disclosure may include, but are not limited to, mobile terminals such as mobile phones, notebook computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and the like, and stationary terminals such as digital TVs, desktop computers, and the like. The electronic device shown in fig. 6 is merely an example and should not be construed to limit the functionality and scope of use of the disclosed embodiments.
As shown in fig. 6, the electronic device 60 may include a processing means (e.g., a central processing unit, a graphics processor, etc.) 601, which may perform various appropriate actions and processes according to a program stored in a Read Only Memory (ROM) 602 or a program loaded from a storage means 608 into a Random Access Memory (RAM) 603. In the RAM 603, various programs and data necessary for the operation of the electronic device 60 are also stored. The processing device 601, the ROM 602, and the RAM 603 are connected to each other through a bus 604. An input/output (I/O) interface 605 is also connected to bus 604.
In general, the following devices may be connected to the I/O interface 605: input devices 606 including, for example, a touch screen, touchpad, keyboard, mouse, image sensor, microphone, accelerometer, gyroscope, etc.; an output device 607 including, for example, a Liquid Crystal Display (LCD), a speaker, a vibrator, and the like; storage 608 including, for example, magnetic tape, hard disk, etc.; and a communication device 609. The communication means 609 may allow the electronic device 60 to communicate with other devices wirelessly or by wire to exchange data. While an electronic device 60 having various means is shown, it is to be understood that not all of the illustrated means are required to be implemented or provided. More or fewer devices may be implemented or provided instead.
In particular, according to embodiments of the present disclosure, the processes described above with reference to flowcharts may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a computer readable medium, the computer program comprising program code for performing the method shown in the flowcharts. In such an embodiment, the computer program may be downloaded and installed from a network via communication means 609, or from storage means 608, or from ROM 602. The above-described functions defined in the methods of the embodiments of the present disclosure are performed when the computer program is executed by the processing device 601.
It should be noted that the computer readable medium described in the present disclosure may be a computer readable signal medium or a computer readable storage medium, or any combination of the two. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this disclosure, a computer-readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In the present disclosure, however, the computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, with the computer-readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: electrical wires, fiber optic cables, RF (radio frequency), and the like, or any suitable combination of the foregoing.
The computer readable medium may be contained in the electronic device; or may exist alone without being incorporated into the electronic device.
The computer readable medium carries one or more programs which, when executed by the electronic device, cause the electronic device to: acquiring at least two internet protocol addresses; sending a node evaluation request comprising the at least two internet protocol addresses to node evaluation equipment, wherein the node evaluation equipment selects an internet protocol address from the at least two internet protocol addresses and returns the internet protocol address; receiving an Internet protocol address returned by the node evaluation equipment; wherein the acquired internet protocol address indicates an edge node in the content distribution network.
Alternatively, the computer-readable medium carries one or more programs that, when executed by the electronic device, cause the electronic device to: receiving a node evaluation request comprising at least two internet protocol addresses; selecting an internet protocol address from the at least two internet protocol addresses; returning the selected internet protocol address; wherein the received internet protocol address indicates an edge node in the content distribution network.
Computer program code for carrying out operations of the present disclosure may be written in one or more programming languages, including an object oriented programming language such as Java, smalltalk, C ++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider).
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The units involved in the embodiments of the present disclosure may be implemented by means of software, or may be implemented by means of hardware. The name of the unit does not in any way constitute a limitation of the unit itself, for example the first acquisition unit may also be described as "unit acquiring at least two internet protocol addresses".
It should be understood that portions of the present disclosure may be implemented in hardware, software, firmware, or a combination thereof.
The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the disclosure are intended to be covered by the protection scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (7)
1. A method for down-conversion processing by a processor, comprising:
dividing the actual frequency variable and the reference frequency variable based on the acquired TSC frequency, the actual frequency variable and the reference frequency variable of the target processor to obtain a frequency ratio, and determining the product of the frequency ratio and the TSC frequency as the actual running frequency of the target processor;
calculating a frequency difference value between the actual operating frequency and the expected operating frequency, and determining an absolute value of the frequency difference value as a frequency deviation value of the target processor; wherein the expected operating frequency is determined by calculation from a plurality of historical frequency values;
when the frequency deviation value is larger than a first threshold value, further acquiring an actual power consumption value of the target processor;
when the actual power consumption value is smaller than a second threshold value, filtering processing is performed on the target processor; the method comprises the following steps: deleting the identification of the target processor in a data center processor cluster; and stopping the operation of the target processor after the identification of the target processor is deleted.
2. The method of claim 1, wherein determining the actual operating frequency of the target processor based on the acquired TSC frequency, the actual frequency number, and the reference frequency number comprises:
and acquiring the TSC frequency, the actual frequency variable and the reference frequency variable of the target processor in real time at intervals of a preset time period.
3. The method of claim 1, wherein the method further comprises, prior to further obtaining the actual power consumption value of the target processor when the frequency deviation value is greater than a first threshold value:
acquiring a first threshold corresponding to the target processor;
and judging whether the frequency deviation value is larger than the first threshold value.
4. The method of claim 1, wherein the obtaining the actual power consumption value of the target processor comprises:
acquiring an ID (identity) of a target processor;
the ID identification and the power query request are sent to a target server;
an actual power consumption value of the target processor is determined based on the power response of the target server.
5. A processor down-conversion processing apparatus, comprising:
the first determining module is used for dividing the actual frequency variable and the reference frequency variable based on the acquired TSC frequency, the actual frequency variable and the reference frequency variable of the target processor to obtain a frequency ratio, and determining the product of the frequency ratio and the TSC frequency as the actual running frequency of the target processor;
the second determining module is used for calculating a frequency difference value between the actual operating frequency and the expected operating frequency, and determining an absolute value of the frequency difference value as a frequency deviation value of the target processor; wherein the expected operating frequency is determined by calculation from a plurality of historical frequency values;
the acquisition module is used for further acquiring an actual power consumption value of the target processor when the frequency deviation value is larger than a first threshold value;
an execution module, configured to execute filtering processing on the target processor when the actual power consumption value is smaller than a second threshold value; the method comprises the following steps: deleting the identification of the target processor in a data center processor cluster; and stopping the operation of the target processor after the identification of the target processor is deleted.
6. An electronic device, characterized in that the electronic device comprises:
at least one processor; the method comprises the steps of,
a memory communicatively coupled to the at least one processor; wherein, the liquid crystal display device comprises a liquid crystal display device,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the processor downscaling method of any one of claims 1-4.
7. A non-transitory computer readable storage medium storing computer instructions for causing the computer to perform the processor down-conversion processing method of any one of claims 1-4.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104246653A (en) * | 2012-04-10 | 2014-12-24 | 国际商业机器公司 | Minimizing power consumption for fixed-frequency processing unit operation |
| WO2018040670A1 (en) * | 2016-08-31 | 2018-03-08 | 深圳市中兴微电子技术有限公司 | Frequency reduction method and device for public resource, and computer storage medium |
| CN108886548A (en) * | 2017-02-24 | 2018-11-23 | 华为技术有限公司 | A kind of method, electronic equipment and the storage medium of the device power consumption of determining electronic equipment |
| CN109710482A (en) * | 2018-11-20 | 2019-05-03 | 广东优世联合控股集团股份有限公司 | A kind of electronic component performance detection method, device, readable medium and electronic equipment |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040268159A1 (en) * | 2003-06-30 | 2004-12-30 | Microsoft Corporation | Power profiling |
-
2019
- 2019-11-11 CN CN201911092417.4A patent/CN111026571B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104246653A (en) * | 2012-04-10 | 2014-12-24 | 国际商业机器公司 | Minimizing power consumption for fixed-frequency processing unit operation |
| WO2018040670A1 (en) * | 2016-08-31 | 2018-03-08 | 深圳市中兴微电子技术有限公司 | Frequency reduction method and device for public resource, and computer storage medium |
| CN107801231A (en) * | 2016-08-31 | 2018-03-13 | 深圳市中兴微电子技术有限公司 | A kind of public resource frequency reducing method and device |
| CN108886548A (en) * | 2017-02-24 | 2018-11-23 | 华为技术有限公司 | A kind of method, electronic equipment and the storage medium of the device power consumption of determining electronic equipment |
| CN109710482A (en) * | 2018-11-20 | 2019-05-03 | 广东优世联合控股集团股份有限公司 | A kind of electronic component performance detection method, device, readable medium and electronic equipment |
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