CN111026239B - Server and method for controlling CPU - Google Patents
Server and method for controlling CPU Download PDFInfo
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- CN111026239B CN111026239B CN201911049191.XA CN201911049191A CN111026239B CN 111026239 B CN111026239 B CN 111026239B CN 201911049191 A CN201911049191 A CN 201911049191A CN 111026239 B CN111026239 B CN 111026239B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/16—Constructional details or arrangements
- G06F1/18—Packaging or power distribution
- G06F1/183—Internal mounting support structures, e.g. for printed circuit boards, internal connecting means
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
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Abstract
The embodiment of the invention discloses a server and a method for controlling a CPU. The server includes a plurality of processors, a platform controller hub, a programmable logic circuit, and an IO extender. The IO expander outputs a CPU on-line request when receiving the CPU on-line request; when the platform controller center polls the CPU on-line request, the CPU on-line command and the CPU hot reset command are output in sequence; the programmable logic circuit brings the CPU specified by the offline, CPU on command and CPU hot reset command on line and hot reset. By the mode, the appointed CPU can be operated online to process the tasks of the server when the server is operated.
Description
Technical Field
The present invention relates to the field of servers, and in particular, to a server and a method for controlling a CPU.
Background
The multi-path server refers to a server having a physical number of Central Processing Units (CPUs) of 2 or more, and generally, CPUs in the multi-path server are divided into two paths, four paths, eight paths, and the like. A plurality of CPUs in the multi-path server work cooperatively, so that powerful computing capability can be provided. The CPUs are mutually coordinated and dependent and do not work independently. When any one of the CPUs fails, the whole system is crashed and cannot work normally.
In the multi-server, the number and position of the CPUs are fixed at the time of assembly. Subsequently, if the number of used CPUs is to be increased or decreased, the configuration must be modified after the multi-way server is shut down. Shutdown maintenance means tedious field manual operation, and the machine is set off, the case is opened, the CPU is assembled, and finally, recovery is carried out.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides a server and a method for controlling a CPU, which can enable a designated CPU to be run online to process a task of the server when the server is running.
In order to achieve the object of the present invention, an embodiment of the present invention provides a server, including: the platform controller comprises a platform controller center PCH, a programmable logic circuit, a plurality of Central Processing Units (CPUs) and an input/output (IO) expander, wherein the PCH is connected with the IO expander, the IO expander is connected with the programmable logic circuit, and the programmable logic circuit is connected with the CPUs;
the IO expander is used for outputting a CPU on-line request when receiving the CPU on-line request; when a CPU on-line command sent by the PCH is received, the CPU on-line command is sent to the programmable logic circuit; when a CPU hot reset command sent by the PCH is received, sending the hot reset command to the programmable logic circuit;
the PCH is used for sending a CPU (central processing unit) online command to the IO expander when polling a CPU online request output by the IO expander; after determining that the specified CPU is on line and checking a super channel interconnection (UPI) topology, setting a UPI route and setting a CPU related register specified by the CPU on-line command, sending a hot reset command to the IO expander; when the specified CPU is determined to be reset, distributing a firmware agent, setting a route and programming an input/output (IO) register for the specified CPU, and sending a basic input/output system (BIOS) ready command;
the programmable logic circuit is used for carrying out on-line on the CPU specified by the CPU on-line command when the CPU on-line command is received from the IO expander; when a hot reset command is received from the IO extender, a hot reset is performed on the designated CPU.
In an alternative embodiment, the CPU on-line request is sent by the baseboard management controller BMC of the server when the load of the running CPU exceeds a threshold.
In an alternative embodiment, the programmable logic circuitry is configured to:
when a CPU on-line command is received from the IO expander, determining that a CPU specified by the CPU on-line command is in place and is in a standby state;
pulling up a power-on signal of a specified CPU for a first delay;
and when the first delay expires, pulling up a reset signal of the designated CPU and a reset signal of a device downstream of the designated CPU.
In an alternative embodiment, the programmable logic circuitry is configured to:
when a hot reset command is received from the IO expander, determining that the specified CPU is currently in place and on line;
pulling down a reset signal of the appointed CPU and a reset signal of downstream equipment of the appointed CPU by a second delay;
and pulling up the reset signal of the designated CPU and the reset signal of the downstream equipment when the second delay expires.
In order to achieve the purpose of the present invention, an embodiment of the present invention provides a method for controlling a CPU, which is applied to a server, where the server includes a platform controller center PCH, a programmable logic circuit, a plurality of central processing units CPUs, and an input/output IO expander, where the PCH is connected to the IO expander, the IO expander is connected to the programmable logic circuit, and the programmable logic circuit is connected to the plurality of CPUs; the method comprises the following steps:
the IO expander outputs a CPU on-line request when receiving the CPU on-line request;
when the PCH polls a CPU on-line request output by the IO expander, the PCH sends a CPU on-line command to the IO expander;
when receiving a CPU (central processing unit) on-line command sent by the PCH (physical channel), the IO expander sends the CPU on-line command to the programmable logic circuit;
when the programmable logic circuit receives a CPU (central processing unit) online command from the IO expander, the CPU specified by the CPU online command is online;
the PCH sends a hot reset command to the IO expander after determining that the specified CPU is on line and checking a super channel interconnection (UPI) topology, setting a UPI route and setting a CPU related register specified by the CPU on-line command;
when receiving a CPU hot reset command sent by the PCH, the IO expander sends the hot reset command to the programmable logic circuit;
the programmable logic circuit carries out hot reset on the appointed CPU according to a hot reset command received from the IO expander;
the PCH, upon determining that the designated CPU has been reset hot, allocates a firmware agent, sets a route, programs an input output IO register for the designated CPU, and sends a BIOS ready command.
In an alternative embodiment, the CPU on-line request is sent by the baseboard management controller BMC of the server when the load of the running CPU exceeds a threshold.
In an alternative embodiment, the step of the programmable logic circuit, when receiving the CPU on-line command from the IO extender, bringing the CPU specified by the CPU on-line command on-line includes:
determining that the CPU specified by the CPU on-line command is in place and in a standby state;
pulling up a power-on signal of a specified CPU for a first delay;
and when the first delay expires, pulling up a reset signal of the designated CPU and a reset signal of a device downstream of the designated CPU.
In an alternative embodiment, the step of the programmable logic circuit performing a hot reset on the designated CPU upon receiving a hot reset command from the IO extender comprises:
when the programmable logic circuit receives a hot reset command from the IO expander, determining that the specified CPU is currently in place and on line;
the programmable logic circuit pulls down a reset signal of the appointed CPU and a reset signal of downstream equipment of the appointed CPU by a second delay;
at the expiration of the second delay, the programmable logic pulls high the reset signal of the designated CPU and the reset signal of the downstream device.
By the method, when the IO expander receives a CPU on-line request, the PCH can be requested to enable the CPU to be on-line; the PCH sends a CPU (central processing unit) online command and a CPU hot reset command in sequence, so that the programmable logic circuit controls the specified CPU to perform online and hot reset in sequence, and the specified CPU can run online to process the tasks of the server when the server runs.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention.
Fig. 1 is a schematic structural diagram of a server according to an embodiment of the present invention;
fig. 2 is a flowchart of a method for controlling a CPU according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.
The steps illustrated in the flow charts of the figures may be performed in a computer system such as a set of computer-executable instructions. Also, while a logical order is shown in the flow diagrams, in some cases, the steps shown or described may be performed in an order different than here.
The multi-path server refers to a server having a physical number of Central Processing Units (CPUs) of 2 or more, and generally, CPUs in the multi-path server are divided into two paths, four paths, eight paths, and the like. A plurality of CPUs in the multi-path server work cooperatively, so that powerful computing capability can be provided. The CPUs are mutually coordinated and dependent and do not work independently. When any one of the CPUs fails, the whole system is crashed and cannot work normally.
In the multi-server, the number and position of the CPUs are fixed at the time of assembly. Subsequently, if the number of used CPUs is to be increased or decreased, the configuration must be modified after the multi-way server is shut down. Shutdown maintenance means tedious field manual operation, and the machine is set off, the case is opened, the CPU is assembled, and finally, recovery is carried out.
In order to solve the above technical problem, an embodiment of the present invention provides a server, as shown in fig. 1, where the server includes: a Platform Controller Hub (PCH) 100, a programmable logic circuit 200, a plurality of Central Processing Units (CPUs) 300 (including CPUs 1310, 2320 and 3330), and an IO extender (Input/Output extender) 400, wherein the PCH100 is connected to the IO extender 400, the IO extender 400 is connected to the programmable logic circuit 200, and the programmable logic circuit 200 is connected to the plurality of CPUs;
after the server is powered on and enters the system, the IO expander 400 is configured to output a CPU online request through a port (SDA/SCL) of the IO expander when receiving the CPU online request; when a CPU on-line command sent by the PCH100 is received, the CPU on-line command is sent to the programmable logic circuit 200 through the IO port thereof; upon receiving a CPU hot reset command sent by PCH100, the hot reset command is sent to programmable logic circuit 200 through its IO port. IO extender 400 may be a Texas instruments Serial to parallel conversion IO extender model No. PCA 9555.
The PCH100 is configured to send a CPU on-line command to the IO extender 400 when polling a CPU on-line request output by the IO extender 400; after determining that the specified CPU is on-line and checking the super channel interconnect UPI topology, setting the UPI route, and setting the CPU-related register specified by the CPU on-line command, a warm reset command is sent to the IO extender 400; when the specified CPU is determined to be reset, distributing a firmware agent, setting a route and programming an input/output (IO) register for the specified CPU, and sending a basic input/output system (BIOS) ready command; since the number of pins of a General-Purpose Input/Output (GPIO) of the PCH100 is very limited, the GPIO pins of the PCH100 can be saved by using an IO extender (for example, the aforementioned IO extender with the model of PCA 9555), and in addition, the IO extender can be used as a center for signal exchange, which facilitates uniform connection and management of signals of the programmable logic circuit 200 and signals of the PCH100 (i.e., signals of the BIOS).
The programmable logic circuit 200 is configured to, when receiving a CPU on-line command from the IO extender 400, bring on-line the CPU specified by the CPU on-line command; upon receiving a warm reset command from IO extender 400, the designated CPU is subjected to a warm reset. In an alternative embodiment, the Programmable Logic circuit 200 may be a Complex Programmable Logic Device (CPLD).
By the above manner, when the IO extender 400 receives a CPU on-line request, the PCH100 is requested to make the CPU on-line; the PCH100 successively sends a CPU on-line command and a CPU hot reset command, so that the programmable logic circuit 200 successively controls the specified CPU to perform on-line and hot reset, so that the specified CPU can run to process the tasks of the server.
In an alternative embodiment, the CPU on-line request is sent by a Baseboard Management Controller (BMC) of the server shown in fig. 1 when the load of the running CPU exceeds a threshold. When the load of the CPU exceeds the preset load threshold value, the BMC sends the CPU on-line request to the programmable logic circuit, the programmable logic circuit 200 forwards the CPU on-line request to the IO extender 400, and the IO extender 400 sends the CPU on-line request to the PCH.
In an alternative embodiment, programmable logic circuit 200 is configured to:
when a CPU on-line command is received from the IO extender 400, it is determined that the CPU specified by the CPU on-line command is on bit and is in a standby state, and the specified CPU feeds back a bit signal (such as CPU1_ sktocc _ n, CPU2_ sktocc _ n, and CPU3_ sktocc _ n in fig. 1);
pulling up a power-on signal (CPU 1_ PWRGD, CPU2_ PWRGD, and CPU3_ PWRGD shown in FIG. 1) of the designated CPU by a first delay; the power-on signal is pulled up by a first delay time, so that the power-on signal is at a high level during the first delay time and is used for meeting the requirement of bottom hardware inside the CPU, and a BIOS system of the server learns that the specified CPU is powered on; the first delay may be 34 milliseconds;
at the expiration of the first delay, the RESET signals designating the CPU (CPU 1_ RESET _ N, CPU2_ RESET _ N and CPU3_ RESET _ N in fig. 1) and the RESET signals designating the devices downstream of the CPU are pulled high. The CPU downstream device may be a device (e.g., a network card, RAID (Redundant Arrays of Independent Drives, disk array)) reset signal pull-up from the CPU connected over the PCIe bus for restoring the designated CPU to an initial state. When the CPU is controlled to be on line, the downstream equipment of the CPU also needs to be correspondingly controlled to normally work. And the PCH determines that the CPU is on line when detecting that the level of a reset signal of the downstream equipment of the CPU is pulled high.
Through the operation process, the BIOS system of the server can know that the specified CPU is in the on-line state.
In an alternative embodiment, programmable logic circuit 200 is configured to:
when a hot reset command is received from the IO expander, determining that the specified CPU is currently in place and on line;
pulling down a reset signal of the appointed CPU and a reset signal of downstream equipment of the CPU by a second delay; pulling down the reset signal by a second delay time, and keeping the reset signal at a low level in the time of the second delay time so as to meet the requirement of bottom layer hardware inside the CPU and enable the BIOS to know that the CPU is reset; the second delay may be 31 milliseconds;
and pulling up the reset signal of the designated CPU and the reset signal of the downstream equipment when the second delay expires. The PCH determines that the designated CPU has been reset hot after detecting that the reset signal of the CPU downstream device is pulled high.
Through the process, the reset signal of the designated CPU is released, and the BIOS system of the server can normally work after the reset signal is released.
In order to solve the technical problem, a method for controlling a CPU is applied to a server, the server comprises a platform controller center PCH, a programmable logic circuit, a plurality of central processing units CPU and an input/output IO expander, wherein the PCH is connected with the IO expander, the IO expander is connected with the programmable logic circuit, and the programmable logic circuit is connected with the plurality of CPUs; as shown in fig. 2, the method includes:
s101, when receiving a CPU on-line request, an IO expander outputs the CPU on-line request;
step S102, when the PCH polls a CPU on-line request output by the IO expander, the PCH sends a CPU on-line command to the IO expander;
step S103, when receiving a CPU on-line command sent by the PCH, the IO expander sends the CPU on-line command to the programmable logic circuit;
step S104, when the programmable logic circuit receives a CPU on-line command from the IO expander, the CPU specified by the CPU on-line command is on-line;
step S105, after determining that the specified CPU is on line, checking the super channel interconnection (UPI) topology, setting a UPI route and setting a CPU related register specified by the CPU on-line command, the PCH sends a hot reset command to the IO expander;
step S106, when receiving a CPU hot reset command sent by the PCH, the IO expander sends the hot reset command to the programmable logic circuit;
step S107, the programmable logic circuit carries out hot reset on the appointed CPU according to the hot reset command received from the IO expander;
in step S108, when the PCH determines that the designated CPU is reset, it allocates a firmware agent, sets a routing, programs an IO register, and sends a BIOS ready command.
In an alternative embodiment, the CPU on-line request is sent by the baseboard management controller BMC of the server when the load of the running CPU exceeds a threshold.
In an alternative embodiment, step S104 includes:
determining that the CPU specified by the CPU on-line command is in place and in a standby state;
pulling up a power-on signal of a specified CPU for a first delay;
and when the first delay expires, pulling up a reset signal of the designated CPU and a reset signal of a device downstream of the designated CPU.
In an alternative embodiment, step S107 comprises:
when the programmable logic circuit receives a hot reset command from the IO expander, determining that the specified CPU is currently in place and on line;
the programmable logic circuit pulls down a reset signal of the appointed CPU and a reset signal of downstream equipment of the appointed CPU by a second delay;
at the expiration of the second delay, the programmable logic pulls high the reset signal of the designated CPU and the reset signal of the downstream device.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (8)
1. A server, comprising: the platform controller comprises a platform controller center PCH, a programmable logic circuit, a plurality of Central Processing Units (CPUs) and an input/output (IO) expander, wherein the PCH is connected with the IO expander, the IO expander is connected with the programmable logic circuit, and the programmable logic circuit is connected with the CPUs;
the IO expander is used for outputting a CPU on-line request when receiving the CPU on-line request; when a CPU on-line command sent by the PCH is received, sending the CPU on-line command to the programmable logic circuit; when a CPU hot reset command sent by the PCH is received, sending a hot reset command to the programmable logic circuit;
the PCH is used for sending a CPU (central processing unit) online command to the IO expander when a CPU online request output by the IO expander is polled; after determining that a specified CPU is on line and checking a super channel interconnection (UPI) topology, setting a UPI route and setting a CPU related register specified by the CPU on-line command, sending a hot reset command to the IO expander; when the specified CPU is determined to be reset in a hot mode, distributing a firmware agent, setting a route and programming an input/output (IO) register for the specified CPU, and sending a basic input/output system (BIOS) ready command;
the programmable logic circuit is used for carrying out on-line on the CPU specified by the CPU on-line command when the CPU on-line command is received from the IO expander; and when the thermal reset command is received from the IO expander, performing thermal reset on the specified CPU.
2. The server of claim 1, wherein the CPU on-line request is sent by a Baseboard Management Controller (BMC) of the server when a load of a running CPU exceeds a threshold.
3. The server of claim 1, wherein the programmable logic circuitry is to:
when the CPU on-line command is received from the IO expander, determining that the CPU specified by the CPU on-line command is in place and is in a standby state;
pulling up a power-on signal of the appointed CPU for a first delay;
and when the first delay expires, pulling up the reset signal of the specified CPU and the reset signal of the equipment downstream of the specified CPU.
4. The server of claim 1, wherein the programmable logic circuitry is to:
determining that the designated CPU is currently on-bit and on-line when a hot reset command is received from the IO extender;
pulling down a reset signal of the appointed CPU and a reset signal of downstream equipment of the appointed CPU by a second delay;
and when the second delay expires, pulling up a reset signal of the appointed CPU and a reset signal of the downstream equipment.
5. A method for controlling a CPU is applied to a server, and the server comprises a platform controller center PCH, a programmable logic circuit, a plurality of Central Processing Units (CPUs) and an input/output (IO) expander, wherein the PCH is connected with the IO expander, the IO expander is connected with the programmable logic circuit, and the programmable logic circuit is connected with the CPUs; characterized in that the method comprises:
the IO expander outputs a CPU on-line request when receiving the CPU on-line request;
when the PCH polls a CPU on-line request output by the IO expander, the PCH sends a CPU on-line command to the IO expander;
when receiving the CPU on-line command sent by the PCH, the IO expander sends the CPU on-line command to the programmable logic circuit;
when the programmable logic circuit receives the CPU on-line command from the IO expander, the CPU specified by the CPU on-line command is on-line;
after determining that the specified CPU is on line and checking a super channel interconnection (UPI) topology, setting a UPI route and setting a CPU related register specified by the CPU on-line command, the PCH sends a hot reset command to the IO expander;
when receiving a CPU hot reset command sent by the PCH, the IO expander sends a hot reset command to the programmable logic circuit;
the programmable logic circuit carries out hot reset on the appointed CPU according to a hot reset command received from the IO expander;
when the PCH determines that the specified CPU is reset in a hot state, the PCH allocates a firmware agent, sets a route, programs an input/output (IO) register for the specified CPU, and sends a basic input/output system (BIOS) ready command.
6. The method of claim 5, wherein the CPU on-line request is sent by a Baseboard Management Controller (BMC) of the server when a load of a running CPU exceeds a threshold.
7. The method of claim 5, wherein the step of the programmable logic circuit bringing on the CPU specified by the CPU on-line command when receiving the CPU on-line command from the IO extender comprises:
determining that the CPU specified by the CPU on-line command is in place and in a standby state;
pulling up a power-on signal of the appointed CPU for a first delay;
and when the first delay expires, pulling up the reset signal of the specified CPU and the reset signal of the equipment downstream of the specified CPU.
8. The method of claim 5, wherein the step of the programmable logic circuit, upon receiving a warm reset command from the IO extender, warm resetting the designated CPU comprises:
when the programmable logic circuit receives a hot reset command from an IO expander, determining that the specified CPU is currently in place and on line;
the programmable logic circuit pulls down a reset signal of the appointed CPU and a reset signal of downstream equipment of the appointed CPU by a second delay;
and when the second delay expires, the programmable logic circuit pulls up a reset signal of the specified CPU and a reset signal of the downstream equipment.
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| CN101510081A (en) * | 2009-03-31 | 2009-08-19 | 浙江中控技术股份有限公司 | Redundant switch control circuit and method |
| JP2016133877A (en) * | 2015-01-16 | 2016-07-25 | ファナック株式会社 | Numerical control system with internal-register self-reset function by serial communication signal monitoring |
| CN107291653A (en) * | 2016-03-31 | 2017-10-24 | 华为技术有限公司 | A kind of multicomputer system and the method for configuring multicomputer system |
| US10482562B2 (en) * | 2017-04-21 | 2019-11-19 | Intel Corporation | Graphics engine partitioning mechanism |
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