CN111008045B - Automatic loading method for off-chip flash high-capacity program - Google Patents
Automatic loading method for off-chip flash high-capacity program Download PDFInfo
- Publication number
- CN111008045B CN111008045B CN201911111829.8A CN201911111829A CN111008045B CN 111008045 B CN111008045 B CN 111008045B CN 201911111829 A CN201911111829 A CN 201911111829A CN 111008045 B CN111008045 B CN 111008045B
- Authority
- CN
- China
- Prior art keywords
- program
- file
- main program
- flash
- binary
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44521—Dynamic linking or loading; Link editing at or after load time, e.g. Java class loading
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/781—On-chip cache; Off-chip memory
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computing Systems (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Stored Programmes (AREA)
Abstract
The invention provides an off-chip FLASH high-capacity program automatic loading method, which comprises the steps of converting a main program software file into a binary storage file, storing the binary main program file in a designated address of FLASH, acquiring an interrupt vector table of a main program interrupt system from the binary main program file, compressing a bootstrap program and a logic program through an instruction to generate a compressed version programming file, programming the compressed version programming file into off-chip FLASH, reading a bootstrap program target program segment from the FLASH to run, moving the main program into a DDR to run by the bootstrap program, moving the interrupt vector table into a BRAM, printing moving completion information by a serial port and guiding the program to run. The invention realizes large-capacity program loading without using a third-party chip and modifying a system architecture, solves the problem of insufficient storage resources, and can complete the function of loading large off-chip storage programs, thereby greatly reducing the system cost.
Description
Technical Field
The invention relates to the technical field of FPGA chips, in particular to an off-chip flash loading method which can improve the convenience of a system and reduce the hardware cost.
Background
Generally, embedded products are based on specific microprocessor architectures, such as x86, powerPC, MIPS, ARM, etc., and processor architectures with the same characteristics constitute a colorful computing control platform, but no matter what type of processor platform, the design and implementation process of the bootstrap program is an essential link for embedded systems. The boot program is typically burned into an external non-volatile memory, such as a Flash chip. The boot program for a specific embedded device is too large and the boot program of the embedded device is limited by the size of the memory chip. This requires the design of a specific boot program for a specific hardware platform. The boot program is software based on a hardware platform, so that the boot program has the functions of initializing the hardware platform and booting an operating system, because the operating system of the embedded system runs in a RAM with a high speed, and the RAM has the characteristic of losing data when power is off. This requires that the operating system kernel or a large amount of programs be uploaded from ROM, flash or via a network to RAM, which is the basic function to be performed by the boot program. The boot program is used as initialization software highly related to a hardware platform, and depends on the architecture of a processor and the configuration of an embedded system board-level device. For example, the size and location of Flash in the whole system, the communication mode of the host, and the size and location of the RAM are configured differently according to the characteristics of the specific development board. Therefore, it is almost impossible to build a generic bootstrap program for all embedded systems, with different processor architectures having different programs.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides an automatic loading method of an off-chip flash high-capacity program.
The technical scheme adopted by the invention for solving the technical problem comprises the following steps:
step 1, converting a main program software file into a binary system storage file through an instruction, and storing the binary system main program file in a FLASH designated address;
step 2, obtaining an interrupt vector table of a main program interrupt system in a binary main program file, and starting an address space of a program segment from 0x00 to 0x 50;
step 3, compressing the bootstrap program and the logic program through the instruction to generate a compressed version programming file, and programming the file into an off-chip FLASH through an iMPACT software tool;
and 4, after the system is powered on, a soft core CPU in the FPGA reads a bootstrap program target program segment from the FLASH to run, the bootstrap program moves the main program to the DDR to run, an interrupt vector table is moved to a BRAM starting address from 0x00 to 0x50, the serial port prints the movement completion information, and the bootstrap program guides the main program to run.
In the step 2, the first 64 bytes in the binary file of the main program are obtained and used as an interrupt vector table of the main program, and the binary file is moved to a soft core CPU BRAM to assist the main program to complete an interrupt function.
In step 4, the interrupt vector table is moved to the BRAM start address of 0x00 to 0x50, and the main program in the flash is moved to the area of the DDR3 start address bit 0x 500000000.
The invention has the beneficial effect that under the condition of not using a third-party chip and not modifying a system architecture, the high-capacity program loading is realized. The method can solve the problem of insufficient storage resources, and can complete the function of loading large storage programs outside the chip, thereby greatly reducing the system cost.
Drawings
FIG. 1 is a diagram of a hardware architecture according to the present invention.
FIG. 2 is a flow chart of a method for automatically loading a high-capacity program.
Fig. 3 is a flowchart of the guiding process.
Detailed Description
The invention is further illustrated with reference to the following figures and examples.
Step 1, converting the main program software file into a binary storage file through an instruction, and storing the binary main program file in a specified address of the FLASH.
Step 2, obtaining an interrupt vector table (an address space of 0x 00-0 x50 of an initial program segment) of a main program interrupt system in a binary main program file;
and 3, compressing the bootstrap program and the logic program through the instruction to generate a compressed version programming file, and programming the file into the off-chip FLASH through an iMPACT software tool.
And 4, after the system is powered on, a soft core CPU in the FPGA reads a bootstrap program target program segment from the FLASH to run, the bootstrap program moves the main program to the DDR to run, an interrupt vector table is moved to a BRAM starting address from 0x00 to 0x50, the serial port prints the movement completion information, and the bootstrap program guides the main program to run.
In the step 3, in an ISE Design Suite Command Prompt tool, the high-capacity main program and elf file are compressed and converted into a binary file through mb-obj copy-organization-r.vectors.
In the step 2, the first 64 bytes in the binary file of the main program are obtained and used as an interrupt vector table of the main program, and the binary file is moved to a soft core CPU BRAM to assist the main program to complete an interrupt function.
In step 4, the interrupt vector table is moved to the BRAM start address of 0x00 to 0x40, and the main program in the flash is moved to the area of the DDR3 start address bit 0x 500000000.
An automatic loading method for off-chip flash large-capacity program relates to four programs, which are respectively a main program, an elf file, a logic program, a bit file, a bootstrap program, an elf file and a programming program, an mcs file (the logic program, the bit file, the bootstrap program and the elf file are generated by combination). The system comprises three memories, namely a FLASH memory and a programming program, wherein the FLASH memories are used for storing a main program and the programming program; the DDR3 memory is used for operating the bootstrap program firstly and then operating the main program; the BRAM memory is used for storing an interrupt vector table, and is shown in detail in fig. 1, and the specific implementation flow is shown in fig. 2.
And converting the bootstrap program in a debug folder under the SDK software path of the project. Namely, opening ISE Design Suite Command Prompt tool, and inputting a Command: mb-obj-operand-r.vector-reset-r.vector-sw _ exception-r.vector-interrupt-r.vector-hw _ exception NUC _ test
Elf is a main program file, and NUC _ testbin.b is a main program binary file.
Then, the NUC _ TESTbin.b file is burnt into the area of the flash start address bit 0x90020000, and the first 64 bytes in the binary file of the main program are obtained as the interrupt vector table of the main program.
The flow chart of the bootstrap process is shown in fig. 3, and the bootstrap process mainly has three functions:
(1) Moving an interrupt vector table (address space of a starting program segment 0x 00-0 x 40) of a main program interrupt system to a BRAM starting address 0x00 area;
(2) Moving the main program in the flash to the DDR3 memory initial address bit 0x500000000 for operation;
(3) Printing program running state information;
(4) And guiding the main program to run.
The bit file generates a programming file and an MCS format file through an SDK tool. And programming the MCS file into Flash through an iMPACT software tool.
Claims (3)
1. An automatic loading method for an off-chip flash high-capacity program is characterized by comprising the following steps:
step 1, converting a main program software file into a binary system storage file through an instruction, and storing the binary system main program file in a FLASH designated address;
step 2, obtaining an interrupt vector table of a main program interrupt system in a binary main program file, and starting an address space of a program segment from 0x00 to 0x 50;
step 3, compressing the bootstrap program and the logic program through an instruction to generate a compressed version programming file, and programming the file into an off-chip FLASH through an iMPACT software tool;
and 4, after the system is powered on, a soft core CPU in the FPGA reads a target program segment of the bootstrap program from the FLASH to run, the bootstrap program moves the main program to the DDR to run, the interrupt vector table is moved to the BRAM starting address from 0x00 to 0x50, the serial port prints the movement completion information, and the bootstrap program guides the main program to run.
2. The method for automatically loading the off-chip flash high-capacity program according to claim 1, characterized in that:
in the step 2, the first 64 bytes in the binary file of the main program are obtained and used as an interrupt vector table of the main program, and the binary file is moved to a soft core CPU BRAM to assist the main program to complete an interrupt function.
3. The method for automatically loading the off-chip flash high-capacity program according to claim 1, characterized in that:
in step 4, the interrupt vector table is moved to the BRAM start address of 0x00 to 0x50, and the main program in the flash is moved to the area of the DDR3 start address bit 0x 500000000.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911111829.8A CN111008045B (en) | 2019-11-14 | 2019-11-14 | Automatic loading method for off-chip flash high-capacity program |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911111829.8A CN111008045B (en) | 2019-11-14 | 2019-11-14 | Automatic loading method for off-chip flash high-capacity program |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111008045A CN111008045A (en) | 2020-04-14 |
| CN111008045B true CN111008045B (en) | 2023-03-21 |
Family
ID=70112025
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911111829.8A Active CN111008045B (en) | 2019-11-14 | 2019-11-14 | Automatic loading method for off-chip flash high-capacity program |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111008045B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11734018B2 (en) * | 2020-07-17 | 2023-08-22 | Western Digital Technologies, Inc. | Parallel boot execution of memory devices |
| CN114816581B (en) * | 2022-05-20 | 2023-06-02 | 中国电子科技集团公司第三十研究所 | ARM processor-based non-operating system algorithm dynamic loading method |
| CN115543467A (en) * | 2022-11-30 | 2022-12-30 | 天津聚芯光禾科技有限公司 | Method for accelerating starting speed of switch |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4404625B2 (en) * | 2003-12-25 | 2010-01-27 | パナソニック株式会社 | Information processing apparatus and ROM image generation apparatus for the apparatus |
| CN104035776B (en) * | 2014-06-23 | 2017-05-17 | 成都万维图新信息技术有限公司 | Operating system starting method |
| CN104572206A (en) * | 2015-01-14 | 2015-04-29 | 厦门为那通信科技有限公司 | Application program self updating and backup recovery method |
| CN109213531A (en) * | 2018-09-01 | 2019-01-15 | 哈尔滨工程大学 | A kind of multi-core DSP based on EMIF16 powers on the simplification implementation method of self-starting |
-
2019
- 2019-11-14 CN CN201911111829.8A patent/CN111008045B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN111008045A (en) | 2020-04-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111008045B (en) | Automatic loading method for off-chip flash high-capacity program | |
| US7082525B2 (en) | Booting from non-linear memory | |
| CN104951334B (en) | FPGA biplate QSPI flash program loading method | |
| US9836417B2 (en) | Bridge configuration in computing devices | |
| US6798713B1 (en) | Implementing software breakpoints | |
| CN103677885A (en) | ARM FLASH simple program programming method | |
| CN111857776A (en) | Online upgrading method for application programs of DSP (digital Signal processor) board cards | |
| US7793004B2 (en) | Computer peripheral device implemented as optic storage device or/and removable disk by software emulation and implementing method thereof | |
| CN104133705A (en) | System and method for loading PowerPC system guide file through serial port | |
| CN108804228A (en) | A kind of implementation method of DSP program space extensions | |
| US8595594B2 (en) | Data processing method, memory controller, and memory storage device | |
| US7574585B1 (en) | Implementing software breakpoints and debugger therefor | |
| US20080155309A1 (en) | Memory card and debugging method employed by the same | |
| CN109426511B (en) | Soft core updating method and system | |
| CN102629212A (en) | Method for indirectly programming to NANDFLASH based on J-LINK | |
| CN114816273B (en) | Norflash-oriented adaptive optimal configuration method, device and medium | |
| CN113946481B (en) | RISC-V kernel MCU debugging downloading program method and debugger | |
| CN111666105A (en) | Program storage and guide system and method based on DSP and FPGA | |
| CN112799683A (en) | Terminal device program programming and testing method | |
| CN116302122A (en) | Multi-core heterogeneous domain controller, peripheral adaptation method and storage medium | |
| CN110502439B (en) | Debugging method, device, electronic equipment and storage medium | |
| US8117427B2 (en) | Motherboard, storage device and controller thereof, and booting method | |
| CN114528141A (en) | Method and device for repairing program defects in embedded system kernel mode | |
| CN100470681C (en) | Method for implementing user program booting based on NAND flash memory | |
| CN114281632A (en) | Method and device for initializing Romcode in SoC verification |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |