CN111003682A

CN111003682A - Electronic package and manufacturing method thereof

Info

Publication number: CN111003682A
Application number: CN201811169829.9A
Authority: CN
Inventors: 许凯翔
Original assignee: Phoenix and Corp
Current assignee: Phoenix Pioneer Technology Co Ltd
Priority date: 2018-10-08
Filing date: 2018-10-08
Publication date: 2020-04-14

Abstract

An electronic package and its preparation method, including forming the circuit layer on a bearing base plate taking the form of light transmission first, carry on the operation of laminating and sealing of the electronic component with the seal and conductive element, then carry on operations such as packaging layer, conductive structure and circuit structure, etc., so the invention does not need to add and protect the electronic component and provide the chip to actuate the space in the subsequent process like the traditional cover part (cap) structure additionally, so can reduce the cost of manufacture and raise the production efficiency, and can reduce the whole thickness of the electronic package.

Description

Electronic package and manufacturing method thereof

Technical Field

The present invention relates to electronic package structures, and more particularly to an electronic package suitable for sensing signals.

Background

With the development of electronic industry, the electronic products using sensor devices or camera lenses tend to be designed in the direction of light, thin, small, and diversified functions, and the semiconductor packaging technology develops different packaging forms accordingly.

Currently, many sensing chips, such as leds (light emitting diodes), MEMS (Micro-electro-mechanical Systems), and CMOS (Complementary Metal-Oxide-Semiconductor), require a cavity space for actuation or protection, and are packaged by soldering gold/copper wires or flip chip (flip chip) on a carrier substrate. The general process steps are as follows: firstly, the chip is arranged on the bearing substrate or in the groove of the bearing substrate, and the mode of covering a chip or dispensing and attaching the chip is adopted. Then, the bonding gold wire is used to electrically connect the chip and the carrier substrate (this step is omitted in flip chip manner), especially for MEMS type chip, which requires a space for operation, the chip is usually connected to the carrier substrate by using the bonding gold wire. Then, a cover (cap) is covered on the chip to protect the chip and provide a chip actuating space, or a transparent glue body is formed to protect the chip, wherein most of the LED type chip is protected by the transparent glue body, and the MEMS type chip is protected by the cover and provides a chip actuating space.

Fig. 1A is a schematic cross-sectional view of a conventional sensing package 1A. As shown in fig. 1A, the sensing package 1A includes: a package substrate 10a, a MEMS type sensing chip 14, a lid 19 a. The package substrate 10a includes a circuit layer 11. The sensing chip 14 is bonded to the upper side of the package substrate 10a by a glue material, and is electrically connected to the package substrate 10a by a plurality of gold wires 140. The lid 19a is mounted on the package substrate 10a by supporting legs 190 and covers the sensing chip 14.

However, in the conventional sensing package 1a, the soldering of the gold wire 140 has the following disadvantages:

firstly, after the sensing chip 14 is bonded, a cap 19a for protection is added on the sensing chip 14 in a pick and place (pick and place) manner, and when the pick and place manner is used in a mass production process, the cap 19a needs to be loaded one by one, that is, only one cap 19a can be arranged on the packaging substrate 10a in one mounting step, so that the mass production process is long in time, the production cost is greatly increased, and the production efficiency is very poor.

Secondly, the gold wire 140 is soldered on the sensing chip 14, which not only has a slow process speed, but also is prone to oxidation or contamination of the circuit layer 11 of the package substrate 10a due to long waiting time during large-area operation.

Third, other chips, such as an Application-specific integrated circuit (ASIC) functional chip, are added to the MEMS type sensing package 1a for modularization, so that the area occupied by the gold wires 140 cannot be reduced, and the area of the board surface of the package substrate 10a must be increased, which results in that the overall area and package volume of the final electronic product cannot be effectively reduced.

In order to solve the above problems, a Through Silicon Via (TSV) technique using a semiconductor substrate is used for packaging.

As shown in fig. 1B, the manufacturing method of the conventional sensing package 1B first manufactures a full-surface lid 19B by etching a wafer or glass, then assembles a full-surface MEMS type sensing chip 14 onto the full-surface lid 19B by wafer bonding (wafer bonding), and then performs singulation (as shown in the figure, the singulation path L) to obtain a plurality of sensing packages 1B, wherein the sensing chip 14 needs to manufacture a conductive Through Silicon Via (TSV) 100B by a TSV (Through Silicon Via) process to be used as an electrical contact (I/O). Accordingly, the entire thickness of the sensing package 1b can be reduced without performing a wire bonding process.

However, in the conventional sensing package 1b, the manufacturing cost is greatly increased due to the high cost, high integration difficulty, high technical difficulty and long process for manufacturing the conductive through silicon via 100 b.

Alternatively, as compared to the process of fig. 1A, a substrate with a recess may be used for packaging, as shown in fig. 1C. Specifically, the manufacturing method of the conventional sensing package 1c first attaches the sensing chip 14 to the groove structure 100 of a package substrate 10c through an adhesive material, electrically connects the package substrate 10c and the sensing chip 14 through a plurality of gold wires 140, and covers the package substrate 10c with a cover member 19c made of glass or other materials to cover the groove structure 100 for protecting the cavity.

However, the manufacturing time and cost of the package substrate 10c are long due to the need to fabricate the groove structure 100.

In addition, after the sensing chip 14 is bonded, the lid 19c is added on the sensing chip 14 by a pick and place (pick and place) method, which is required to perform the loading operation of the lid 19c one by one during the mass production process, i.e. only one lid 19c can be installed on the package substrate 10c in one mounting step, so that the mass production process is long in time, the production cost is greatly increased, and the production efficiency is very poor.

Alternatively, as compared to the process shown in fig. 1A, a Package on Package (PoP) method may be adopted, as shown in fig. 1D. Specifically, the manufacturing method of the conventional sensing package 1d first arranges the sensing chip 14 on the package substrate 10a in a flip chip (flip chip) manner through a plurality of conductive bumps 141, seals the conductive bumps 141 with an underfill material 17 such as glass paste, and then superimposes another package substrate 10d on the package substrate 10a through a plurality of solder balls 15 to form a cavity to protect the sensing chip 14.

However, in the conventional sensing package 1d, since two mounting operations (i.e., the mounting of the sensing chip 14 and the other package substrate 10d) are required, the process is tedious, and only the solder balls 15 are used to surround the periphery of the sensing chip 14, the product sealing performance is poor, and the height of the solder balls 15 after reflow is easily changed, so that the thickness of the sensing package 1d is difficult to be precisely controlled.

Therefore, how to overcome the above problems of the conventional technologies has become a problem to be overcome in the industry.

Disclosure of Invention

In view of the above-mentioned drawbacks of the conventional technologies, the present invention provides an electronic package and a method for fabricating the same, which can reduce the fabrication cost and improve the production efficiency.

The method for manufacturing the electronic packaging piece comprises the following steps: forming a circuit layer on a transparent bearing substrate; forming a sealing body on the bearing substrate and the circuit layer; arranging at least one electronic element with a sensing part on the sealing body, so that the electronic element, the sealing body, the circuit layer and the bearing substrate form a sealed cavity, and the sensing part and the bearing substrate are respectively positioned at two opposite sides of the sealed cavity; and forming a packaging layer on the bearing substrate to coat the electronic element and the sealing body.

The present invention also provides an electronic package comprising: a carrier substrate, which is transparent; a circuit layer disposed on the carrier substrate; the sealing body is arranged on the bearing substrate and the circuit layer; the electronic element is provided with a sensing part and is arranged on the sealing body, so that a sealing cavity is formed among the electronic element, the sealing body, the circuit layer and the bearing substrate, and the sensing part and the bearing substrate are respectively positioned at two opposite sides of the sealing cavity; and the packaging layer is formed on the bearing substrate to coat the electronic element and the sealing body.

In the electronic package and the manufacturing method thereof, the sealing body is a non-conductive body.

In an embodiment, the electronic component is disposed on the circuit layer through a conductive element, and the conductive element is located in the sealed cavity. For example, the conductive element includes a conductive pillar bonded to the circuit layer and a conductive layer disposed on the conductive pillar.

In the electronic package and the method for manufacturing the same, at least one conductive structure electrically connected to the circuit layer is formed in the package layer. For example, at least one circuit structure electrically connected to the conductive structure is formed on the package layer. Alternatively, the conductive structure is in the form of a conductive post or a conductive via.

In the electronic package and the method for manufacturing the same, the package layer is not formed in the sealed cavity.

In the electronic package and the method for manufacturing the same, a functional chip is disposed on the package layer.

In view of the above, the electronic package and the manufacturing method thereof of the present invention mainly form the circuit layer directly on the transparent carrier substrate, then perform the bonding and sealing operations of the electronic component with the sealing body and the conductive component, and then perform the operations of the package layer, the conductive structure, the circuit structure, etc., so the present invention has the following advantages:

first, the subsequent process does not need to use the traditional cover plate structure such as a glass plate or an iron shell, so the manufacturing cost can be reduced, the whole thickness of the electronic packaging part can be reduced, and the production efficiency can be effectively improved.

Secondly, a wire bonding process is not used, so that the packaging volume and the area of the electronic packaging piece are reduced.

Thirdly, a plurality of chips can be directly packaged on a bearing substrate to achieve the modularization effect and reduce the volume of subsequent electronic products.

Fourthly, the traditional conductive through silicon via is replaced by the conductive structure, so that the TSV process with high cost, high integration difficulty and high technical difficulty is not required, and the manufacturing cost can be effectively reduced.

Drawings

FIG. 1A is a cross-sectional view of a conventional sensing package;

FIG. 1B is a cross-sectional view of a conventional sensing package;

FIG. 1C is a cross-sectional view of a conventional sensing package;

FIG. 1D is a cross-sectional view of a conventional sensing package;

fig. 2A to 2F are schematic cross-sectional views illustrating a method for manufacturing an electronic package according to a first embodiment of the invention; wherein FIG. 2C' is a partial top view of FIG. 2C;

FIG. 2G is a subsequent application of FIG. 2F; and

fig. 3A to 3D are schematic cross-sectional views illustrating a method for manufacturing an electronic package according to a second embodiment of the invention.

Description of reference numerals:

1a, 1b, 1c,

1d sensing packages

10a, 10c, 10d package substrates

100 groove structure 100b conductive through-silicon-via

11. 21 line layer 14 sensing chip

140 gold wire 141, 280 conductive bump

15 solder ball 17 underfill

19a, 19b, 19c cover 190 support the foot

2. 3 electronic package 20 carrier substrate

21 wiring layer 21a conductive trace

210 electrical contact pad 211 external pad

22 encapsulant 23 conductive element

230 conductive post 231 conductive layer

24 active surface of electronic component 24a

24b non-active surface 240 electrode pad

25. 35 conductive structure 25a end face

26 encapsulation layer 26a first surface

26b second surface 260 is perforated

27. 37 circuit structure 28 function chip

L cutting path of A sensing part

S seals the cavity t gap.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and technical effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification.

It should be understood that the structures, ratios, sizes, and the like shown in the drawings of the present specification are only used for matching with the disclosure of the specification to provide understanding and reading for those skilled in the art, and are not used to limit the limit conditions of the present invention, so they have no technical significance, and any modification of the structures, changes of the ratio relationships, or adjustments of the sizes should still fall within the scope of the technical content of the present invention without affecting the technical effects and realizations of the present invention. In addition, the terms "first", "second" and "first" used in the present specification are for clarity of description only, and are not intended to limit the scope of the present invention, and changes or modifications in the relative relationship may be made without substantial changes in the technical content.

Fig. 2A to fig. 2F are schematic cross-sectional views illustrating a method for manufacturing an electronic package 2 according to a first embodiment of the invention.

As shown in fig. 2A, a circuit layer 21 is formed on a carrier substrate 20.

In the present embodiment, the carrier substrate 20 is a transparent plate such as a glass plate or other suitable interlayer plate.

In addition, the circuit layer 21 has a plurality of conductive traces 21a, electrical contact pads 210 and external pads 211 at opposite ends of the conductive traces 21 a.

As shown in fig. 2B, a sealing body 22 is formed on the carrier substrate 20 and the circuit layer 21.

In the present embodiment, the sealing body 22 is a non-conductive body, such as glass cement or an insulating material made of other sealing materials, which is in a ring shape. For example, the sealing member 22 is substantially formed on the carrier substrate 20 and partially covers the conductive traces 21a of the circuit layer 21.

In addition, a plurality of conductive elements 23 are formed on the electrical contact pads 210 of the circuit layer 21. For example, a conductive pillar 230 may be formed on the electrical contact pad 210, and then a conductive layer 231 may be formed on the conductive pillar 230, so that the conductive pillar 230 and the conductive layer 231 form a bulk conductive element 23. Specifically, the conductive pillar 230 is a copper pillar or other metal pillar, and the conductive layer 231 is a solder paste or copper paste formed by printing. It should be understood that the conductive elements 23 can be fabricated in various embodiments, such as solder bumps, copper bumps, etc., as required, and are not limited thereto.

As shown in fig. 2C and 2C', an electronic component 24 having a sensing portion a is disposed on the conductive element 23, and the electronic component 24 is close to the sealing body 22, so that the electronic component 24, the sealing body 22, the circuit layer 21 and the carrier substrate 20 form a sealed cavity S, the sensing portion a and the carrier substrate 20 are respectively located at two opposite sides of the sealed cavity S, and the conductive element 23 is located in the sealed cavity S.

In the embodiment, the electronic component 24 is a sensor component, such as an led (light emitting diode), an MEMS (Micro-electro-mechanical Systems), a CMOS (Complementary Metal-Oxide-Semiconductor) or other Semiconductor chip structure, and has an active surface 24a and an inactive surface 24b opposite to each other, and the active surface 24a has the sensing portion a and a plurality of electrode pads 240, so that the electronic component 24 contacts the sealing body 22 through the active surface 24a, and the electrode pads 240 are combined with the conductive elements 23, so that the electronic component 24 is electrically connected to the circuit layer 21 through the conductive elements 23.

The sensor portion a is provided with a light sensing structure or a fingerprint recognition structure.

The electronic component 24 is substantially rectangular, and the sealing body 22 is rectangular corresponding to the side contour of the electronic component 24.

As shown in fig. 2D, at least one conductive structure 25 is formed on the external pad 211 of the circuit layer 21, and the conductive structure 25 is electrically connected to the circuit layer 21.

In the present embodiment, the conductive structure 25 is in the form of a conductive pillar, for example, a plurality of copper pillars are formed on the circuit layer 21 by electroplating to serve as the conductive structure 25. It should be understood that the conductive posts can be fabricated in a variety of ways, and are not limited to the above.

As shown in fig. 2E, an encapsulation layer 26 is formed on the carrier substrate 20 to encapsulate the conductive structure 25, the electronic element 24 and the sealing body 22.

In the present embodiment, the package layer 26 is not formed in the sealed cavity S, and the conductive structure 25 is embedded in the package layer 26.

In addition, the encapsulation layer 26 has a first surface 26a and a second surface 26b opposite to each other, the first surface 26a is bonded to the carrier substrate 20, and the end surface 25a of the conductive structure 25 is exposed from the second surface 26 b. The end surface 25a of the conductive structure 25 is flush with the second surface 26b of the encapsulation layer 26, for example, by a planarization process that grinds the encapsulation layer 26. The conductive structure 25 may be exposed out of the encapsulation layer 26 in various ways, such as opening, but not limited to the above.

The material forming the sealing layer 26 is a dielectric material, such as liquid Epoxy resin, Film-shaped ABF (ajinomoto build-up Film), Prepreg (Prepreg), Epoxy Molding Compound (EMC), or photosensitive resin, but is not limited to the above.

As shown in fig. 2F, a circuit structure 27 is formed on the second surface 26b of the package layer 26, and the circuit structure 27 is electrically connected to the conductive structure 25.

In the present embodiment, the circuit structure 27 is a single wiring layer, but a plurality of wiring layers, such as a build-up wiring, may be formed as required, and the form of the circuit structure 27 is not particularly limited.

In addition, in the subsequent process, a functional chip 28, such as an Application-specific integrated circuit (ASIC), may be disposed on the circuit structure 27 through the plurality of conductive bumps 280 as required, as shown in fig. 2G.

Fig. 3A to 3D are schematic cross-sectional views illustrating a method for manufacturing an electronic package 3 according to a second embodiment of the invention. The difference between this embodiment and the first embodiment is that the process of the conductive structure is substantially the same as the other processes, and therefore the description of the same parts is omitted.

As shown in fig. 3A, the process shown in fig. 2C is completed.

As shown in fig. 3B, an encapsulation layer 26 is formed on the carrier substrate 20 to encapsulate the electronic component 24 and the sealing body 22.

In the present embodiment, the encapsulation layer 26 has a first surface 26a and a second surface 26b opposite to each other, and the first surface 26a is bonded to the carrier substrate 20.

As shown in fig. 3C, a plurality of through holes 260 are formed on the second surface 26b of the package layer 26, such that the external pads of the circuit layer are exposed out of the through holes 260.

In this embodiment, the through hole 260 is formed by a laser method. It should be understood that the through hole 260 can be made in various ways, and is not limited to the above.

As shown in fig. 3D, at least one conductive structure 35 is formed on the external pads 211 in the through hole 260, and a circuit structure 37 is formed on the second surface 26b of the package layer 26, such that the circuit structure 37 is electrically connected to the circuit layer 21 through the conductive structure 35.

In the present embodiment, the conductive structure 35 is in the form of a conductive via, for example, formed by electroplating the circuit structure 37 and the conductive structure 35 together. It should be understood that the conductive vias can be fabricated in a variety of ways, and are not limited to the above.

The

electronic packages

2 and 3 of the present invention include: a carrier 20, a circuit layer 21, a sealing body 22, an electronic component 24 having a sensing portion a, and a package layer 26.

The circuit layer 21 is disposed on the carrier substrate 20.

The sealing body 22 is disposed on the carrier substrate 20 and the circuit layer 21.

The electronic component 24 is disposed on the sealing body 22, so that a sealed cavity S is formed between the electronic component 24, the sealing body 22, the circuit layer 21 and the carrier substrate 20, and the sensing portion a and the carrier substrate 20 are respectively located at two opposite sides of the sealed cavity S.

The encapsulation layer 26 is disposed on the carrier substrate 20 to encapsulate the electronic component 24 and the sealing member 22.

In one embodiment, the carrier substrate 20 is a transparent plate.

In one embodiment, the seal 22 is non-conductive.

In one embodiment, the electronic component 24 is electrically connected to the circuit layer 21 through a plurality of conductive elements 23, and the conductive elements 23 are located in the sealed cavity S. For example, the conductive element 23 includes a conductive pillar 230 combined with the circuit layer 21 and at least one conductive layer 231 disposed on the conductive pillar 230.

In one embodiment, the package layer 26 has at least one

conductive structure

25, 35 formed therein and electrically connected to the circuit layer 21. For example, at least one

circuit structure

27, 37 electrically connected to the

conductive structures

25, 35 is formed on the encapsulation layer 26. Alternatively, the

conductive structures

25, 35 are in the form of conductive pillars or conductive vias.

In one embodiment, the encapsulation layer 26 is not formed in the sealed cavity S.

In one embodiment, the electronic package 2 further includes a functional chip 28 disposed on the packaging layer 26.

As described above, the method for manufacturing an electronic package and the structure thereof according to the present invention directly form the circuit layer 21 on the transparent carrier substrate 20, and then perform the operations of bonding and sealing the electronic element 24 with the sealing body 22 and the conductive element 23, and then perform the operations of the package layer 26, the

conductive structures

25 and 35, and the

circuit structures

27 and 37, so that the present invention has the following advantages:

first, the following process does not need to use the conventional lid structure, so the manufacturing cost can be reduced, the overall thickness of the electronic package can be reduced, and the production efficiency can be effectively improved.

Secondly, a wire bonding process is not used, thereby reducing the packaging volume of the

electronic packaging parts

2 and 3.

Thirdly, a plurality of chips can be directly packaged on a carrier substrate 20 to achieve the modularization effect and reduce the volume of the subsequent electronic products. As shown in fig. 2G, the ASIC-type functional chip 28 can be directly packaged in a modular manner to reduce the thickness of the whole package structure.

Fourthly, the traditional conductive through silicon via is replaced by the

conductive structures

25 and 35, so that the TSV process with high cost, high integration difficulty and high technical difficulty is not required, and the manufacturing cost can be effectively reduced.

Fifth, compared to the conventional sensing package shown in fig. 1A, the present invention uses the circuit layer 21 on the carrier substrate 20 as an electrical conduction path to reduce the thickness of the structure, and the carrier substrate 20 does not need to place the package lids 19a one by one during the mass production process, thereby simplifying the manufacturing process and improving the efficiency.

Sixth, compared to the conventional sensor package shown in fig. 1B, the present invention does not require semiconductor processes such as TSV fabrication and wafer bonding (wafer bonding) fabrication, thereby greatly reducing the product cost and achieving the same high-hermetic package effect, and the carrier substrate 20 replaces the lid 19B, which not only can be used as an electrical conduction path of a dual-side conduction structure, but also has a lower cost (because the lid 19B with a cavity is not required to be etched in advance due to the time and cost).

Seventh, compared to the conventional sensor package shown in fig. 1C, the carrier substrate 20 of the present invention does not need to be fabricated with a recessed structure, and does not need to place the conventional lid members 19C one by one, and a sealed cavity S is naturally formed by the sealing body 22 and the package layer 26 during the packaging process, so that the product cost can be reduced. In addition, the carrier substrate 20 can be used as an electrical conduction path of the double-sided conduction structure and one side structure of the double-sided upper part.

Eighth, compared to the conventional sensing package shown in fig. 1D, the sealing cavity S formed by the sealing body 22 and the package layer 26 according to the present invention has better sealing performance, and the conventional package substrate 10D does not need to be loaded one by one, so that the process flow can be shortened and the production efficiency can be effectively improved. In addition, the present invention avoids the deformation of the solder balls 15 shown in fig. 1D during the packaging process by the design of the

conductive structures

25 and 35, so as to effectively and precisely control the thickness of the product and improve the alignment precision of the functional chip 28.

The above embodiments are merely illustrative of the principles and technical effects of the present invention, and are not intended to limit the present invention. Any person skilled in the art can modify the above-described embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.

Claims

1. A method of fabricating an electronic package, comprising:

forming a circuit layer on a transparent bearing substrate;

forming a sealing body on the bearing substrate and the circuit layer;

arranging at least one electronic element with a sensing part on the sealing body, so that the electronic element, the sealing body, the circuit layer and the bearing substrate form a sealed cavity, and the sensing part and the bearing substrate are respectively positioned at two opposite sides of the sealed cavity; and

and forming a packaging layer on the bearing substrate to coat the electronic element and the sealing body.

2. The method of manufacturing an electronic package according to claim 1, wherein the sealing body is a non-conductive body.

3. The method of claim 1, wherein the electronic component is disposed on the circuit layer via a conductive element, and the conductive element is disposed in the sealed cavity.

4. The method of claim 3, wherein the conductive element comprises a conductive pillar bonded to the circuit layer and a conductive layer disposed on the conductive pillar.

5. The method of claim 1, wherein the package layer has at least one conductive structure electrically connected to the circuit layer.

6. The method of claim 5, wherein at least one circuit structure electrically connected to the conductive structure is formed on the encapsulation layer.

7. The method of claim 5, wherein the conductive structure is in the form of a conductive pillar or a conductive via.

8. The method of claim 1, wherein the encapsulation layer is not formed in the sealed cavity.

9. The method of claim 1, further comprising disposing a functional chip on the encapsulation layer.

10. An electronic package, comprising:

a carrier substrate, which is transparent;

a circuit layer disposed on the carrier substrate;

the sealing body is arranged on the bearing substrate and the circuit layer;

the electronic element is provided with a sensing part and is arranged on the sealing body, so that a sealing cavity is formed among the electronic element, the sealing body, the circuit layer and the bearing substrate, and the sensing part and the bearing substrate are respectively positioned at two opposite sides of the sealing cavity; and

and the packaging layer is formed on the bearing substrate to coat the electronic element and the sealing body.

11. The electronic package of claim 10, wherein the encapsulant is non-conductive.

12. The electronic package according to claim 10, wherein the electronic component is electrically connected to the circuit layer through a conductive element, and the conductive element is located in the sealed cavity.

13. The electronic package according to claim 12, wherein the conductive element comprises a conductive pillar bonded to the circuit layer and a conductive layer disposed on the conductive pillar.

14. The electronic package according to claim 10, wherein the encapsulation layer has at least one conductive structure formed therein for electrically connecting to the circuit layer.

15. The electronic package according to claim 14, wherein the encapsulation layer has at least one circuit structure electrically connected to the conductive structure.

16. The electronic package according to claim 14, wherein the conductive structure is in the form of a conductive pillar or a conductive via.

17. The electronic package of claim 10, wherein the encapsulation layer is not formed in the sealed cavity.

18. The electronic package of claim 10, further comprising a functional chip disposed on the encapsulation layer.