CN110998729B

CN110998729B - Performing background functions using logic integrated with memory

Info

Publication number: CN110998729B
Application number: CN201880039312.XA
Authority: CN
Inventors: M·S·格罗斯曼; 徐晓玲
Original assignee: Microsoft Technology Licensing LLC
Current assignee: Microsoft Technology Licensing LLC
Priority date: 2017-06-16
Filing date: 2018-05-24
Publication date: 2023-08-22
Anticipated expiration: 2038-05-24
Also published as: US10884656B2; KR102582492B1; EP3639264B1; WO2018231482A1; EP3639264A1; KR20200018509A; US20180364944A1; CN110998729A

Abstract

Logic integrated with memory for performing background functions and related methods are provided. The method in the memory comprises the following steps: processing of the background function is initiated in response to a request from a host separate from the memory. The method further includes automatically monitoring the memory to detect if any standard operations requiring use of at least one of the plurality of memory locations of the memory or at least one data path of the memory are being performed. The method further comprises the steps of: when a standard operation requiring a data path using a storage unit or a memory is detected, the processing of the background function is automatically suspended unless the processing of the background function is only required as a resource provided as a logic portion integrated with the memory and configured to process only the background function.

Description

Performing background functions using logic integrated with memory

Background

Conventional computing systems include a CPU that may be coupled to a memory such as Dynamic Random Access Memory (DRAM). The CPU performs read/write operations on the DRAM to access data stored in the DRAM. As part of these operations, the CPU may issue commands to the DRAM via the DRAM controller. The DRAM may process commands based on its timing specification and provide data to the CPU or store data provided by the CPU.

Disclosure of Invention

In one example, the present disclosure relates to a method in a memory having a plurality of storage units configured to perform standard operations based on at least one specification issued by a standard body. The method may include: processing of the background function is initiated in response to a request from a host separate from the memory using logic integrated with the memory. The method may further include automatically monitoring the memory during processing of the background function using logic integrated with the memory to detect whether any standard operations requiring use of at least one of a plurality of memory locations of the memory or at least one data path of the memory are being performed. The method may further comprise: when standard operations requiring use of at least one of a plurality of memory locations of the memory or at least one data path of the memory are detected, processing of the background function is automatically suspended unless processing of the background function only requires resources provided as part of the logic integrated with the memory and configured to process only the background function.

In another example, the disclosure relates to a memory having a plurality of storage units and logic integrated with the memory, wherein the memory is configured to perform standard operations based on at least one specification issued by a standard body. Logic integrated with the memory may be configured to initiate processing of the background function in response to a request from a host separate from the memory. The logic integrated with the memory may be further configured to automatically monitor the memory during processing of the background function to detect whether any standard operations requiring use of at least one of a plurality of memory locations of the memory or at least one data path of the memory are being performed. The logic integrated with the memory may be further configured to automatically suspend processing of the background function when standard operations requiring use of at least one of the plurality of memory locations of the memory or at least one data path of the memory are detected, unless processing of the background function only requires resources provided as part of the logic integrated with the memory and configured to process only the background function.

In another example, the disclosure relates to a memory having a plurality of memory cells and logic integrated with the memory, wherein the memory is configured to perform standard operations based on at least one specification issued by a standard body. The memory may also be configured to operate in a first mode and in a second mode. In the first mode, the memory may be configured to: in response to a first request from a host separate from the memory, initiating processing of the first background function during processing of the first background function using logic integrated with the memory; automatically monitoring the memory to detect whether any standard operations requiring use of at least one of a plurality of memory locations of the memory or at least one data path of the memory are being performed; and when standard operations requiring use of at least one of the plurality of memory locations of the memory or at least one data path of the memory are detected, automatically suspending processing of the first background function unless processing of the background function only requires resources provided as part of the logic integrated with the memory and configured to process only the background function. In a second mode, the memory may be configured to: initiating processing of a second background function in response to a second request from a host separate from the memory; suspending processing of the second background function in response to a third request from the host; and resuming processing of the second background function in response to the fourth request from the host.

Drawings

The present disclosure is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.

FIG. 1 illustrates a diagram of a memory with enhanced logic and control, according to one example;

FIG. 2 illustrates a diagram of a system that includes memory that can be used to perform functions in the background, according to one example;

FIG. 3 illustrates a diagram of a system including memory with enhanced logic and control, according to one example;

FIG. 4 illustrates a flow chart of a method for performing background functions in memory according to one example; and

fig. 5 illustrates another flow chart showing steps associated with memory according to one example.

Detailed Description

Examples described in this disclosure relate to memories and systems with enhanced logic and control that may be used to perform functions in the background. As an example, the background function may be executed without issuing a command issued by a standard principal (e.g., JEDEC). Some examples relate to memories such as Dynamic Random Access Memories (DRAMs). DRAM is typically coupled to a host (such as a CPU, GPU, or another type of processor) for providing non-volatile memory storage for programs and data. In many cases, due to CPU limitations, data may be read from the DRAM using several DRAM read cycles, and after performing a computing function using the CPU, the result or any other relevant data may be written back to the DRAM using several DRAM write cycles. Such I/O operations are power consuming. For at least this reason, there is a need to better manage the division of responsibility between the CPU and DRAM. Certain examples in this disclosure relate to performing functions using logic contained in memory (e.g., DRAM). The functions may be performed in the background in a timely manner so as not to affect normal read/write operations performed by the DRAM. As an example, the function may be performed during a gap between normal operations such as read/write operations. Advantageously, because separate read write operations (e.g., I/O operations) are not required through the DRAM's interface, long-running functions can be performed in the background while consuming less power; and once the long run function is completed, the results may be read back by an additional operation. In this example, the result of the long run function, once completed, will be stored in the DRAM itself. In one example, enhanced logic and control within the DRAM may track the state of signals indicating the start and completion of DRAM operations. These signals include, but are not limited to, signals such as Row Address Strobe (RAS), column Address Strobe (CAS), clock enable (CKE), other DRAM internal signals, or other DRAM signals received or transmitted via the external interface of the DRAM. In one example, the enhanced logic and control may initiate tasks (e.g., initiate new background functions) based on certain new DRAM commands initiated by the host (e.g., CPU). Such commands may be initiated based on a new combination of existing DRAM signals (e.g., RAS, CAS, CKE or WE) and such background functions may be controlled based on new bits contained in a mode register associated with the DRAM. As an example, the enhanced logic and control may access the MODE registers (e.g., MR0 through MR 3) via a standard LOAD MODE command.

FIG. 1 illustrates a diagram of a memory 100 (with enhanced logic and control) according to one example. In one example, memory 100 may be a Dynamic Random Access Memory (DRAM) chip. Memory 100 may include control logic 110, core banks 112 and 114, bank address terminals (BA [0:n ]) 116, address terminals (A [0:n ]) 118, address latches (e.g., ADDR IN) 120, address stages 122, I/O blocks 130, read latches 132 and 134, multiplexer 136, write stages and drivers 146, multiplexer 144, input/output pins (DQ [0:n ]) 138, and write input FIFO142. Memory 100 may also include enhanced logic and control 150 coupled to multiplexer 152. Memory 100 may receive address information corresponding to data stored in core banks 112 and/or 114 via bank address terminals (BA [0:n ]) 116, address terminals (A [0:n ]) 118, and address stage 122. The address information may be used to select memory locations on the chip. By asserting the row and column addresses in a multiplexed manner, the address terminals can be used for row and column address selection. The number and organization of address terminals and core banks may depend on the size and organization of the memory. The voltage level present at each address terminal may determine a row or column address, respectively, upon RAS or CAS activation. The address information may correspond to a read or write operation. In response to a read operation, memory 100 may provide data to input/output pins (DQ [0:n ]) 138 via I/O block 130, read latches 132 and 134, and multiplexer 136. As part of the read operation, some sequence of steps may occur, including: (1) providing a row address via an address terminal; (2) Asserting the RAS signal by changing the state of the RAS signal from a high level to a low level; (3) Providing a column address via the address terminal after asserting the CAS signal; and (4) after a certain time (specified by the memory timing specification), changing the RAS signal and the CAS signal to inactive levels once data is present on the input/output terminals. These steps may be performed within timing constraints imposed by the memory specification. The write operation may result in data being provided to the memory via the write input FIFO142, the write stage and driver 146, and the I/O block 130. As part of a write operation, some sequence of steps may occur, including: (1) providing a row address via an address terminal; (2) Asserting the RAS signal by changing the state of the RAS signal from a high level to a low level; (3) After asserting the CAS signal, providing the column address via the address terminals; (4) Data is supplied to the memory via the input/output terminal, and the RAS signal and the CAS signal are changed to inactive stages. These steps may be performed within timing constraints imposed by the memory specification. Data under the control of control logic 110 may be written to the corresponding memory banks.

With continued reference to FIG. 1, the enhanced logic AND control 150 may include at least one Arithmetic Logic Unit (ALU) to perform operations such as add, count, compare, bitwise AND, shift, AND bitwise XOR. Enhanced logic and control 150 may also include registers (including general purpose counters, next address value registers, CRC value registers, and other registers for storing intermediate values). The enhanced logic and control 150 may also include data paths and interfaces to read incoming write data and provide the calculated data to the input/output pins of the core memory bank or memory. At least one controller incorporating enhanced logic and control 150 may include logic to: (1) receive regular external commands and enhanced external commands, (2) pass incoming addresses to decoding logic associated with the memory, (3) pass incoming data to the corresponding core memory for the regular commands, (4) receive data from the core bank, (5) generate read and write operations internally, (6) generate new addresses and provide them to the decoding logic, and (7) perform complex operations with multiple internal reads and writes performed in the background without disturbing the timing of the memory operations. Alternatively, memory 100 may provide a mode that modifies standard interface timing in a predictable manner to accommodate background operation. As an example, the standard interface timing of DRAM may be modified by adding additional clock delays to parameters such as tRD and tRD-WR.

Still referring to fig. 1, the enhanced logic and control 150 may be configured to monitor the state of signals indicative of the start and completion of DRAM operations (e.g., when the memory 100 is a DRAM). Such signals include, but are not limited to, signals such as Row Address Strobe (RAS), column Address Strobe (CAS), clock enable (CKE), other DRAM internal signals, or other DRAM signals received or transmitted via the external interface of the DRAM. In some examples, enhanced logic and control 150 may be configured to monitor whether any operations that require changing the state of memory cells in memory 100 have been completed. As an example, enhanced logic and control 150 may be configured to detect whether memory 100 is performing a write operation or a read operation. In one example, the enhanced logic and control 150 may initiate tasks (e.g., initiate new background functions) based on certain new DRAM commands initiated by the host (e.g., CPU). Such commands may be initiated based on a new combination of existing DRAM signals (e.g., RAS, CAS, CKE or WE) and based on utilizing new bits used by a mode register associated with the DRAM. As an example, enhanced logic and control 150 may access MODE registers (e.g., MR0 through MR 3) via a standard LOAD MODE command. The enhanced logic and control 150 may be configured to process functions using its computing resources, including registers and memory resources of the memory 100. Example functions include, but are not limited to: find first event (logging), count event, checksum function, clear constant, test constant, read mask, constant write mask, and error detection and correction.

In one example, enhanced logic and control 150 may be configured to operate memory 100 in two different modes. In a first mode, after a host (e.g., a CPU coupled to memory 100) issues instructions or commands to memory 100 to run certain functions in the background, memory 100 may run those functions in the background in good time without additional instructions from the host. In the second mode, the host may have full control of when memory 100 is allowed to run any function in the background. As an example, in the first mode, enhanced logic and control 150 may be configured to track the state of functions running in the background. The enhanced logic and control 150 may also be configured to suspend functions running in the background and resume functions running in the background. Enhanced logic and control 150 may accomplish this by tracking the state of signals indicating the start and completion of a DRAM operation (e.g., when memory 100 is a DRAM). These signals include, but are not limited to, signals such as Row Address Strobe (RAS), column Address Strobe (CAS), clock enable (CKE), other DRAM internal signals, or other DRAM signals received or transmitted via the external interface of the DRAM. Thus, as an example, the enhanced logic and control 150 may be configured to monitor the status of the RAS and CAS signals. If these signals are inactive for some pre-configured amount of time, enhanced logic and control 150 may initiate or resume a function that the host has requested memory 100 to perform. Any intermediate results generated during processing of one or more functions may be stored in an internal register associated with memory 100. The host may track the status of the function or the enhanced logic and control 150 may be configured to track the status of the function.

In the second mode, the host may have full control of when memory 100 is allowed to run any function in the background. In one example, full control may include: only the host is allowed to use the memory 100 to initiate or resume running background functions. In one example, the host may be configured to indicate to the memory 100 via at least one signal when to initiate or resume a background function. As an example, the host may assert certain signal sequences or signal types using a clock enable (CKE) signal line for memory 100. In another example, the host may assert a signal combination including control and address signals to indicate to memory 100 when to initiate or resume background functionality. Any intermediate results generated during processing of one or more functions may be stored in an internal register associated with memory 100. The host may track the status of the function. Although fig. 1 shows a number of components of memory 100 arranged in some manner, there may be a greater or a greater number of components arranged differently. As an example, enhanced logic and control 150 may be integrated with memory 100 in various ways. One way is to form the logic on the same chip as the memory. Alternatively, the logic portion may be integrated by tightly coupling the logic with the memory. Other ways of integrating logic with memory are described with respect to fig. 2.

Fig. 2 shows a diagram of a system 200, the system 200 comprising memory that may be used to perform functions in the background. The system 200 may include a package substrate 210 connected to an interposer 220. Interposer 220 may also be connected to DRAM logic die 230 and host 280. Host 280 may be a Graphics Processor Unit (GPU), a Central Processing Unit (CPU), or a system on a chip (SOC). Memory die such as DRAM die 240, DRAM die 250, DRAM die 260, and DRAM die 270 may be stacked on top of DRAM logic die 230. DRAM logic die 230 may include components (e.g., PHY 232) and host 280 may also include similar components (e.g., PHY 282). These components may be used to physically interconnect through interposer 220. The DRAM logic die 230 and the stacked DRAM die may be interconnected via micro bumps (Microbump) and Through Silicon Vias (TSV). In this system, the host may advantageously offload even more functionality to a memory system including DRAM logic die 230 and the stacked DRAM die. Thus, in one example, each DRAM die may be similarly configured and used as memory 100. Additionally, each DRAM die may receive additional commands/instructions from DRAM logic die 230. In this way, DRAM logic die 230 may provide control as to when a background function is initiated or when a background function is restored after suspension. As an example, DRAM logic die 230 may control functionality related to security or integrity checks. In another example, each DRAM die may be a standard DRAM die and may not have any enhanced logic and control functions. Rather, all of the enhanced logic and control functions as described with respect to memory 100 of FIG. 1 may be included in DRAM logic die 230. Thus, the system may operate in a third mode in which control of background functionality is shared between DRAM logic die 230 and a host (e.g., host 280). Although fig. 2 shows a number of components of system 200 arranged in some manner, there may be a greater or a greater number of components in different arrangements. As an example, DRAM logic die and DRAM need not be stacked. Similarly, while FIG. 2 shows an interposer for interconnecting DRAM logic die, host, and DRAM die, other interconnect arrangements for integrating logic with memory may be used. As an example, these components may be packages that may be mounted on a PCB or another shared substrate. The host and DRAM die may also be packaged side-by-side in a single package substrate.

FIG. 3 illustrates a diagram of a system 300 according to one example. System 300 shows additional details corresponding to system 200. In one example, system 300 may include multiple memory dies (e.g., HBM DRAM die 380 and HBM DRAM die 390). As shown in fig. 2, in one configuration of the system, these DRAM dies may be stacked on a DRAM logic die. IN one example, system 300 may include control logic 310, DRAM dice 380 and 390, bank address terminals (BA [0:n ]) 318, address terminals (A [0:n ]) 316, address latches (e.g., ADDR IN) 320, address stage 322, multiplexer 352, basic cache 370, enhanced logic and control 350, input/output pins (DQ [0:m-1]336 and DQ [ m:n ] 338). System 300 may receive address information corresponding to data stored in the DRAM die via bank address terminals (BA [0:n ]) 318, address terminals (A [0:n ]) 316, and address stage 322. The address information may be used to select memory locations on the DRAM die and chip. The address terminals may be used for row and column address selection by asserting the row and column addresses in a multiplexed manner. The number and organization of address terminals may depend on the size and organization of the memory.

With continued reference to FIG. 3, the enhanced logic AND control 350 may include at least one Arithmetic Logic Unit (ALU) to perform operations such as add, count, compare, bitwise AND, shift, AND bitwise XOR. Enhanced logic and control 350 may also include registers (including general purpose counters, next address value registers, CRC value registers, and other registers for storing intermediate values). The enhanced logic and control 350 may also include data paths and interfaces to read incoming write data and provide the calculated data to the input/output pins of the core memory bank or memory. At least one controller incorporating enhanced logic and control 350 may include logic to: (1) receiving a regular external command and an enhanced external command, (2) passing the incoming address to decoding logic associated with the memory, (3) passing the incoming data to a corresponding core bank of the regular command, (4) receiving data from the core bank, (5) generating read and write operations internally, (6) generating a new address and providing it to the decoding logic, and (7) executing complex commands with multiple internal reads and writes in the background without disturbing the timing of the memory operations.

Still referring to fig. 3, enhanced logic and control 350 may be configured to monitor the status of signals indicative of the start and completion of DRAM operations associated with any DRAM die included as part of system 300. Such signals include, but are not limited to, signals such as Row Address Strobe (RAS), column Address Strobe (CAS), clock enable (CKE), other DRAM internal signals, or other DRAM signals received or transmitted via a DRAM external interface. In some examples, enhanced logic and control 350 may be configured to monitor whether any operations that require changing the state of memory cells associated with any DRAM have been completed. As an example, enhanced logic and control 350 may be configured to detect whether any of the DRAM die is performing a write operation or a read operation. In one example, the enhanced logic and control 350 may initiate tasks (e.g., initiate new background functions) based on certain new DRAM commands initiated by the host (e.g., CPU). Such commands may be initiated based on a new combination of existing DRAM signals (e.g., RAS, CAS, CKE or WE) and based on utilizing new bits used by a mode register associated with the DRAM. As an example, enhanced logic and control 350 may access the MODE registers (e.g., MR0 through MR 3) via a standard LOAD MODE command. Enhanced logic and control 350 may be configured to process functions using computing resources and memory resources located on DRAM logic die 230 of fig. 2. Example functions include, but are not limited to: find first event, count event, checksum function, clear to constant, test constant, read mask, constant write mask, and error detection and correction. Although fig. 3 shows a number of components of system 300 arranged in some manner, there may be a greater or lesser number of components in different arrangements.

In one example, after a host (e.g., host 280) initiates instructions or commands to run certain functions in the background, enhanced logic and control 350 may run the functions in the background in good time without additional instructions from the host. The enhanced logic and control 350 may be configured to track the state of functions running in the background. The enhanced logic and control 350 may also be configured to suspend functions running in the background and resume functions running in the background. The enhanced logic and control 350 may accomplish this by tracking the state of signals indicating the start and completion of any DRAM operation. Such signals include, but are not limited to, signals such as Row Address Strobe (RAS), column Address Strobe (CAS), clock enable (CKE), other DRAM internal signals, or other DRAM signals received or transmitted via the external interface of the DRAM. Thus, as an example, the enhanced logic and control 350 may be configured to monitor the status of the RAS and CAS signals. If these signals are inactive for a certain pre-configured amount of time, enhanced logic and control 350 may initiate or resume a function that the host has requested to perform. Alternatively, the enhanced logic and control 350 may be configured to monitor the state of a word line or bit line associated with the DRAM to determine when to initiate or resume functionality. Any intermediate results generated during processing of one or more functions may be stored in internal registers associated with enhanced control and logic 350. The host may track the status of the function or the enhanced logic and control 350 may be configured to track the status of the function.

FIG. 4 illustrates a flow chart of a method according to one example. In one example, the steps described in the method may be performed by enhanced logic and control located in a memory such as a DRAM. Step 402 may include initiating processing of a background function in response to a request from a host separate from memory using logic integrated with the memory (e.g., DRAM). Thus, the CPU may request the DRAM to perform background functions other than normal read or write operations. As previously described, logic integrated with the memory (e.g., logic embedded in the DRAM) may begin running the background functions at the appropriate time. As discussed with respect to fig. 5, any of the functional code steps may be delayed due to resource conflicts with new foreground commands. As previously described, any of the functions may be a "find first event" function. The function may include searching for a first address within a specified range of addresses, where the bit pattern matches a reference pattern of some desired length. For simplicity, it is assumed here that the pattern length is a power of 2 (e.g., 1/2 or 1/4) of the line length. One example of a function input and function code is shown in table 1 below:

TABLE 1

Another function may be a count event function, which may include searching a specified address range and counting the number of times the bit pattern matches a reference pattern of a certain length. One example of the function code is shown in table 2 below:

TABLE 2

Another function may be a histogram function, which may include searching for a specified address range and counting the number of item length (itemLength) bit patterns that fall within each of a small number of ranges ("bins"). One example of a function input and function code is shown in table 3 below:

TABLE 3 Table 3

Any of the above functions may also be performed on the encrypted data. To this end, the enhanced logic and control in the DRAM may further include: (1) An electrical fuse for storing one or more master keys, the master keys being programmed in one programming during system configuration; and (2) a register for storing the encryption key. Additionally, the host may need to issue commands to the DRAM to allow the host to send the wrapped encryption key. The DRAM may use the master key to open these wrapped encryption keys and store them. Furthermore, background operations may be limited to a correctly aligned address range (e.g., 256 or 512 bytes) depending on the cryptographic algorithm used. Finally, as part of the function code, each time the read function is invoked, replacement with ReadAndDecrypt (using the appropriate stored encryption key) may be required.

Another function that can be handled is a checksum function. The functions may include: a checksum code (e.g., a Cyclic Redundancy Check (CRC) code) is generated as part of the write operation and the code is checked to confirm that any bits between the start address and the end address are not modified because they were written. The content may be encrypted. Thus, the CRC check may work for both encrypted and decrypted content. The enhanced logic and control previously described may be extended to include registers for storing a predetermined number of checksums. The registers may be configured such that only the host can directly perform read or write operations on these registers. To initiate the checksum, the enhanced logic and control may receive a security command from the host requesting that it generate a checksum for the region between StartAddr and EndAddr. The command may further specify which checksum register(s) to use. As previously described, the enhanced logic and control within the DRAM may perform checksum functions in the background. The security command may only be initiated by the root of trust of the host, and the enhanced logic and control may be the only hardware that may initiate the checksum function. If during the background processing of the checksum function, memory locations in the region between StartAddr and EndAddr are written (e.g., using a non-standard DRAM write command), errors may be generated. Background running of checksum operations may advantageously provide enhanced security. As an example, at programmable intervals, the enhanced logic and control may regenerate a checksum over the same memory region, instead of storing a new value, it may check against a previously stored value. If the verification fails, the enhanced logic and control may require the DRAM to optionally block any further reads from the region (e.g., return to all zeros or some other programmed constant value).

In addition to the above functions, other functions may be performed in the background. Table 4 provides a non-exhaustive list of such functions:

TABLE 4 Table 4

In step 404, during processing of the function, logic integrated with the memory (e.g., embedded in the DRAM) may monitor the memory to detect an operation requiring use of at least one memory cell of the memory or at least one data path of the memory. As previously described with respect to fig. 1, enhanced logic and control 150 may accomplish this by tracking the state of a signal indicating the beginning of an operation of the DRAM (e.g., when memory 100 is a DRAM). These signals include, but are not limited to, signals such as Row Address Strobe (RAS), column Address Strobe (CAS), clock enable (CKE), other DRAM internal signals, or other DRAM signals received or transmitted via the external interface of the DRAM. Thus, as an example, the enhanced logic and control 150 may be configured to monitor the status of the RAS and CAS signals. If these signals are not active for some pre-configured amount of time, enhanced logic and control 150 may initiate a function that the host has requested memory 100 to perform. Alternatively, enhanced logic and control 150 may be configured to monitor the state of a word line or bit line associated with memory 100 to determine when to initiate a function.

Step 406 may include: when an operation requiring use of at least one memory location of the memory is detected, processing of the function is automatically suspended unless processing of the background function is only required to be provided as part of the logic integrated with the memory and configured to process only resources of the background function. The method may further comprise automatically resuming the processing of the function after the operation requiring use of at least one memory location of the memory or at least one data path of the memory is completed. As previously described with respect to fig. 1, enhanced logic and control 150 may accomplish this by tracking the state of a signal indicating the start of operation of the DRAM (e.g., when memory 100 is a DRAM). These signals include, but are not limited to, signals such as Row Address Strobe (RAS), column Address Strobe (CAS), clock enable (CKE), other DRAM internal signals, or other DRAM signals received or transmitted via the external interface of the DRAM. Thus, as an example, the enhanced logic and control 150 may be configured to monitor the status of the RAS and CAS signals. If these signals are not active for some predetermined amount of time, enhanced logic and control 150 may initiate or resume a function that the host has requested memory 100 to perform. Alternatively, enhanced logic and control 150 may be configured to monitor the state of a word line or bit line associated with memory 100 to determine when to resume functionality.

Fig. 5 illustrates another flow chart showing steps associated with memory 100 according to one example. In step 502, a memory, such as a DRAM, may wait for a command. If a foreground command (e.g., a read or write command from a host) is received by the DRAM as in step 510, the DRAM (e.g., enhanced logic and control) may determine whether the background function is running in step 512. If the background function is running, then in step 514, the enhanced logic and control may determine if this causes a resource conflict. Resource conflict may involve determining whether any DRAM resources to be used by the foreground command are being used by the background function in a manner that would adversely affect the performance of the foreground command. In step 516, the enhanced control and logic may delay the background function. After the delay or if no running background function is detected in step 512, the DRAM may execute the foreground command in step 518.

Still referring to FIG. 5, while the DRAM waits for a command to be received, it may initiate a background function (e.g., in step 520). The DRAM may also include the ability to process new foreground commands: foreground results are obtained (step 530). After receiving the command, the enhanced logic and control may determine whether the background function is running (step 532). If no background functions are running, then in step 536, enhanced logic and control may return a background result. Alternatively, the enhanced logic and control may return a message or status (e.g., "incomplete"). Although fig. 5 depicts steps in a certain order, it is not necessary to perform the steps in that order.

In summary, the present disclosure relates to a method in a memory having a plurality of storage units configured to perform standard operations based on at least one specification issued by a standard body. The method may include: processing of the background function is initiated in response to a request from a host separate from the memory using logic integrated with the memory. The method may further include automatically monitoring the memory to detect whether any standard operations requiring use of at least one of a plurality of memory locations of the memory or at least one data path of the memory are being performed during processing of the background function using logic integrated with the memory. The method may further comprise: when standard operations requiring use of at least one of a plurality of memory locations of the memory or at least one data path of the memory are detected, processing of the background function is automatically suspended unless processing of the background function only requires resources provided as part of the logic integrated with the memory and configured to process only the background function.

The method may further include (1) after standard operations requiring use of at least one of the plurality of memory locations of the memory or at least one data path of the memory are completed; or (2) automatically resume processing of the background function upon resolving a resource conflict between the standard operation and the background function. The method may further comprise: in response to a resume request from the host, (1) after standard operations requiring use of at least one of the plurality of storage locations of the memory or at least one data path of the memory are completed, or (2) upon resolution of resource conflicts between standard operations and background functions, resume processing of the background functions.

Monitoring the memory to detect whether any standard operation requires use of at least one of a plurality of memory locations of the memory or at least one data path of the memory may include monitoring a state of at least one signal corresponding to at least a subset of the standard operation.

The method may further include automatically executing the background function without interruption after the background function is restored. The background functionality may be selected from the group consisting of: a find first event function, a count event function, a checksum function, a clear to constant function, a test constant function, a read mask function, a constant write mask function, and an error detection and correction function.

The method may further comprise: the memory receives a non-standard foreground command from the host, and in response to the non-standard foreground command, the memory provides any results generated by the processing of the background function to the host upon completion of the processing of the background function.

In another example, the disclosure relates to a memory having a plurality of memory cells and logic integrated with the memory, wherein the memory is configured to perform standard operations based on at least one specification issued by a standard body. Logic integrated with the memory may be configured to initiate processing of the background function in response to a request from a host separate from the memory. The logic integrated with the memory may also be configured to automatically monitor the memory during processing of the background function to detect whether any standard operations requiring use of at least one of a plurality of memory locations of the memory or at least one data path of the memory are being performed. The logic integrated with the memory may be further configured to automatically suspend processing of the background function when standard operations requiring use of at least one of the plurality of memory locations of the memory or at least one data path of the memory are detected, unless processing of the background function only requires resources provided as part of the logic integrated with the memory and configured to process only the background function.

Logic integrated with the memory may also be configured to (1) after standard operations requiring use of at least one of the plurality of memory locations of the memory or at least one data path of the memory are completed; or (2) automatically resume processing of the background function upon resolving a resource conflict between the standard operation and the background function. Logic integrated with the memory may also be configured to: in response to a resume request from the host, (1) after standard operations requiring use of at least one of the plurality of storage locations of the memory or at least one data path of the memory are completed, or (2) upon resolution of resource conflicts between standard operations and background functions, resume processing of the background functions.

Logic integrated with the memory may also be configured to monitor a state of at least one signal corresponding to at least a subset of the standard operations. Logic integrated with the memory may also be configured to automatically perform the background function without interruption after the background function is restored. The background functionality may be selected from the group consisting of: a find first event function, a count event function, a checksum function, a clear to constant function, a test constant function, a read mask function, a constant write mask function, and an error detection and correction function. The logic integrated with the memory may be further configured to receive a non-standard foreground command from the host and, in response to the non-standard foreground command, provide any results generated by the processing of the background function to the host upon completion of the processing of the background function.

In another example, the disclosure relates to a memory having a plurality of memory cells and logic integrated with the memory, wherein the memory is configured to perform standard operations based on at least one specification issued by a standard body. The memory may be further configured to operate in a first mode and in a second mode. In the first mode, the memory may be configured to: in response to a first request from a host separate from the memory, initiating processing of the first background function during processing of the first background function using logic integrated with the memory; automatically monitoring the memory to detect whether any standard operations requiring use of at least one of a plurality of memory locations of the memory or at least one data path of the memory are being performed; and when standard operations requiring use of at least one of the plurality of memory locations of the memory or at least one data path of the memory are detected, automatically suspending processing of the first background function unless processing of the background function only requires resources provided as part of the logic integrated with the memory and configured to process only the background function. In a second mode, the memory may be configured to: initiating processing of a second background function in response to a second request from a host separate from the memory; suspending processing of the second background function in response to a third request from the host; and resuming processing of the second background function in response to the fourth request from the host.

The memory may be further configured (1) after standard operations requiring use of at least one of the plurality of memory cells of the memory or at least one data path of the memory are completed; or (2) automatically resume processing of the background function upon resolving a resource conflict between the standard operation and the background function. In the first mode, the memory may be further configured to monitor a state of at least one signal corresponding to at least a subset of the standard operations. In the first mode, the memory may also be configured to monitor a state of a word line or bit line of the memory.

The background functionality may be selected from the group consisting of: a find first event function, a count event function, a checksum function, a clear to constant function, a test constant function, a read mask function, a constant write mask function, and an error detection and correction function. Additionally, in the first mode and the second mode, the memory may be further configured to receive a non-standard foreground command from the host and, after processing of the respective background function is completed, to provide any results generated by processing of the first background function or the second background function to the host in response to the non-standard foreground command.

It should be understood that the methods, modules, and components described herein are merely exemplary. Alternatively or additionally, the functions described herein may be performed, at least in part, by one or more hardware logic components. For example, but not limited to, exemplary types of hardware logic components that can be used include Field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), complex Programmable Logic Devices (CPLDs), and the like. In an abstract, but still definite sense, arrangement of components to achieve the same functionality is effectively "associated" such that the desired functionality is achieved. Thus, any two components herein combined to achieve a particular functionality can be seen as "associated with" each other such that the desired functionality is achieved, irrespective of architectures or intermedial components. Likewise, any two components so associated can also be viewed as being "operably connected," or "coupled," to each other to achieve the desired functionality.

The functionality associated with some examples described in this disclosure may also include instructions stored in a non-transitory medium. The term "non-transitory medium" as used herein refers to any medium that stores data and/or instructions that cause a machine to operate in a specific manner. Exemplary non-transitory media include non-volatile media and/or volatile media. Non-volatile media includes, for example, hard disk, solid state drive, magnetic disk or tape, optical disk or tape, flash memory, EPROM, NVRAM, PRAM, or other such media, or networked versions of such media. Volatile media include, for example, dynamic memory (e.g., DRAM, SRAM, cache) or other such media. Non-transitory media are different from, but may be used in combination with, transmission media. The transmission medium is used to transmit data and/or instructions to or from the machine. Exemplary transmission media include coaxial cables, fiber optic cables, copper wire and wireless media (e.g., radio waves).

Furthermore, those skilled in the art will recognize that boundaries between the functionality of the above described operations merely illustrative. The functionality of multiple operations may be combined into a single operation, and/or the functionality of a single operation may be distributed in other operations. Further, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments.

Although the present disclosure provides specific examples, various modifications and changes may be made without departing from the scope of the present disclosure as set forth in the appended claims. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present disclosure. Any benefits, advantages, or solutions to problems that are described herein with regard to specific examples are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.

Furthermore, the terms "a" or "an," as used herein, are defined as one or more. Moreover, even though the same claims contain the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" or "an", the use of introductory phrases such as "at least one" and "one or more" in the claims should not be interpreted to imply that the introduction of another claim element by the indefinite articles "a" or "an" limits any particular claim containing such introduced claim element to inventions containing only one such element. The same holds true for the use of definite articles.

Unless otherwise indicated, terms such as "first" and "second" are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.

Claims

1. A memory having a plurality of memory cells and logic integrated within the memory, wherein the memory is configured to perform standard operations based on at least one specification issued by a standard body, the logic integrated within the memory configured to:

initiating processing of a background function in response to a request from a host separate from the memory;

during processing of the background function, automatically monitoring the memory to detect whether any standard operations requiring use of at least one of the plurality of memory locations of the memory or at least one data path of the memory are being performed; and

when the standard operation requiring use of the at least one storage unit of the plurality of storage units of the memory or the at least one data path of the memory is detected, the processing of the background function is automatically suspended unless the processing of the background function requires resources provided only as part of the logic integrated within the memory and resources allocated only to process the background function.

2. The memory of claim 1, wherein the logic integrated within the memory is further configured to (1) after the standard operation requiring use of the at least one of the plurality of memory cells of the memory or the at least one data path of the memory is completed; or (2) automatically resuming processing of the background function upon resolving a resource conflict between the standard operation and the background function.

3. The memory of claim 1, wherein the logic integrated within the memory is further configured to: in response to a resume request from the host, (1) after the standard operation requiring use of the at least one of the plurality of storage units of the memory or the at least one data path of the memory is completed, or (2) upon resolution of a resource conflict between the standard operation and the background function, resume processing of the background function.

4. The memory of claim 1, wherein the logic integrated within the memory is further configured to monitor a state of at least one signal corresponding to at least a subset of the standard operations.

5. The memory of claim 2, wherein the logic integrated within the memory is further configured to automatically execute the background function without interruption after the background function is restored.

6. The memory of claim 1, wherein the background function is selected from the group consisting of: a find first event function, a count event function, a checksum function, a clear to constant function, a test constant function, a read mask function, a constant write mask function, and an error detection and correction function.

7. The memory of claim 1, wherein the memory is further configured to receive a non-standard foreground command from the host and, in response to the non-standard foreground command, to provide any results generated by the processing of the background function to the host upon completion of the processing of the background function.

8. A method in a memory having a plurality of memory locations, the memory configured to perform standard operations based on at least one specification issued by a standard body, the method comprising:

initiating processing of a background function in response to a request from a host separate from the memory using logic integrated within the memory;

During processing of the background function using the logic integrated within the memory, automatically monitoring the memory to detect whether any standard operations requiring use of at least one of the plurality of memory locations of the memory or at least one data path of the memory are being performed; and

9. The method of claim 8, further comprising (1) after the standard operation requiring use of the at least one of the plurality of memory locations of the memory or the at least one data path of the memory is completed; or (2) automatically resuming processing of the background function upon resolving a resource conflict between the standard operation and the background function.

10. The method of claim 8, further comprising, in response to a resume request from the host, (1) resuming processing of the background function after the standard operation requiring use of the at least one of the plurality of storage units of the memory or the at least one data path of the memory is completed, or (2) upon resolution of a resource conflict between the standard operation and the background function.

11. The method of claim 8, wherein monitoring the memory to detect whether any standard operations requiring use of the at least one of the plurality of memory locations of the memory or the at least one data path of the memory include monitoring a state of at least one signal corresponding to at least a subset of the standard operations.

12. The method of claim 9, further comprising automatically executing the background function without interruption after the background function is restored.

13. The method of claim 8, wherein the background function is selected from the group consisting of: a find first event function, a count event function, a checksum function, a clear to constant function, a test constant function, a read mask function, a constant write mask function, and an error detection and correction function.

14. The method of claim 8, further comprising the memory receiving a non-standard foreground command from the host, and the memory providing any results generated by the processing of the background function to the host upon completion of the processing of the background function in response to the non-standard foreground command.

15. A memory having a plurality of memory cells and logic within the memory, wherein the memory is configured to perform standard operations based on at least one specification issued by a standard body, wherein the memory is configured to operate in a first mode and in a second mode, wherein in the first mode the memory is configured to:

initiating processing of a first background function in response to a first request from a host separate from the memory;

during processing of the first background function using the logic integrated within the memory, automatically monitoring the memory to detect whether any standard operations requiring use of at least one of the plurality of memory locations of the memory or at least one data path of the memory are being performed; and

When the standard operation requiring use of the at least one storage unit of the plurality of storage units of the memory or the at least one data path of the memory is detected, unless the processing of the first background function requires resources provided only as part of the logic within the memory and resources allocated only to process only the first background function, otherwise the processing of the first background function is automatically suspended; and

in the second mode, the memory is configured to:

initiating processing of a second background function in response to a second request from the host separate from the memory;

suspending the processing of the second background function in response to a third request from the host; and

in response to a fourth request from the host, the processing of the second background function is resumed.

16. The memory of claim 15, wherein in the first mode, the memory is further configured to (1) after the standard operation requiring use of the at least one of the plurality of memory cells of the memory or the at least one data path of the memory is completed; or (2) automatically resuming processing of the first background function upon resolving a resource conflict between the standard operation and the first background function.

17. The memory of claim 15, wherein in the first mode, the memory is further configured to monitor a state of at least one signal corresponding to at least a subset of the standard operations.

18. The memory of claim 15, wherein in the first mode, the memory is further configured to monitor a state of a word line or bit line of the memory.

19. The memory of claim 15, wherein the first background function or the second background function is selected from the group consisting of: a find first event function, a count event function, a checksum function, a clear to constant function, a test constant function, a read mask function, a constant write mask function, and an error detection and correction function.

20. The memory of claim 15, wherein in both the first mode and the second mode, the memory is further configured to receive a non-standard foreground command from the host and, in response to the non-standard foreground command, to provide any results generated by the processing of the first background function or the second background function to the host upon completion of the processing of the respective background function.