CN110991130A - Method for checking standard unit time sequence library by circuit simulation - Google Patents
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Abstract
A method for checking a standard cell timing library using circuit simulation, comprising the steps of: 1) selecting an inspection unit and constructing an inspection circuit; 2) calculating the input conversion value and the output load value of the checking unit; 3) looking up a table to obtain a time sequence value of the time sequence arc corresponding to the checking unit; 4) setting an input voltage/temperature condition, and generating a simulation circuit and an excitation signal; 5) performing spice simulation on the inspection unit to obtain a simulation result; 6) and comparing and displaying the simulation result with the time sequence value of the corresponding time sequence arc of the inspection unit. The method for checking the standard cell time sequence library by using circuit simulation can effectively help a designer to find problems, examine the time sequence performance trend change of cells and help the designer to select the cell types under different conditions.
Description
Technical Field
The invention relates to the technical field of EDA (electronic design automation) design, in particular to a method for checking a standard cell time sequence library by utilizing circuit simulation.
Background
As digital integrated circuit designs become more complex, hierarchical designs using standard cell libraries are required. Wherein the Timing Library (Timing Library) of the standard cell Library defines the Timing performance of each of the cells from input to output Timing edges (Timing Arc). In the process of timing analysis and optimization, a Static Timing Analysis (STA) tool can calculate the delay of each unit and each network in the timing path according to the information of the standard unit timing library, thereby checking whether the timing path delay meets the requirement of timing constraint.
Under the advanced process condition of 16nm and below, the influence of various process effects on the time sequence becomes more sensitive (such as Miller effect, long tail effect and the like), so that the errors of data obtained by calculation of an STA method and actual results of a chip become larger. This phenomenon is particularly prominent for low voltage designs. The designer needs to check the cell timing library in advance at the initial stage of design to ensure subsequent timing convergence and design quality.
The standard cell time series library is obtained by a standard cell library characterization extraction (K library) tool. Typically, the generation of a standard cell timing library takes weeks or even months. Some EDA tools use artificial intelligence to accelerate, and predict a new timing library through the existing timing library information, but the obtained timing value often has a certain accuracy error.
The timing library of standard cells is very important for digital integrated circuit design, and it determines the subsequent timing convergence and design performance. While standard cell library characterization extraction (K library) tools require a significant amount of time to produce cell sequence library content. How to quickly verify the contents of the time sequence library of the standard cell and ensure that the precision requirement under the advanced process condition is met becomes a requirement of designers and a challenge in the industry.
Disclosure of Invention
In order to solve the defects of the prior art, the invention aims to provide a method for checking a standard cell timing library by using circuit simulation, which can effectively help a designer to find problems, examine the trend change of the timing performance of a cell and help the designer to select the cell type under different conditions.
In order to achieve the above object, the method for checking a standard cell timing library by circuit simulation provided by the present invention comprises the following steps:
1) selecting an inspection unit and constructing an inspection circuit;
2) calculating the input conversion value and the output load value of the checking unit;
3) looking up a table to obtain a time sequence value of the time sequence arc corresponding to the checking unit;
4) setting an input voltage/temperature condition, and generating a simulation circuit and an excitation signal;
5) performing spice simulation on the inspection unit to obtain a simulation result;
6) and comparing and displaying the simulation result with the time sequence value of the corresponding time sequence arc of the inspection unit. Further, before the step 1), reading in the standard cell time sequence library information, and the corresponding spice model and sub-circuit file.
Further, the sub-circuit file includes transistor interconnection information inside each of the standard cells.
Further, the step 6) further includes displaying the difference between the simulation result and the timing value of the timing arc corresponding to the inspection unit in a graphical manner, and displaying the timing performance trend of the inspection unit under different working voltages or temperature conditions.
Further, the step 1) further comprises: the input stage of the previous stage and the output stage of the next stage of the inspection unit are constructed by the same number of the same units to form a three-stage circuit structure of the input stage, the current stage and the output stage.
Further, the step 3) further comprises: inquiring the time sequence value D of the time sequence arc of the checking unit under the corresponding condition in the time sequence library according to the input conversion value and the output load value of the checking unit0。
Further, the step 4) further comprises: a fixed voltage/temperature condition or a linearly varying voltage/temperature condition is set.
To achieve the above object, the present invention also provides a computer readable storage medium having stored thereon computer instructions which, when executed, perform the method steps of checking a standard cell timing library with circuit emulation as described above.
In order to achieve the above object, the present invention further provides an apparatus for checking a standard cell timing library, including a memory and a processor, wherein the memory stores computer instructions running on the processor, and the processor executes the computer instructions to execute the method steps for checking the standard cell timing library by using circuit simulation as described above.
The method for checking the standard unit time sequence library by using circuit simulation has the following beneficial effects:
1) the standard cell timing library content can be quickly checked in an EDA tool using SPICE simulation methods.
2) And checking whether the values in the cell timing library are consistent with the SPICE simulation result under the condition of fixed voltage or temperature.
2) The method can effectively help a designer to find problems, examine the time sequence performance trend change of the unit through the change of input voltage and temperature conditions, and help the designer to select the unit under different conditions.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a flow chart of a method for checking a standard cell timing library using circuit simulation according to the present invention;
FIG. 2 is a diagram illustrating contents of a standard cell timing library according to an embodiment of the method for checking the standard cell timing library using circuit simulation of the present invention;
FIG. 3 is a schematic diagram of a FO4 circuit structure according to an embodiment of the method for checking the standard cell timing library by circuit simulation of the present invention;
FIG. 4 is a diagram illustrating comparison of simulation results according to an embodiment of the method for checking a standard cell timing library by circuit simulation of the present invention;
FIG. 5 is a schematic diagram of cell performance under different conditions according to an embodiment of the method for checking a standard cell timing library using circuit simulation of the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.
Fig. 1 is a flowchart illustrating a method for checking a standard cell timing library using circuit simulation according to the present invention, and the method for checking a standard cell timing library using circuit simulation according to the present invention will be described in detail with reference to fig. 1.
First, in step 101, standard cell timing library information is read in, along with the SPICE Model and subbckt files that match it. In this step, the EDA tool reads in the timing library and the corresponding SPICE Model and subbckt files. Generally speaking, a Foundry will provide a SPICE Model file corresponding to a library element under certain process conditions.
Preferably, the Subckt file gives the transistor interconnection information inside each standard cell.
In step 102, a cell to be inspected is selected and an inspection circuit is constructed.
Preferably, the same number of units are used to form a three-stage circuit structure of the input stage, the current stage and the output stage, and the input transition and the output load size of the unit are obtained through calculation. In this step, after the inspection unit is selected, the EDA tool automatically constructs an inspection circuit, for example: the FO4 circuit configuration, which represents a typical operating condition for a cell, automatically configures the FO4 circuit configuration to obtain the input transition and output load values for the cell.
In step 103, a table lookup method is used to obtain a Timing value D corresponding to Timing Arc in the unit Timing library0. In this step, the { transition, load } binary group is used in the cell timing libraryIn the data table, the time sequence value D of a certain Timing Arc unit under the condition is obtained by table look-up0。
In step 104, input voltage and input temperature conditions are specified. In this step, a fixed voltage/temperature may be created, or a certain condition may be specified to perform a scan change, creating a simulation task of voltage/temperature scan, for example: the input voltage is varied from 1.0 volt to 2.0 volts, increasing in steps of 0.2 volts each time.
In step 105, an excitation signal is generated according to the conversion value and the load value, a SPICE simulator is called, and SPICE circuit simulation is carried out on the checking unit. In this step, according to the transition value and the load value, the tool will automatically generate the excitation signal, call the SPICE simulator, and perform SPICE circuit simulation on the checking unit.
Preferably, after the simulation task is finished, the simulation result of the TimingArc in the unit is obtained, and the time sequence simulation result D of the TimingArc is collected1And the definition value D in the cell timing library0A comparison is made.
In step 106, D is compared0And D1And adopting a graphical display method to report results. In the step, the difference between the simulation result and the content in the cell timing sequence library is displayed by using an EDA tool graphical display method, and the timing sequence performance trend of the cell under different working voltages or temperature conditions is displayed.
The method for checking the standard cell timing library by circuit simulation according to the present invention will be further described with reference to an embodiment.
FIG. 2 is a diagram illustrating the contents of a standard cell Timing library according to an embodiment of the present invention, wherein the contents of the standard cell Timing library, a Timing edge (Timing Arc) information of the AND2 cell from the input pin A1 to the output pin Z, is shown in FIG. 2. Wherein the contents of the table of figure 2 define the delay values of the signal rise/fall.
Assuming that there is a standard cell Timing library under certain process conditions, the specific Timing information for each Timing Arc in a cell is composed of a table similar to that shown in FIG. 2. The checking tool can read in the time sequence library and simultaneously read in the SPICE Model file and Subckt file information matched with the time sequence library.
Selecting a certain cell to be checked, for example: AND2, checking whether the Timing values defined by Timing Arc of a1 to Z in the Timing library are accurate.
Fig. 3 is a schematic diagram of a circuit structure of FO4 according to an embodiment of the method for checking a standard cell timing library by circuit simulation of the present invention, and as shown in fig. 3, a FO4 checking circuit structure is constructed, and a FO4 circuit structure is constructed, in which an input of a previous stage and an output of a subsequent stage are constructed by the same cell, and each stage includes N =4 cells with the same number. The transfer value of the AND2 cell at input pin A1 AND the load value at output pin Z are calculated. The definition values D of A1 to Z in the cell timing library are obtained by looking up the table in FIG. 20。
An input voltage and an input temperature are specified. Either fixed voltage and temperature (which may be chosen by default to be consistent with the cell timing library) or specified voltage or temperature, varying linearly from a starting value to an ending value.
According to the transition value and the load value, the tool automatically generates a simulation circuit and an excitation signal, calls a SPICE simulator to carry out SPICE simulation of the unit, and obtains simulation result values D from A1 to Z1。
FIG. 4 is a schematic diagram showing comparison of simulation results according to the embodiment of the method for checking the standard cell timing library by circuit simulation of the present invention, comparison D0And D1And adopting a graphical display method to report the result, as shown in FIG. 4, comparing the SPICE simulation result with the Timing Arc content in the cell Timing library under the condition of fixed working voltage and temperature, and displaying the Timing edge (Timing Arc) of the inspection cell and the simulation result D thereof1And definition content D in the time sequence library0The difference in (a).
Fig. 5 is a schematic diagram of unit performance under different conditions according to an embodiment of the method for checking a standard cell timing library by circuit simulation of the present invention, and as shown in fig. 5, SPICE simulation results of a cell under different input conditions are obtained by scanning operating voltage or temperature, so as to analyze a timing performance trend of the cell, and also to display a variation trend of timing performance of the cell under different voltages or different temperatures.
The invention provides a method for checking a standard cell time sequence library by circuit simulation, which is characterized in that a typical circuit structure is built to obtain transition and load values, an excitation signal is automatically generated, and the Timing Arc time sequence values of cells in the time sequence library are checked and verified by using SPICE circuit simulation technology, so that a designer can be effectively helped to find problems, the time sequence performance trend change of the cells can be investigated by the change of input voltage and temperature conditions, and the designer is helped to carry out cell type selection under different conditions.
To achieve the above object, the present invention also provides a computer readable storage medium having stored thereon computer instructions which, when executed, perform the method steps of checking a standard cell timing library with circuit emulation as described above.
In order to achieve the above object, the present invention further provides an apparatus for checking a standard cell timing library, including a memory and a processor, wherein the memory stores computer instructions running on the processor, and the processor executes the computer instructions to execute the method steps for checking the standard cell timing library by using circuit simulation as described above.
Those of ordinary skill in the art will understand that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. A method for checking a standard cell timing library by circuit simulation is characterized by comprising the following steps:
1) selecting an inspection unit and constructing an inspection circuit;
2) calculating the input conversion value and the output load value of the checking unit;
3) looking up a table to obtain a time sequence value of the time sequence arc corresponding to the checking unit;
4) setting an input voltage/temperature condition, and generating a simulation circuit and an excitation signal;
5) performing spice simulation on the inspection unit to obtain a simulation result;
6) and comparing and displaying the simulation result with the time sequence value of the corresponding time sequence arc of the inspection unit.
2. The method for checking a standard cell timing library using circuit simulation as claimed in claim 1, further comprising, before said step 1), reading in standard cell timing library information, and corresponding spice models and sub-circuit files.
3. The method of checking a standard cell timing library using circuit simulation as claimed in claim 2, wherein the sub-circuit file includes transistor interconnection information inside each of the standard cells.
4. The method for checking a standard cell timing library using circuit simulation as claimed in claim 1, wherein said step 6) further comprises graphically displaying the difference between the simulation result and the timing value of the corresponding timing arc of the checking cell, and the timing performance trend of the checking cell under different operating voltage or temperature conditions.
5. The method for checking a standard cell timing library using circuit simulation as claimed in claim 1, wherein the step 1) further comprises: the input stage of the previous stage and the output stage of the next stage of the inspection unit are constructed by the same number of the same units to form a three-stage circuit structure of the input stage, the current stage and the output stage.
6. The method of claim 1 or 2 using circuit simulationThe method for searching the standard cell time sequence library is characterized in that the step 3) further comprises the following steps: inquiring the time sequence value D of the time sequence arc of the checking unit under the corresponding condition in the time sequence library according to the input conversion value and the output load value of the checking unit0。
7. The method for checking a standard cell timing library using circuit simulation as claimed in claim 1, wherein the step 4) further comprises: a fixed voltage/temperature condition or a linearly varying voltage/temperature condition is set.
8. A computer readable storage medium having stored thereon computer instructions, wherein the computer instructions when executed perform the method steps of any of claims 1 to 7 for checking a standard cell timing library using circuit emulation.
9. An apparatus for checking a standard cell timing library, comprising a memory and a processor, wherein the memory stores computer instructions running on the processor, and the processor executes the computer instructions to perform the method steps of any one of claims 1 to 7 for checking the standard cell timing library using circuit emulation.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112232006A (en) * | 2020-10-26 | 2021-01-15 | 海光信息技术股份有限公司 | Standard cell library verification method and device, electronic equipment and storage medium |
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| CN102436533A (en) * | 2011-12-30 | 2012-05-02 | 中国科学院微电子研究所 | Time sequence verification method for standard cell library model |
| US20150213168A1 (en) * | 2014-01-30 | 2015-07-30 | Mentor Graphics Corporation | Logic equivalency check using vector stream event simulation |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112232006A (en) * | 2020-10-26 | 2021-01-15 | 海光信息技术股份有限公司 | Standard cell library verification method and device, electronic equipment and storage medium |
| CN112232006B (en) * | 2020-10-26 | 2021-07-02 | 海光信息技术股份有限公司 | Standard cell library verification method and device, electronic equipment and storage medium |
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