CN110941578A - LIO design method and device with DMA function - Google Patents
LIO design method and device with DMA function Download PDFInfo
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- CN110941578A CN110941578A CN201911175718.3A CN201911175718A CN110941578A CN 110941578 A CN110941578 A CN 110941578A CN 201911175718 A CN201911175718 A CN 201911175718A CN 110941578 A CN110941578 A CN 110941578A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
- G06F13/282—Cycle stealing DMA
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Abstract
The invention discloses a design method and a device of LIO with DMA function, wherein a command analysis and control module is used for analyzing a command sent by a bus and carrying out corresponding processing and control according to the command; the address mapping module is used for converting the FLASH address received from the command analysis and control module into an external equipment address and sending the external equipment address to the receiving and sending control module; the receiving and transmitting control module is used for writing data into the transmitting cache and reading data from the receiving cache; the receiving and transmitting cache is used for matching the transmission speed of a transmission line and an LIO bus between the controller and the FLASH simulator, and the data stored in the receiving and transmitting cache consists of addresses and data; the LIO control module is used for realizing an LIO read-write time sequence; the DMA control module is used for providing an external control interface for DMA transmission; when the LIO is used for communicating with the external equipment, the external equipment can directly exchange data with the system memory without passing through the processor, so that the LIO transmission speed is improved, and the running load of the processor is also reduced.
Description
Technical Field
The invention relates to the field of data transmission, in particular to a design method and a device of LIO with a DMA function.
Background
Interpretation of terms:
LIO bus: english is called LocalIO, a transmission bus.
DMA: the English full name Direct Memory Access is an interface technology for directly exchanging data with a system Memory without a CPU (central processing unit) by an external device.
In the prior art: some processors, such as Loongson 2F and Loongson 2K1000, are designed with LIO, also known as LocalBus interface, which can be used to connect memory for system boot. In practice, LIO is also often used as a parallel interface for communicating with external devices, but unfortunately none of these processors has designed a DMA controller for LIO, i.e. it is impossible to use DMA to transfer data with external devices when LIO communication is used. No solution to this problem has been seen at present.
Disclosure of Invention
The invention provides a design method and a device of an LIO with a DMA function, and aims to solve the problem that LIO integrated by some processors cannot perform DMA transmission without DMA.
In order to achieve the above object, the present invention provides a method for designing an LIO having a DMA function, the method comprising:
designing a FLASH simulator, wherein the FLASH simulator comprises: the command analysis and control module is used for analyzing the command sent by the bus and performing corresponding processing and control according to the command; the address mapping module is used for converting the FLASH address received from the command analysis and control module into an external equipment address and sending the external equipment address to the receiving and sending control module; the receiving and transmitting control module is used for writing data into the transmitting cache and reading data from the receiving cache;
designing a receiving cache and a sending cache, wherein the receiving cache and the sending cache are used for matching transmission lines between a controller and a FLASH simulator and the transmission speed of an LIO bus, and data stored in the receiving cache and the sending cache are composed of addresses and data;
designing an LIO control module, wherein the LIO control module is used for realizing an LIO read-write time sequence;
the DMA control module is designed and used for providing an external control interface for DMA transmission.
The principle of the invention is as follows: because the LIO has no DMA function, the processor needs to complete the data transmission each time when the processor communicates with the external equipment, thereby greatly increasing the load of the processor and reducing the data transmission speed. The invention provides a design method and a device of LIO with DMA function, when LIO is used for communicating with external equipment, the external equipment can directly exchange data with a system memory without a processor, so that the LIO transmission speed is improved, and the operation load of the processor is also reduced.
Preferably, the command analysis and control module is used for analyzing the command sent by the bus, and if the command analysis and control module analyzes that the command is a write data command, the address is sent to the address mapping module, and the data is sent to the transceiving control module; if the analyzed data is the data reading command, the address is sent to the address mapping module, and the data is read from the transceiving control module.
Preferably, the address and data of the cache are written in by the transceiving control module and read out by the LIO control module; the address of the receiving buffer is written in by the receiving and sending control module and read out by the LIO control module, and the data is written in by the LIO control module and then read out by the receiving and sending control module.
Preferably, the LIO control module is configured to implement an LIO read-write timing sequence, and includes: sending the address and data read from the send cache onto the LIO bus; the LIO bus transmits the address read from the receive buffer and writes the read data to the receive buffer.
Preferably, the external control interface for providing DMA transfer by the DMA control module comprises: a DMA _ REQ interface, a DMA _ ACK interface and a DMA _ DONE interface; the DMA _ REQ is a request signal of an external device, and the DMA control module sends an interrupt signal to the processor after receiving the request signal and informs the processor to start DMA transmission; DMA _ ACK is a reply indication to the request signal indicating that DMA transfer has started; DMA _ DONE indicates DMA transfer completion.
Preferably, the processor is a NAND controller or a PCIE controller, and the LIO interface is extended through a NAND bus or a PCIE bus.
In another aspect, the present invention further provides an LIO interface apparatus with DMA function, where the apparatus includes:
the FLASH simulator comprises: the command analysis and control module is used for analyzing the command sent by the bus and performing corresponding processing and control according to the command; the address mapping module is used for converting the FLASH address received from the command analysis and control module into an external equipment address and sending the external equipment address to the receiving and sending control module; the receiving and transmitting control module is used for writing data into the transmitting cache and reading data from the receiving cache;
the receiving and sending caches are used for matching transmission speed of a transmission line and an LIO bus between the controller and the FLASH simulator, and data stored in the receiving and sending caches consist of addresses and data;
the LIO control module is used for realizing an LIO read-write time sequence;
and the DMA control module is used for providing an external control interface for DMA transmission.
Further, the command analysis and control module is used for analyzing the command sent by the bus, and if the command analysis and control module analyzes that the command is a write data command, the address is sent to the address mapping module, and the data is sent to the transceiving control module; if the analyzed data is the data reading command, the address is sent to the address mapping module, and the data is read from the transceiving control module.
Furthermore, the address and data of the sending buffer are written in by the transceiving control module and read out by the LIO control module; the address of the receiving buffer is written in by the receiving and sending control module and read out by the LIO control module, and the data is written in by the LIO control module and then read out by the receiving and sending control module.
Further, the external control interface for providing DMA transfer by the DMA control module includes: a DMA _ REQ interface, a DMA _ ACK interface and a DMA _ DONE interface; the DMA _ REQ is a request signal of an external device, and the DMA control module sends an interrupt signal to the processor after receiving the request signal and informs the processor to start DMA transmission; DMA _ ACK is a reply indication to the request signal indicating that DMA transfer has started; DMA _ DONE indicates DMA transfer completion.
One or more technical schemes provided by the invention at least have the following technical effects or advantages:
the invention provides a design method and a device of LIO with DMA function, when LIO is used for communicating with external equipment, the external equipment can directly exchange data with a system memory without a processor, so that the LIO transmission speed is improved, and the operation load of the processor is also reduced.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention;
FIG. 1 is a hardware block diagram of the present invention;
fig. 2 is a schematic diagram of the NAND FLASH simulator.
Detailed Description
In order that the above objects, features and advantages of the present invention can be more clearly understood, a more particular description of the invention will be rendered by reference to the appended drawings. It should be noted that the embodiments and features of the embodiments of the present application may be combined with each other without conflicting with each other.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced in other ways than those specifically described and thus the scope of the present invention is not limited by the specific embodiments disclosed below.
It will be understood by those skilled in the art that in the present disclosure, the terms "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used in an orientation or positional relationship indicated in the drawings for ease of description and simplicity of description, and do not indicate or imply that the referenced devices or components must be constructed and operated in a particular orientation and thus are not to be considered limiting.
It is understood that the terms "a" and "an" should be interpreted as meaning that a number of one element or element is one in one embodiment, while a number of other elements is one in another embodiment, and the terms "a" and "an" should not be interpreted as limiting the number.
The hardware block diagram of the present invention is shown in fig. 1, and the design idea of the present invention is to extend an LIO interface with a DMA function through a NAND bus by using a processor-integrated NAND controller or a PCIE controller (only the case of a NAND controller is described in the present invention). The parts participating in realizing the function are a NAND controller, a DMA controller, an interrupt controller in the processor, an NAND FLASH simulator designed by FPGA, a transceiving cache, an LIO control module and a DMA control module.
NAND FLASH simulator: the NAND FLASH simulator shown in fig. 2 is composed of function blocks such as a command parsing and control module, an address mapping module, a transceiving control module, etc. The command analysis and control module is responsible for analyzing the command sent by the NAND bus and performing corresponding processing and control according to the command. If the command analysis and control module analyzes that the command is a write data command, the address is sent to the address mapping module, and the data is sent to the transceiving control module; if the command is a read data command, the address is sent to the address mapping module, and the data is read from the transceiving control module. The address mapping module is responsible for converting the NAND FLASH address received from the command parsing and control module into an external device address and transmitting the external device address to the transceiving control module. The receiving and transmitting control module is responsible for writing data into the transmitting cache and reading data from the receiving cache.
Receiving and caching, sending and caching: the receiving and transmitting buffer is used for matching the transmission speed of the NAND BUS and the LIO BUS, and the data stored in the receiving and transmitting buffer consists of addresses and data. The address and data of the sending and caching are written in by the receiving and sending control module and read out by the LIO control module; the address of the receiving buffer is written in by the receiving and sending control module and read out by the LIO control module, and the data is written in by the LIO control module and then read out by the receiving and sending control module.
An LIO control module: the functions comprise the realization of LIO read-write time sequence; sending the address and data read from the issue cache onto the LIO bus; the LIO bus transmits the address read from the receive buffer and writes the read data to the receive buffer.
A DMA control module: an external control interface for DMA transmission is provided, the DMA _ REQ is a request signal of an external device, and the DMA control module sends an interrupt signal to the processor after receiving the request signal and informs the processor to start the DMA transmission; DMA _ ACK is a reply to the request signal indicating that DMA transfer has started; DMA _ DONE indicates DMA transfer completion.
The design idea of the LIO interface with the DMA function is expanded by utilizing a NAND controller or a PCIE controller integrated by a processor through a NAND bus or a PCIE bus.
The invention uses FPGA to expand a design method of LIO interface with DMA function through NAND bus.
The LIO DMA transmission design method provided by the invention solves the problem that the LIO integrated by the processor cannot carry out DMA transmission, not only improves the speed of the processor and external equipment for transmitting data, but also reduces the load of the processor when the data is transmitted.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A method for designing an LIO with DMA function, the method comprising:
designing a FLASH simulator, wherein the FLASH simulator comprises: the command analysis and control module is used for analyzing the command sent by the bus and performing corresponding processing and control according to the command; the address mapping module is used for converting the FLASH address received from the command analysis and control module into an external equipment address and sending the external equipment address to the receiving and sending control module; the receiving and transmitting control module is used for writing data into the transmitting cache and reading data from the receiving cache;
designing a receiving cache and a sending cache, wherein the receiving cache and the sending cache are used for matching transmission lines between a controller and a FLASH simulator and the transmission speed of an LIO bus, and data stored in the receiving cache and the sending cache are composed of addresses and data;
designing an LIO control module, wherein the LIO control module is used for realizing an LIO read-write time sequence;
the DMA control module is designed and used for providing an external control interface for DMA transmission.
2. The method of claim 1, wherein the command parsing and control module is configured to parse a command sent from the bus, and if the command parsing and control module parses the command as a write data command, send the address to the address mapping module and send the data to the transceiving control module; if the analyzed data is the data reading command, the address is sent to the address mapping module, and the data is read from the transceiving control module.
3. The method of claim 1, wherein the address and data of the cache are written by the transceiving control module and read by the LIO control module; the address of the receiving buffer is written in by the receiving and sending control module and read out by the LIO control module, and the data is written in by the LIO control module and then read out by the receiving and sending control module.
4. The method as claimed in claim 1, wherein the LIO control module is configured to implement an LIO read/write sequence, and comprises: sending the address and data read from the send cache onto the LIO bus; the LIO bus transmits the address read from the receive buffer and writes the read data to the receive buffer.
5. The method of claim 1, wherein the DMA control module provides an external control interface for DMA transfer, comprising: a DMA _ REQ interface, a DMA _ ACK interface and a DMA _ DONE interface; the DMA _ REQ is a request signal of an external device, and the DMA control module sends an interrupt signal to the processor after receiving the request signal and informs the processor to start DMA transmission; DMA _ ACK is a reply indication to the request signal indicating that DMA transfer has started; DMA _ DONE indicates DMA transfer completion.
6. The design method of an LIO with DMA function as claimed in claim 1, wherein the processor is a NAND controller or a PCIE controller, and the LIO interface is extended through a NAND bus or a PCIE bus.
7. An LIO interface device with DMA functionality, the device comprising:
the FLASH simulator comprises: the command analysis and control module is used for analyzing the command sent by the bus and performing corresponding processing and control according to the command; the address mapping module is used for converting the FLASH address received from the command analysis and control module into an external equipment address and sending the external equipment address to the receiving and sending control module; the receiving and transmitting control module is used for writing data into the transmitting cache and reading data from the receiving cache;
the receiving and sending caches are used for matching transmission speed of a transmission line and an LIO bus between the controller and the FLASH simulator, and data stored in the receiving and sending caches consist of addresses and data;
the LIO control module is used for realizing an LIO read-write time sequence;
and the DMA control module is used for providing an external control interface for DMA transmission.
8. The LIO interface apparatus having DMA capability of claim 7, wherein the command parsing and control module is configured to parse a command sent from the bus, and if the command parsing and control module parses the command as a write data command, send the address to the address mapping module and send the data to the transceiving control module; if the analyzed data is the data reading command, the address is sent to the address mapping module, and the data is read from the transceiving control module.
9. The LIO interface apparatus with DMA capability of claim 7, wherein the cached address and data are written by the transceiving control module and read by the LIO control module; the address of the receiving buffer is written in by the receiving and sending control module and read out by the LIO control module, and the data is written in by the LIO control module and then read out by the receiving and sending control module.
10. The LIO interface device with DMA function of claim 7, wherein the external control interface for providing DMA transfer by the DMA control module comprises: a DMA _ REQ interface, a DMA _ ACK interface and a DMA _ DONE interface; the DMA _ REQ is a request signal of an external device, and the DMA control module sends an interrupt signal to the processor after receiving the request signal and informs the processor to start DMA transmission; DMA _ ACK is a reply indication to the request signal indicating that DMA transfer has started; DMA _ DONE indicates DMA transfer completion.
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| CN111581136A (en) * | 2020-05-08 | 2020-08-25 | 上海琪埔维半导体有限公司 | DMA controller and implementation method thereof |
| CN111666237A (en) * | 2020-06-08 | 2020-09-15 | 王斌 | DMA controller with cache management function |
| CN114267404A (en) * | 2022-03-03 | 2022-04-01 | 深圳佰维存储科技股份有限公司 | eMMC test method, device, readable storage medium and electronic equipment |
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