CN110928816B

CN110928816B - On-chip configurable interrupt control system circuit

Info

Publication number: CN110928816B
Application number: CN201911033514.6A
Authority: CN
Inventors: 张永波; 张奇荣; 车德亮; 张龙
Original assignee: Beijing Microelectronic Technology Institute; Mxtronics Corp
Current assignee: Beijing Microelectronic Technology Institute; Mxtronics Corp
Priority date: 2019-10-28
Filing date: 2019-10-28
Publication date: 2021-06-08
Anticipated expiration: 2039-10-28
Also published as: CN110928816A

Abstract

The invention relates to a configurable interrupt control system circuit on a chip, which comprises an interrupt source module, a clock reset module, a control register, N interrupt state processing modules, an interrupt source configuration module, a priority encoder, a self-clearing signal generating logic of a suspension register and an interrupt vector address generator, wherein the interrupt source module is connected with the clock reset module; n is more than or equal to 2; the invention can repeatedly utilize the system on chip aiming at different interrupt source requirements, does not need to be redesigned, only needs to carry out register configuration through software, is freely cut down, has high circuit reusability of the interrupt control system, and reduces the problems of circuit redesign resource waste and circuit function reliability.

Description

On-chip configurable interrupt control system circuit

Technical Field

The invention belongs to the technical field of computers, relates to a high-performance processor, a Digital Signal Processor (DSP) and integrated circuit design and manufacture, and particularly relates to an implementation method of an on-chip configurable interrupt control system circuit.

Background

Interrupt control systems are important functional logic in high performance processors, digital signal processors, and various types of chips. Configurable interrupt control system circuits that can be adapted to different on-chip processor interrupt requirements are currently reported in the literature.

The circuit of the interrupt control system with good design performance needs to meet the following requirements: the circuit design of the disclosed interrupt control system is rarely reported, the principle is mainly explained in a processor, most of the traditional interrupt system designs different interrupt systems according to different processors, and because the structures and software instructions of the different processors are not completely the same, the interrupt systems also adopt different designs, so that the great waste of design resources is brought, and meanwhile, the circuit of the re-logic design is realized on a chip, and the uncertainty of functions can also be brought; compared with the prior art that the area of a time sequence unit of a traditional interrupt control system circuit is larger by adopting a trigger structure design, the circuit designed based on the trigger has the defect of larger area for the application in the field of the system on a chip requiring microminiaturization.

Disclosure of Invention

The technical problem solved by the invention is as follows: the on-chip configurable interrupt control system circuit is provided for solving the problems of complex design structure, large area, low reusability and the like of the traditional on-chip interrupt control system.

The technical scheme of the invention is as follows: an on-chip configurable interrupt control system circuit, comprising: the system comprises an interrupt source module, a clock reset module, a control register, N interrupt state processing modules, an interrupt source configuration module, a priority encoder, a self-clearing signal generating logic of a suspension register and an interrupt vector address generator; n is more than or equal to 2;

the clock reset module generates a system working clock and a global reset signal, sends the global reset signal to the control register, and respectively sends the system working clock and the global reset signal to each interrupt state processing module;

the control register receives and stores control information from the outside after receiving the global reset signal, and sends the control information to each interrupt state processing module and the interrupt vector address to generate control information;

the interrupt source module is used for respectively sending the N pieces of interrupt source information to the N pieces of interrupt state processing modules; configuring interrupt sources with corresponding levels according to requirements, sending corresponding level control information to an interrupt source configuration module, and triggering N pieces of interrupt source information to send N interrupt request signals according to the interrupt requirements of an external application system;

each interrupt state processing module completes initialization under the control of a system working clock and a global reset signal, generates an interrupt signal to the interrupt source configuration module according to the received interrupt source information sent by the interrupt source module, writes an interrupt request signal of the interrupt source information sent by an external system to a data bus or the interrupt source module into an internal register of the interrupt state processing module according to the control information sent by the control register, and sends the interrupt signal stored in the internal register of the interrupt state processing module to the data bus for the external system to call according to the control information; completing self-clearing of the state of an internal register according to the received interrupt self-clearing information;

the interrupt source configuration module is used for gating or shielding the received interrupt signals sent by the N interrupt state processing modules according to the received stage control information and then outputting the interrupt signals to the priority encoder;

the priority encoder generates an interrupt state flag signal and an N-bit interrupt signal after the received interrupt signals are subjected to priority arrangement, outputs the N-bit interrupt signal to a self-clearing signal generation logic of a suspension register and an interrupt vector address generator, and sends the interrupt state flag signal to an external system for informing the external system that the interrupt control system is executing an interrupt process;

the self-clearing signal generating logic of the suspension register generates N-bit interrupt self-clearing information through logic processing after receiving the N-bit interrupt signal sent by the priority encoder, and correspondingly sends the N-bit interrupt self-clearing information to the interrupt state processing module;

the interrupt vector address generator receives the N-bit interrupt signal sent by the priority encoder, generates interrupt vector address data under the control of the control information sent by the control register, and sends the interrupt vector address data to the data bus, the external system starts the interrupt execution process of the external system according to the received interrupt state flag signal, and takes the data sent to the data bus by the interrupt vector address data, and the data is used as the entry address of the interrupt service program of the external system program.

Preferably, the interrupt source module configures the stage control information through the interrupt source configuration register; the interrupt source configuration register is an N-bit register, and each bit corresponds to one interrupt state processing module by setting a control signal ctrl (i is 0 to N-1): when ctrl is 1, indicating to select the interrupt state processing module corresponding to the register bit, and when ctrl is 0, abandoning the interrupt state processing module; and according to the required interrupt source number requirement, making the ctrl i of the corresponding digit equal to 1 to obtain the final stage control information.

Preferably, the final stage number control information is obtained by setting ctrl of the corresponding number of bits to 1 in the order of ctrl, starting with i equal to 0, according to the required number of interrupt sources.

Preferably, the interrupt state processing module comprises a jump detector, an interrupt suspension register, an interrupt mask register, a register data read-write module, and an interrupt signal output and mask prohibition control module.

The jump detector judges each bit of received interrupt source information, if the interrupt source information jumps from low to high, the jump detector outputs an interrupt request signal to an interrupt suspension register, and the interrupt suspension register returns a jump detection zero clearing signal to the jump detector after receiving the interrupt request signal for resetting the state of the jump detector;

the interrupt suspension register writes the interrupt request signal or the software interrupt request signal data acquired from the data bus into the interrupt suspension register according to the control information sent by the control register;

the interrupt mask register is used for requesting the mask enable signal data to be written in from the software interrupt acquired by the data bus according to the control information sent by the control register;

in order to adapt to the application of an external system and the structural reliability, the writing and reading control signals of the interrupt shielding register adopt a dual redundancy design;

under the control of the control information sent by the control register, reading out interrupt signal data and interrupt mask enabling signal data from the interrupt suspension register and the interrupt mask register, and sending the interrupt signal data and the interrupt mask enabling signal data to the register data reading module and the interrupt signal output and mask prohibition control module;

under the control of control information sent by the control register, the register data reading module outputs received interrupt signal data and interrupt shielding enabling signal data to a data bus, and an external system accesses the data bus and is used for judging the states of the interrupt shielding register and the interrupt suspension register; the interrupt signal output and shielding prohibition control module judges whether shielding is effective or not according to the data state of the interrupt shielding enabling signal of the interrupt shielding register, if the data value is '0', the interrupt shielding state is effective, the interrupt state processing module outputs an invalid interrupt signal, otherwise, the interrupt signal output and shielding prohibition control module outputs the valid and invalid interrupt signals to the interrupt source configuration module;

and after the priority encoder generates the interrupt state flag signal and the N-bit interrupt signal, the interrupt suspension register is self-cleared according to the received interrupt self-clearing information state.

Preferably, the interrupt pending register can receive hardware interrupt source information and can also be written in by software, and the interrupt pending register can be configured into 1 to 8 bits according to requirements.

Preferably, the interrupt mask register can only be written in by software, if the state of the register is set to 1, it indicates that the interrupt source of the bit is allowed to trigger interrupt, if the position 0 indicates that the interrupt source corresponding to the bit is prohibited to trigger interrupt, the interrupt request is invalid, and the interrupt pending register can be configured to 1 to 8 bits according to requirements.

Preferably, the interrupt mask register and the interrupt pending register can be read by software, the register data read-write module in the system can read a data bus according to a control signal of the control register, the data bus is 8 bits, and the interrupt signal output and mask prohibition control module can output an interrupt signal according to an interrupt state signal output enable information state of the control register.

Preferably, the control information includes interrupt mask register write enable information, interrupt mask register read enable information, interrupt pending register software write enable information, interrupt pending register hardware write enable information, interrupt pending register read enable information, interrupt status signal output enable information, and interrupt vector address generation control information.

Preferably, the control register is at least a 7-bit register, and the 9-bit control register is flexibly configured according to an applied on-chip environment, so as to ensure that the interrupt control system circuit can be used in different on-chip processor systems, and each bit of the interrupt control system circuit is defined as follows:

one bit is set as the software write enable pending _ soft _ wr of the start interrupt pending register, when the pending _ soft _ wr is equal to 1, the external system writes an interrupt request signal into the interrupt pending register through a data bus, and when the pending _ soft _ wr is equal to 0, the software write operation is invalid;

one bit is set as hardware write enable pending _ hd _ wr of the start-up interrupt pending register, when pending _ hd _ wr is equal to 1, an interrupt request signal sent by the interrupt state processing module can write the interrupt pending register, and when pending _ hd _ wr is equal to 0, the hardware write operation is invalid;

a bit is set to enable the interrupt mask register write enable mask _ wr _ ctrl1, when mask _ wr _ ctrl1 is 1, the external system can write the interrupt mask enable signal into the interrupt mask register through the data bus, when mask _ wr _ ctrl1 is 0, the write operation is disabled;

a bit is set to enable the interrupt mask register read _ mask _ reg1, when read _ mask _ reg1 is equal to 1, the external system can read the interrupt mask enable signal from the interrupt mask register through the data bus, and when read _ mask _ reg1 is equal to 0, the read operation is invalid;

one bit is set to start the interrupt pending register read _ pending _ reg, when the read _ pending _ reg is equal to 1, the external system reads an interrupt request signal from the interrupt pending register through a data bus, and when the read _ pending _ reg is equal to 0, the read operation is invalid;

a bit is set to enable the interrupt status signal output enable forbid _ ctrl, which is generated by an external system according to requirements, and when forbid _ ctrl is 1, the interrupt signal output is allowed, and when forbid _ ctrl is 0, the interrupt signal output is invalid;

one bit is set as start interrupt vector address generation enable int _ generator _ ctrl, when int _ generator _ ctrl is 1, the interrupt vector address generator outputs 3-bit interrupt vector to the data bus, when int _ generator _ ctrl is 0, the interrupt vector is not output.

Preferably, according to the application requirement and reliability requirement of the external system, a two-bit redundancy backup design is added in the control register, wherein one bit is set to start the interrupt mask register write enable mask _ wr _ ctrl2, when mask _ wr _ ctrl2 is 1, the external system can write an interrupt mask enable signal into the interrupt mask register through a data bus, and when mask _ wr _ ctrl2 is 0, the read operation is invalid;

a bit is set to enable the interrupt mask register read _ mask _ reg2, the external system may read the interrupt mask enable signal from the interrupt mask register via the data bus when read _ mask _ reg2 is 1, and the read operation is disabled when read _ mask _ reg2 is 0.

Compared with the prior art, the invention has the beneficial effects that:

(1) the invention provides a method for realizing an on-chip configurable interrupt control system circuit aiming at the problems of complex design structure, large area, weak reusability and the like of the traditional on-chip interrupt control system, the interrupt system circuit adopts an interrupt source configuration register to select and configure an interrupt source module, adopts a control register to control the interrupt state processing process, can be repeatedly used aiming at the on-chip systems with different interrupt source requirements, does not need to be redesigned, only needs software to configure the register, is freely cut down, has high reusability of the interrupt control system circuit, and reduces the problems of circuit redesign resource waste and circuit function reliability; the circuit structure adopts the design of LATCH LATCH, 12 MOS tubes are needed for realizing a D trigger in the design of an integrated circuit at a gate level, 6 MOS tubes are needed for realizing a LATCH, logic resources consumed by the LATCH LATCH relative to the D trigger are less, the integration level of the LATCH is higher, the number of transistors on a chip is greatly reduced, and therefore the area is reduced. The circuit structure of the interrupt control system can be repeatedly applied to chips of a high-performance processor, a network processor and a signal processor, and has high reliability.

(2) The on-chip configurable interrupt control system circuit adopts the control register and can flexibly configure the control information of the 9-bit control register according to the on-chip system, thereby further ensuring that the interrupt system circuit can be used in different on-chip processor systems, and simultaneously reducing the design cost and having good reusability by the reusable interrupt system circuit;

(3) the on-chip configurable interrupt control system circuit of the invention can be applied to a microsatellite integrated electronic system, is an important component of an electronic system coprocessor, because the micro satellite integrated electronic system processor can process a plurality of loads, power supplies, attitude and orbit control and other external states, and the required interrupt requests are different, the interrupt system can be flexibly configured according to the requirements of processors with different functional requirements for processing the number of interrupt sources, the control register is flexibly configured according to different on-chip application environments, is applicable to different on-chip systems, since the interrupt system is designed as a configurable circuit, hardware IP is formed, no hardware cut is required, the circuit design of the interrupt control system can meet the requirements of a micro satellite integrated electronic system processor.

Drawings

FIG. 1 is a circuit diagram of an on-chip configurable interrupt control system according to the present invention;

FIG. 2 is a block diagram of an interrupt status handling module according to the present invention;

FIG. 3 is a block diagram of a transition detector of the present invention;

FIG. 4 is a block diagram of an interrupt pending register of the present invention;

FIG. 5 is a block diagram of an interrupt mask register of the present invention;

FIG. 6 is a block diagram of a register data read module according to the present invention;

FIG. 7 is a block diagram of an interrupt signal output and mask disable control module according to the present invention;

FIG. 8 is a block diagram of an interrupt source configuration module of the present invention;

FIG. 9 is a block diagram of a priority encoder of the present invention;

FIG. 10 is a block diagram of the suspension register self-zeroing signal generation logic of the present invention;

FIG. 11 is a block diagram of an interrupt vector address generator according to the present invention;

fig. 12 is a block diagram of a clock reset module of the present invention.

Detailed Description

The invention is further illustrated by the following examples.

The on-chip configurable interrupt control system circuit can be applied to a micro satellite integrated electronic system and is an important component of an electronic system coprocessor, because the satellite integrated electronic system processor has more external states such as processable load, power supply, attitude and orbit control and the like, and the required interrupt requests are different, the interrupt system can be flexibly configured according to the different requirements of processors with different functional requirements on the number of interrupt sources, control registers are flexibly configured according to different on-chip application environments and can be suitable for different on-chip systems.

The interrupt control system circuit is configurable via the interrupt source configuration register to handle interrupt systems of different numbers of interrupt sources, for example: the on-chip processor only needs to process the interrupt system of 5 interrupt sources, and then the system can be configured into a system which can only process 5 interrupt sources according to the interrupt source configuration register, redesign is not needed, register configuration can be carried out through software, free cutting is achieved, the system can be repeatedly utilized, and the problems of redesign resource waste and circuit function reliability are reduced;

the control register can flexibly configure a 9-bit control register according to the on-chip environment of the application to ensure that the interrupt system can be used in different on-chip processor systems;

an on-chip configurable interrupt control system circuit, as shown in fig. 1, specifically includes an interrupt source module, a clock reset module, a control register, N interrupt state processing modules, an interrupt source configuration module, a priority encoder, a self-clearing signal generation logic of a suspension register, and an interrupt vector address generator.

The clock reset module is used for generating a system working clock and a global reset signal, sending the global reset signal to the control register and sending the system working clock and the global reset signal to the interrupt state processing module;

the interrupt source module comprises transmission interrupt source information and an interrupt source configuration register, the received interrupt source information is respectively sent to each interrupt state processing module, the interrupt source configuration register can configure 1-8 interrupt sources with any number of stages, control information of the interrupt source configuration register is sent to the interrupt source configuration module, the interrupt source configuration register flexibly configures the number requirement of the interrupt sources according to the system on chip, and N pieces of interrupt source information are triggered to send N interrupt request signals according to the interrupt requirement of an external application system.

The control register comprises 9 bits of control information, can be flexibly configured, and after receiving the global reset signal, the control register receives and stores control information from the outside, the control information comprises interrupt mask register write enable information, interrupt mask register read enable information, interrupt suspension register software write enable information, interrupt suspension register hardware write enable information, interrupt suspension register read enable information, interrupt state signal output enable information and interrupt vector address generation control information, and the interrupt state processing module is sent with the interrupt mask register write enable information, the interrupt mask register read enable information, the interrupt suspension register software write enable information, the interrupt suspension register hardware write enable information, the interrupt suspension register read enable information, the interrupt state signal output enable information and the interrupt vector address generation control information;

an interrupt state processing module for receiving the system working clock and the global reset signal sent by the clock reset module, completing the initialization of the interrupt state processing module under the control of the system working clock and the global reset signal, receiving the interrupt source information sent by the interrupt source module, receiving the interrupt self-clearing information sent by the self-clearing signal generating logic of the suspension register, receiving the interrupt mask register write enable information, the interrupt mask register read enable information, the interrupt suspension register software write enable information, the interrupt suspension register hardware write enable information, the interrupt suspension register read enable information and the interrupt state signal output enable information sent by the control register,

the data writing of the interrupt suspension register is completed under the action of the software write enable information of the interrupt suspension register, the external system writes an interrupt request signal into the interrupt suspension register through a data bus, the interrupt request signal sent by the jump detector is written into the interrupt suspension register under the action of the hardware write enable information of the interrupt suspension register,

the data writing of the interrupt mask register is completed under the action of the write enable information of the interrupt mask register, the external system writes the interrupt mask enable signal into the interrupt mask register through a data bus,

the reading of the interrupt request signal in the interrupt suspension register is completed under the action of the read enabling information of the interrupt suspension register, the output data is respectively sent to the register data reading module and the interrupt signal output and shielding prohibition control module, the reading of the interrupt shielding register is completed under the action of the read enabling information of the interrupt shielding register, the output data is respectively sent to the register data reading module and the interrupt signal output and shielding prohibition control module,

under the action of control information, the register data reading module outputs an interrupt request signal and interrupt mask enable signal data of an interrupt mask register and an interrupt suspension register to a data bus for application of an external system, under the action of the control information, the interrupt signal output and mask prohibition control module outputs an interrupt signal to the interrupt source configuration module, and meanwhile, the interrupt state processing module completes self-clearing of the state of the interrupt suspension register according to received interrupt self-clearing information;

in this example, 8 interrupt state processing modules are shared, the logic of 8 modules is the same, and the 8 modules are respectively defined as module 1, module 2, module 3, module 4, module 5, module 6, module 7 and module 8, the 8 modules respectively send interrupt information to the interrupt source configuration module and receive information control register control information, the priority order of the 8 interrupt control systems is from low to high as module 1, module 2, module 3, module 4, module 5, module 6, module 7 and module 8;

the interrupt source configuration module is used for receiving the control information of the interrupt source configuration register in the interrupt source module, determining the number of interrupt sources contained in the system according to the control information of the interrupt source configuration register, gating or shielding the 8 interrupt source information sent by the 8 interrupt state processing modules and outputting the information to the priority encoder;

the priority encoder is used for receiving 8 interrupt signals sent by the interrupt source configuration module, generating an interrupt state flag signal and an 8-bit interrupt signal after priority arrangement, and outputting the 8-bit interrupt signal to the self-clearing signal generation logic of the suspension register and the interrupt vector address generator;

the self-clearing signal generating logic of the suspension register generates 8-bit interrupt self-clearing information through logic processing after receiving the 8-bit interrupt signal sent by the priority encoder, and respectively and correspondingly sends the 8-bit interrupt self-clearing information to 8 interrupt state processing modules;

and the interrupt vector address generator receives the 8-bit interrupt signal sent by the priority encoder, generates interrupt vector address data through an interrupt vector address generation logic under the control of interrupt vector address generation control information sent by the control register, sends the interrupt vector address data to a data bus, and the external system uses the interrupt vector address information on the data bus as an entry address of a system interrupt service program to execute interrupt operation.

As shown in fig. 2, the interrupt state processing module structure of the present invention: the interrupt state processing module receives an interrupt request signal sent by an external interrupt source module and inputs the interrupt request signal to the jump detector as an interrupt signal, the jump detector outputs the interrupt request signal to the interrupt suspension register through logic analysis and processing, the interrupt suspension register stores the interrupt request signal and outputs the interrupt request signal to the interrupt signal output and shielding prohibition control module and the register data reading module through control signal control, and the interrupt suspension register can also write the interrupt request signal through software; the interrupt mask register can write an interrupt mask enable signal through software; the data of the register is output to the interrupt signal output and shielding prohibition control module and the register data reading module through the control signal; in the interrupt signal output and shielding prohibition control module, when the output signal state of the interrupt shielding register is shielding effectiveness, the interrupt signal output and shielding prohibition control module outputs an interrupt signal as an ineffective interrupt signal, otherwise, the interrupt signal is output effectiveness; under the control of the control signal, the register data reading module can output an interrupt request signal for interrupting the suspension register and an interrupt mask enable signal of the interrupt mask register to the data bus for calling by an external system.

As shown in fig. 3, the jump detector of the present invention is characterized by: a transition detector, comprising: input signals interrupt _ source, clka, clkb, int _ pendinggreg _ out, output signal pendinggreg _ in, latches LATCH _1, LATCH _2, LATCH _3, LATCH _4, NOR gate NOR3_1, OR gate OR2_ 1; the jump detector judges the received hardware interrupt source information, if the output interrupt source information jumps from low to high, the jump detector outputs an interrupt request signal to the interrupt suspension register, and the interrupt source is indicated to have an interrupt request; the interrupt source signal interrupt _ source is input to the LATCH _1, the QN terminal of the LATCH _1 outputs a signal to the LATCH _2 under the control of the clock signal clkb, the LATCH _2 outputs a signal from the QN terminal to the LATCH _3 under the control of the clock signal clka, the QN terminal of the LATCH _1 and the QN terminal output signal and the input signal int _ pendinggreg _ out of the LATCH _3 are output to the OR gate OR2_1 and the data D terminal of the LATCH _4 through the NOR gate NOR3_1, the NOR3_1 output and the input signal int _ pendinggreg _ out are output to the clock terminal of the LATCH _4 through the OR gate OR2_1, and the Q terminal output signal pendinggreg _ in of the LATCH _ 4. The input signal int _ pendingreg _ out is a to _ transition _ dt output signal in the interrupt pending register, the system resets and outputs 0 state, clka and clkb are frequency division clock signals with opposite phases, and the output signal pendingreg _ in outputs an interrupt request signal with a clka clock state cycle width to the interrupt pending register when the interrupt source signal interrupt _ source jumps from low level to high level.

As shown in fig. 4, the interrupt pending register structure of the present invention is characterized by: an interrupt pending register comprising: input signals pending _ soft _ wr, s _ clr, rst, pending _ hd _ wr, fr _ transition _ dt, data, output signals to _ transition _ dt, pending _ reg _ out, inverters INV _1, INV _2, INV _3, AND gate 2_1, AND2_2, NAND gate NAND2_1, NOR2_1, NOR2_2, OR gate OR3_1, LATCH _ 5; the interrupt suspension register can receive hardware interrupt source information and can be written in by software, and the interrupt suspension register can be configured into 1-8 bits according to requirements in the system; when the CPU detects that 8 interrupt sources jump from low to high, the interrupt suspension register sets the corresponding position of the register, namely, the interrupt is suspended. The suspension means that an interrupt application is available but a response state is not available, once the suspended interrupt is responded, an interrupt vector entering an interrupt service program is obtained, a corresponding bit is cleared, the interrupt suspension register can be read and written, the suspended interrupt can be removed by clearing the corresponding bit, even if the suspended interrupt is forbidden, the suspension register can be set, and the interrupt suspension register can be read to determine which interrupt is suspended; the write interrupt request signal is output through an input signal data through an inverter INV _1, the INV _1 outputs an interrupt suspension register software write signal pending _ soft _ wr from the control register to NOR2_1 through an AND2_1, the NOR2_1 outputs a signal to a LATCH _5 input D terminal, a self-clearing signal s _ clr from a suspension register self-clearing signal generating logic output is output through an inverter INV _2, an INV _2 output signal AND a reset signal rst are output through a NAND gate 2_1, an interrupt suspension register hardware write enable signal pending _ hd _ wr sent from the control register receives control write enable information, a transition detector output pendreg _ in outputs a signal to an input terminal fr _ transition _ dt of the interrupt suspension register, pending _ hd _ wr AND fr _ transition _ dt output through an AND gate 2_2, AND an AND2_2 output signal AND a Q output signal of the LATCH ch 5 output signal are output through a NOR gate 592 _ pending _ reg _ 592, the output signal pending _ reg _ out is an interrupt signal output port of the interrupt suspension register, the NOR2_2 output signal is output through an inverter INV _3, the INV _3 output signal is output to the clock terminal of the LATCH _5 through an OR gate OR3_1 together with the NAND2_1 output signal and pending _ soft _ wr, and the output terminal D of the LATCH _5 outputs a signal to _ transition _ dt; the interrupt pending register may be accessed by two means, software and hardware, the access and write process by software is that an input signal pending _ soft _ wr receives a software write enable signal sent by a control register, the signal is valid when the signal is high, a written interrupt request signal writes a data value to be 1 by a data bus input signal data, a signal value is output to be 1 at an output end D of a LATCH _5, the output signal at the pending _ reg _ out terminal is 0, when the state of the input signal pending _ soft _ wr is 0, the output terminal D of the LATCH _5 continues to LATCH the signal value to be 1, the output end pending _ reg _ out keeps the output signal value to be 0 continuously, and the data stored in the interrupt pending register is represented to be in a triggerable interrupt state when the pending register outputs the signal 0, so that the functions of writing software into the interrupt pending register and latching are completed; the writing process of accessing the register in a hardware mode is that when an interrupt source signal has an interrupt request, an output end pendinggreg _ in of a jump detector outputs a high-pulse interrupt request signal with a clka clock cycle width to an input end fr _ transition _ dt of an interrupt suspension register, meanwhile, the pendingding _ hd _ wr receives a hardware write enable signal sent by a control register, and the output end pendingreg _ out outputs a signal value of 0, and the interrupt is effective through hardware; the state of a self-clearing signal generated by logic output of the self-clearing signal s _ clr receiving the self-clearing signal of the suspension register is 1, clearing is effective, and when the s _ clr receiving the 1 state signal, the value of a pending _ reg _ out output signal is 1, the register is indicated to be cleared.

As shown in FIG. 5, the interrupt mask register architecture of the present invention is characterized by: an interrupt mask register comprising: input signals clkc, rst, mask _ wr _ ctrl1, mask _ wr _ ctrl2, data, an output signal mask _ reg _ out, a NOR gate NOR2_3, NOR2_4, inverters INV _4, INV _5, INV _6, an AND gate AND2_3, a NAND gate 3_1, a LATCH LATCH _6 AND a multiplexer MUX _1, wherein when an enable end C of the multiplexer MUX _1 is in a0 state, the output end Y gates a D0 channel, otherwise, when the C is in a1 state, the output end Y gates a D1 channel; clkc is a frequency division clock signal output by the clock reset module, rst is a global reset signal output by the clock reset module, mask _ wr _ ctrl1 and mask _ wr _ ctrl2 are write enable signals of an interrupt mask register output by a control register, data is a data bus output data bit of 1bit number, and mask _ reg _ out is an interrupt mask register output signal, the interrupt mask register can only be written in by software, if the state of the register is set to 1, the interrupt source at the bit is allowed to trigger interrupt, if the position 0 indicates that the interrupt source corresponding to the bit is forbidden to trigger interrupt, the interrupt request is invalid, and an interrupt suspension register in the system can be configured into 1 to 8 bits according to requirements; the interrupt mask register is used for controlling whether a certain interrupt source is allowed to carry out interrupt request, when a certain bit of the register is 1, the corresponding interrupt source is allowed to carry out interrupt request, otherwise, the corresponding interrupt source is forbidden, even if a certain interrupt is masked, the interrupt source can be suspended; thus, it is often desirable to clear the corresponding overhang bit before removing the mask for an interrupt to avoid causing an undesirable interrupt; once the interrupt service program is entered, at least one instruction can be executed to respond to another interrupt with higher priority; the input signals mask _ wr _ ctrl1 AND mask _ wr _ ctrl2 are output through NOR gate NOR2_3, the clock signal clkc AND the reset signal rst AND NOR gate NOR2_3 output signal are output through NAND gate NAND3_1 to the clock terminal of LATCH _6, the output terminal Q of LATCH _6 AND the clock signal clkc are output through AND gate AND2_3, the AND2_3 output is connected to the D data1 terminal of multiplexer MUX _1, the input data is connected to the D0 terminal of multiplexer MUX _1, the output end of the NOR2_3 is connected with the C end of the multiplexer MUX _1, the output end Y of the multiplexer MUX _1 is output through an inverter INV _5, the input reset signal rst is output through an inverter INV _6, the output end of the inverter INV _5 and the output end of the inverter INV _6 are output to the input end D of the LATCH LATCH _6 through a NOR gate NOR2_4, and the output end QN of the LATCH LATCH _6 is connected with an output signal mask _ reg _ out; the access writing process of the interrupt mask register is that after the input signal mask _ wr _ ctrl1 or mask _ wr _ ctrl2 receives the control information sent by the control register, when any state value of the mask _ wr _ ctrl1 and the mask _ wr _ ctrl2 is 1, the interrupt mask register output signal mask _ reg _ out outputs the inverse value of the received interrupt mask enable signal data, namely when the data input is 1, the output signal mask _ reg _ out output value is 0, the characterization interrupt mask register allows interrupt execution, otherwise, the interrupt request signal is masked.

As shown in fig. 6, the register data reading module of the present invention has the structural features: a register data read module comprising: inputting signals of mask _ reg _ data, pending _ reg _ data, read _ mask _ reg1, read _ mask _ reg2, read _ pending _ reg and outputting signals data; OR gate OR2_2, inverters INV _16 and INV _17, and tri-state buffers TRIBUF _1 and TRIBUF _ 2; the interrupt mask register and the interrupt suspension register can be read by software, and the interrupt signal output and mask prohibition control module can output an interrupt signal according to the interrupt state signal output enable information state of the control register; the method comprises the steps that input signals read _ mask _ reg1 and read _ mask _ reg2 receive an interrupt mask register read enabling signal sent by a control register, read _ pending _ reg receives an interrupt suspension register read enabling signal sent by the control register, mask _ reg _ data receives an interrupt mask enabling signal sent by an output end of the interrupt mask register mask _ reg _ out and pending _ reg _ data receives an interrupt request signal sent by an output end of the interrupt suspension register pending _ reg _ out, the output signals are 1bit data, and the read interrupt request signal of the interrupt mask register and the read interrupt suspension register data output the interrupt mask enabling signal to a data bus; the read _ mask _ reg1 and the read _ mask _ reg2 are output to the control terminal ENB of the tri-state buffer TRIBUF _1 through an OR gate 2_2, the read _ pending _ reg is input to the control terminal ENB of the tri-state buffer TRIBUF _2, the mask _ reg _ data is output to the input terminal of the tri-state buffer TRIBUF _1 through an inverter INV _16, the pending _ reg _ data is output to the input terminal of the tri-state buffer TRIBUF _2 through an inverter INV _17, and the tri-state buffers TRIBUF _1 and TRIBUF _2 are output to the data; the interrupt mask enable signal of the interrupt mask register is read out to the data bus when read _ mask _ reg1 is set to 1 or read _ mask _ reg2 is set to 1, and the interrupt pending register interrupt request signal is read out to the data bus when read _ pending _ reg is set to 1.

As shown in fig. 7, the structural features of the interrupt signal output and mask disable control module of the present invention are as follows: the interrupt signal output and mask inhibit control module includes: inputting an interrupt request signal mask _ reg _ data, an interrupt mask enable signal pending _ reg _ data, an interrupt state signal output enable forbid _ ctrl, and outputting an interrupt signal out _ data; NOR gate NOR2_5, LATCH _ 7; an input signal mask _ reg _ data receives a signal sent by an output end mask _ reg _ out of an interrupt mask register, an input signal pending _ reg _ data receives a signal sent by an output end pending _ reg _ out of an interrupt hanging register, the mask _ reg _ data and the pending _ reg _ data are output to a D end of a LATCH LATCH _7 through a NOR gate NOR2_5, an input signal forbid _ ctrl receives an enable signal sent by a control register, the forbid _ ctrl is connected with a clock end of the LATCH LATCH _7, and an output end Q of the LATCH LATCH _7 is connected with an output signal out _ data; when the received signal of mask _ reg _ data is 1, the representation mask register masks the interrupt request of the suspension register, when the received signal of mask _ reg _ data is 0, the representation allows the interrupt request of the suspension register to be interrupted, when the received signal of pending _ reg _ data is 0, the representation of the suspension register has the interrupt request, otherwise, when the received signal of pending _ reg _ data is 1, the representation indicates that the suspension register has no interrupt request, the signal forbid _ ctrl is an interrupt state signal output enable signal, when the signal is set to 1, the representation allows the interrupt request to continue to be transmitted, the interrupt request valid interrupt signal is output from out _ data, otherwise, the valid interrupt request signal transmission is prohibited no matter what states the pending _ reg _ data and the mask _ reg _ data are in.

As shown in fig. 8, the interrupt source configuration module structure feature of the present invention: an interrupt source configuration module comprising: input signals ctrl0, ctrl1, ctrl2, ctrl3, int _ state _ mk3_ in, output signals int _ state _ mk3, int _ state _ m 3, AND3, int _ state _3, AND 3; the input signals int _ state _ mk1_ in, int _ state _ mk2_ in, int _ state _ mk3_ in, int _ state _ mk4_ in, int _ state _ mk5_ in, int _ state _ mk6_ in, int _ state _ mk7_ in, and int _ state _ mk8_ in receive the interrupt signals output by the module 1, the module 2, the module 3, the module 4, the module 5, the module 6, the module 7, and the module 8, ctrl0, ctrl1, ctrl2, ctrl3, ctrl4, ctrl5, ctrl6, ctrl7, respectively, receive the control information transmitted from the interrupt configuration source register in the interrupt source module; ctrl0 AND int _ state _ mk1_ in output int _ state _ mk1 signal through AND gate 2_4, ctrl1 AND int _ state _ mk1_ in output int _ state _ mk1 signal through AND gate 1_ 5, ctrl1 AND int _ state _ mk1_ in output int _ state _ mk1 signal through AND gate 1_ 6, ctrl1 AND int _ state _ mk1_ in output int _ state _ mk1 signal through AND gate 1_ 7, ctrl1 AND int _ state _ mk1_ in output int _ state _ mk1 signal through AND gate 1_ 8, ctrl1 AND int _ state _ mk1_ in output int _ state _ mk1 signal through AND gate 1_ 9, AND int _ state _ mk _ m 1_ in AND gate 1_ state _ m _ n output AND gate 1_ state _ m _ k _ m _ k1 signal through AND gate 1_ m _ n to determine which AND gate 1 signal AND gate 1_ m _ k _ m _ n output AND gate 1_ m _ n output signal AND gate 1_ 72 AND gate 1_ m.

As shown in fig. 9, the priority encoder structure of the present invention is characterized in that: a priority encoder, comprising: the input signals int _ state _ mk1, int _ state _ mk2, int _ state _ mk3, int _ state _ mk4, int _ state _ mk5, int _ state _ mk6, int _ state _ mk7, int _ state _ mk8, the output signals int _ state _ sign _ out, int _ state _ mk1_ out, int _ state _ 2_ out, int _ state mk3_ out, int _ state _ 4_ out, int _ state _ k5_ out, int _ state _ mk6_ out, int _ state _ mk7_ out, int _ state _ mk8_ out, inverters INV _7, INV _8, INV _9, INV _10, INV _11, INV _12, INV _13, INV _14, INV _15 _ NOR 72, NOR _8, NOR _ 72, NOR _8, NOR _; the input signals int _ state _ mk1, and int _ state _ mk1 respectively receive the output signals int _ state _ mk1, int _ state _ mk _ state _ m 1, int _ state _ m _1, int _ state _ m _ k _ m _ k _ m _ k _ m _ k _ m _ k _1, int _ state _ m _ k _ m _ k _ m _, int _ statemk2_ out, int _ statemk3_ out, int _ statemk4_ out, int _ statemk5_ out, int _ statemk6_ out, int _ statemk7_ out, int _ statemk8_ out, and interrupt state flag signal int _ state _ sign _ out; the input signals int _ state _ mk1, int _ state _ mk2, int _ state _ mk3, int _ state _ mk4 are output to the OR5_1 through the OR4_1, the OR4_1 outputs the int _ state _ mk4, the int _ state _ mk4 output through the OR4_1, the signal int _ state _ sign _ out is output through the inverter _7 INV, the INV _7 output and the int _ 72 _1 output of the int _ state _ mk4, the int _ state _ NOR4_1, the int _ state _ mk4_ NOR 72 _ output through the inverter 4 INV _ m _ NOR 72, the int _ state _ m 4, the int _ state _ NOR 72, the int _ state _ m _ k4, the int _ NOR 72, the int _ state _ m _ n _ flag signal 72, the int _ out output through the OR 72 _ state _ NOR4, the int _ state _ NOR 72 _ state _ 72 _ NOR 72, the int _ state _ NOR 72, the int _ state _ NOR 72, the int _ NOR _ state _ NOR _ 4_ NOR _4, the int _ state _ NOR, int _ state _ mk4 and int _ state _ mk5 output interrupt signals int _ state _ 2_ out through NOR gates NOR5_2, int _ state _ mk7 and int _ state _ mk8 are output through NOR gates NOR2_6, int _ state _ mk3 is output through inverter INV 9, INV _9 output signal and NOR gate NOR2_6 output signal and signals int _ state _ mk4, int _ state _ mk5 and int _ state _ mk6 output interrupt signals int _ state 3_ out through NOR gates NOR5_3, int _ state _ mk4 is output through inverter INV _10, INV _ state _ mk5, int _ state _ mk _ INV 7, int _ state _ mk7, int _ state _ mk 4672 _ m _ out through NOR gates NOR 7_ m 7, int _ state _ m _ 7_ m _ out signal and int _ state _ m _ 7_ m _ out signal through NOR gates NOR 7_ state 7_ m 7 and 7_ m _ out7, the signal int _ state _ mk6 is output through the inverter INV _12, INV _12 output and signals int _ state _ mk7 and int _ state _ mk8 output the interrupt signal int _ state _ mk6_ out through the NOR gate NOR3_3, the signal int _ state _ mk7 output through the inverter INV _13, INV _13 output and signal int _ state _ mk8 output the interrupt signal int _ state _ mk7_ out through the NOR gate NOR2_7, the signal int _ state _ mk8 output through the inverter INV _14, the INV _14 output outputs the interrupt signal int _ state _ mk8_ out through the inverter INV _15, and the output signal priority order from high to low is: int _ statemk8_ out, int _ statemk7_ out, int _ statemk6_ out, int _ statemk5_ out, int _ statemk4_ out, int _ statemk3_ out, int _ statemk2_ out, and int _ statemk1_ out, the priority encoder arranges the transmitted interrupt requests according to the priority order, the interrupt is triggered by the priority of high priority, and the interrupt is triggered after the interrupt triggering is completed by the waiting of high priority of low priority.

As shown in fig. 10, the self-clearing signal of the suspension register of the present invention generates the logical structure characteristics: the suspension register self-clearing signal generation logic comprising: input interrupt request signals priority _ mk _ out1, priority _ mk _ out2, priority _ mk _ out3, priority _ mk _ out4, priority _ mk _ out5, priority _ mk _ out6, priority _ mk _ out7, priority _ mk _ out8, output self-clearing information sf _ clr _ out1, sf _ clr _ out2, sf _ clr _ out3, sf _ clr _ out4, sf _ clr _ out5, sf _ clr _ out6, sf _ clr _ out7, sf _ clr _ out 8; NOR gates NOR3_4, NOR3_5, NOR3_6, NOR3_7, NOR3_8, NOR3_9, NOR3_10, NOR3_11, NOR5_5, NOR5_6, NOR5_7, NOR5_8, NOR5_9, NOR5_10, NOR5_11, NOR5_ 12; the input signals priority _ mk _ out1, priority _ mk _ out2, priority _ mk _ out3, priority _ mk _ out4, priority _ mk _ out5, priority _ mk _ out6, priority _ mk _ out7, and priority _ mk _ out8 are respectively connected to the output signals int _ state k1_ out, int _ state k2_ out, int _ state k3_ out, int _ state k4_ out, int _ state 5_ out, int _ state k6_ out, int _ state 7_ out, and int _ state k8_ out of the priority encoder; the input signals priority _ mk _ out, and priority _ mk _ out are output through the NOR-gate NOR _4, the NOR-4 output signal and the priority _ mk _ out, and priority _ mk _ out are output from the clear-zero signal sf _ clr _ out through the NOR-gate NOR _5, the input signals priority _ mk _ out, and priority _ mk _ out are output through the NOR-gate NOR _5, the NOR-5 output signal and the priority _ mk _ out, priority _ mk _ out are output from the clear-zero signal sf _ clr _ out through the NOR-gate NOR _6, the input signals priority _ mk _ out, priority _ m _ out, priority _ m _ out, priority _ m _ out, and priority _ m _ out are output through the NOR _ m _5, the NOR _ m _, The priority _ mk _ out and the priority _ mk _ out are output through the NOR gate NOR _7, the NOR _7 output signal and the priority _ mk _ out, the priority _ mk _ out are output through the NOR gate NOR _8 from the clearing signal sf _ clr _ out, the input signals priority _ mk _ out, and priority _ mk _ out are output through the NOR gate NOR _8, the NOR _8 output signal and the priority _ mk _ out, and the priority _ mk _ out are output through the NOR gate NOR _9 from the clearing signal sf _ clr _ out, the input signals priority _ mk _ out, the priority _ m _ out, the priority _ m _9 from the NOR gate NOR _9 from the priority _ m _9 from the priority _ 0 _ m _8 output signals, the priority _ m _ 0 _ m _8 output through the priority _ m _ 0 _ out, the priority _ 0, The priority _ mk _ out8 is output through a NOR gate NOR3_10, the NOR3_10 output signal and the priority _ mk _ out2, the priority _ mk _ out3, the priority _ mk _ out4 and the priority _ mk _ out5 are output through a NOR gate NOR5_11 from a clear zero signal sf _ clr _ out7, the input signals priority _ mk _ out1, priority _ mk _ out6 and priority _ mk _ out7 are output through a NOR gate 3_11, the NOR3_11 output signal and the priority _ mk _ out2, priority _ mk _ out3, priority _ mk _ out4 and priority _ mk _5 are output through a NOR gate 5_12 from a suspended clear zero signal sf _ clr 8, and when an interrupt signal corresponding to a priority clear interrupt signal triggers a high interrupt occurs, the clear interrupt register is output from a clear zero signal.

As shown in FIG. 11, the interrupt vector address generator of the present invention is characterized by: an interrupt vector address generator comprising: input signals priority _ mk _ out1, priority _ mk _ out2, priority _ mk _ out3, priority _ mk _ out4, priority _ mk _ out5, priority _ mk _ out6, priority _ mk _ out7, priority _ mk _ out8, int _ generator _ ctrl, data bus signals data0, data1, data2, wherein data0 is the lowest bit zero of the bus, data1 is the first bit of the data bus, data2 is the second bit of the data bus, NOR nand gate 4_3, NOR4_4, NOR4_5, tri-state buffers TRIBUF _3, TRIBUF _4, TRIBUF _ 5; the input signals priority _ mk _ out1, priority _ mk _ out2, priority _ mk _ out3, priority _ mk _ out4, priority _ mk _ out5, priority _ mk _ out6, priority _ mk _ out7, and priority _ mk _ out8 respectively receive the output signals int _ status 1_ out, int _ status 2_ out, int _ status 3_ out, int _ status 4_ out, int _ status 5_ out, int _ status 6_ out, int _ status 7_ out, int _ status 8_ out, the input signal int _ generator _ ctrl receives the interrupt vector address sent by the control register to generate the enable signal, and the int _ generator _ ctrl outputs the three-bit interrupt vector data to the ternary bus buffer under int _ generator _ ctrl _ controller; the input signals priority _ mk _ out1, priority _ mk _ out3, priority _ mk _ out5, priority _ mk _ out7 are output through the NOR gate NOR4_3, the input signals priority _ mk _ out1, priority _ mk _ out2, priority _ mk _ out5, priority _ mk _ out6 are output through the NOR gate NOR4_4, the input signals priority _ mk _ out1, priority _ mk _ out2, priority _ mk _ out3, priority _ mk _4 are output through the NOR gate NOR 42 _5, int _ generator _ ctrl connect the enable terminals of the three-state buffers buf _3, trif _4, trif _5, the data output level is output through the NOR gate NOR 3742 _5, the data output level is output through the NOR gate NOR 27 _5, the data output level is high-data output through the NOR gate 4, the data output level 4 is output through the NOR gate 3645, the data0, data1 and data2 constitute three-bit interrupt vector address data, the interrupt vector address is generated and sent to a data bus, and the external system CPU accesses the acquired interrupt vector address data through the data bus and takes the data as an entry address of an interrupt service program to execute the interrupt program.

As shown in fig. 12, the clock reset module of the present invention has the structural features: the main clock frequency can keep consistent with the main clock frequency of the external system, the clocks clka and clkc are non-overlapped clocks, namely clka and clkc are 1/3 with the main clock frequency as the clock frequency, the duty ratios of the clocks clka and clkc are 1/3, the cycles of the clocks clka and clkc are the same but the high levels are not overlapped, the rising edge of the clock clka corresponds to the falling edge of the clock clkc, the clock clkb is the complementary clock of the clock clka, the clock period is the same as clka, the duty ratio is 2/3, the rising edge of the clock clka corresponds to the falling edge of the clock clkb, the falling edge of the clock clka corresponds to the rising edge of the clock clkb, three times of the main clock period is used as a clock state period, the reset signal rst is asynchronous reset, the rst low level is reset, the rst low level keeps valid for more than one clock state period, otherwise, the reset is invalid, the clock signals clka, clkc and clkc are used as the system working clock, the interrupt structure system can work orderly according to a fixed clock beat, and the reset signal rst can carry out global reset on the interrupt system.

TABLE 1 interrupt Source configuration register

As shown in Table 1, the interrupt source configuration register of the present invention is characterized by: the interrupt source configuration register has 8 bits, and configures and selects the interrupt systems with different numbers of interrupt sources according to the different interrupt systems required by different processors, which is defined as follows:

the first bit is set as follows: setting ctrl0 as a module 1 selection signal in the interrupt status processing module, selecting module 1 when ctrl0 is equal to 1, and discarding the module when ctrl0 is equal to 0;

the second bit is set as follows: setting ctrl1 as a module 2 selection signal in the interrupt status processing module, selecting module 2 when ctrl1 is equal to 1, and discarding the module when ctrl1 is equal to 0;

the third bit is set as follows: setting ctrl2 as a module 3 selection signal in the interrupt status processing module, selecting module 3 when ctrl2 is equal to 1, and discarding the module when ctrl2 is equal to 0;

the fourth bit is set as follows: setting ctrl3 as a module 4 selection signal in the interrupt status processing module, selecting module 4 when ctrl3 is equal to 1, and discarding the module when ctrl3 is equal to 0;

the fifth bit is set as follows: setting ctrl4 as a module 5 selection signal in the interrupt status processing module, selecting module 5 when ctrl4 is equal to 1, and discarding the module when ctrl4 is equal to 0;

the setting of the sixth bit is as follows: setting ctrl5 as a module 6 selection signal in the interrupt status processing module, selecting module 6 when ctrl5 is equal to 1, and discarding the module when ctrl5 is equal to 0;

the seventh bit is set as follows: setting ctrl6 as a module 7 selection signal in the interrupt status processing module, selecting module 7 when ctrl6 is equal to 1, and discarding the module when ctrl6 is equal to 0;

the setting of the eighth bit is as follows: setting ctrl7 as a module 8 selection signal in the interrupt status processing module, selecting module 8 when ctrl7 is equal to 1, and discarding the module when ctrl7 is equal to 0;

the interrupt control system is configured in the following way corresponding to the interrupt source requirement: when one interrupt source is used, configuring an interrupt source configuration register as ctrl7 ═ 0, ctrl6 ═ 0, ctrl5 ═ 0, ctrl4 ═ 0, ctrl3 ═ 0, ctrl2 ═ 0, ctrl1 ═ 0, and ctrl0 ═ 1, and selecting module 1 of the interrupt state processing module; when two interrupt sources are used, the interrupt source configuration registers are configured to be ctrl7 ═ 0, ctrl6 ═ 0, ctrl5 ═ 0, ctrl4 ═ 0, ctrl3 ═ 0, ctrl2 ═ 0, ctrl1 ═ 1, and ctrl0 ═ 1, and the module 1 and the module 2 of the interrupt state processing module are selected; when the three interrupt sources are used, the interrupt source configuration registers are configured to be ctrl7 ═ 0, ctrl6 ═ 0, ctrl5 ═ 0, ctrl4 ═ 0, ctrl3 ═ 0, ctrl2 ═ 1, ctrl1 ═ 1, and ctrl0 ═ 1, and the module 1, the module 2, and the module 3 of the interrupt state processing module are selected; when the four interrupt sources are used, the interrupt source configuration registers are configured to ctrl7 ═ 0, ctrl6 ═ 0, ctrl5 ═ 0, ctrl4 ═ 0, ctrl3 ═ 1, ctrl2 ═ 1, ctrl1 ═ 1, and ctrl0 ═ 1, and the module 1, the module 2, the module 3, and the module 4 of the interrupt state processing module are selected; when the five interrupt sources are used, the interrupt source configuration registers are configured to ctrl7 ═ 0, ctrl6 ═ 0, ctrl5 ═ 0, ctrl4 ═ 1, ctrl3 ═ 1, ctrl2 ═ 1, ctrl1 ═ 1, and ctrl0 ═ 1, and the module 1, the module 2, the module 3, the module 4, and the module 5 of the interrupt state processing module are selected; when the six interrupt sources are used, the interrupt source configuration registers are configured to ctrl7 ═ 0, ctrl6 ═ 0, ctrl5 ═ 1, ctrl4 ═ 1, ctrl3 ═ 1, ctrl2 ═ 1, ctrl1 ═ 1, and ctrl0 ═ 1, and the module 1, the module 2, the module 3, the module 4, the module 5, and the module 6 of the interrupt state processing module are selected; when seven interrupt sources are used, the interrupt source configuration registers are configured to ctrl7 ═ 0, ctrl6 ═ 1, ctrl5 ═ 1, ctrl4 ═ 1, ctrl3 ═ 1, ctrl2 ═ 1, ctrl1 ═ 1, and ctrl0 ═ 1, and the module 1, the module 2, the module 3, the module 4, the module 5, the module 6, and the module 7 of the interrupt state processing module are selected; when the eight interrupt sources are used, the interrupt source configuration registers are configured to ctrl7 ═ 1, ctrl6 ═ 1, ctrl5 ═ 1, ctrl4 ═ 1, ctrl3 ═ 1, ctrl2 ═ 1, ctrl1 ═ 1, and ctrl0 ═ 1, and the module 1, the module 2, the module 3, the module 4, the module 5, the module 6, the module 7, and the module 8 of the interrupt state processing module are selected.

TABLE 2 control register

As shown in table 2, the control register structure of the present invention is characterized by: the control register has 9 bits, and the control register with 9 bits can be flexibly configured according to the on-chip environment of the application, so that the interrupt system can be used in different on-chip processor systems, and each bit is defined as follows:

the first bit is set as follows: setting pending _ soft _ wr, namely starting software write enabling of the interrupt suspension register, wherein when the pending _ soft _ wr is equal to 1, the interrupt suspension register can be written through a data bus, and when the pending _ soft _ wr is equal to 0, the software write operation is invalid;

the second bit is set as follows: setting pending _ hd _ wr to start hardware write enable of the interrupt pending register, wherein when pending _ hd _ wr is equal to 1, an interrupt source sent by the interrupt state processing module can perform write operation on the interrupt pending register, and when pending _ hd _ wr is equal to 0, the hardware write operation is invalid;

the third bit is set as follows: setting mask _ wr _ ctrl1 to enable the interrupt mask register write enable, writing to the interrupt mask register via the data bus when mask _ wr _ ctrl1 is 1, and disabling the write when mask _ wr _ ctrl1 is 0;

the fourth bit is set as follows: setting mask _ wr _ ctrl2 to enable the interrupt mask register write enable, writing to the interrupt mask register via the data bus when mask _ wr _ ctrl2 is 1, and disabling the write when mask _ wr _ ctrl2 is 0;

the fifth bit is set as follows: setting read _ mask _ reg1 to start interrupt mask register read enable, when read _ mask _ reg1 is 1, the interrupt mask register can be read through the data bus, when read _ mask _ reg1 is 0, the read operation is invalid;

the setting of the sixth bit is as follows: setting read _ mask _ reg2 to start interrupt mask register read enable, when read _ mask _ reg2 is 1, the interrupt mask register can be read through the data bus, when read _ mask _ reg2 is 0, the read operation is invalid;

the seventh bit is set as follows: setting read _ pending _ reg as starting interrupt pending register read enable, when the read _ pending _ reg is equal to 1, reading the interrupt pending register through a data bus, and when the read _ pending _ reg is equal to 0, the reading operation is invalid;

the setting of the eighth bit is as follows: setting forbid _ ctrl to enable interrupt status signal output enable, allowing interrupt signal output when forbid _ ctrl equals to 1, and disabling interrupt signal output when forbid _ ctrl equals to 0;

the ninth bit is set as follows: setting int _ generator _ ctrl to start interrupt vector address generation enable, outputting a 3-bit interrupt vector to a data bus when int _ generator _ ctrl is 1, and not outputting the interrupt vector when int _ generator _ ctrl is 0;

the on-chip configurable interrupt control system circuit can be configured into interrupt systems capable of processing different numbers of interrupt sources through the interrupt source configuration register, is suitable for requirements of different on-chip systems, does not need to be redesigned, can be freely cut down by performing register configuration through software, has high circuit repeated utilization rate, reduces redesign resource waste, further ensures circuit function reliability, and reduces system design cost.

The configurable interrupt control system circuit on the chip adopts a LATCH LATCH design, in the integrated circuit design, the LATCH LATCH consumes less logic resources compared with a D flip-flop, 12 MOS tubes are needed for realizing one D flip-flop, 6 MOS tubes are needed for realizing one LATCH, the LATCH integration level is higher, 56 LATCHs are needed in the interrupt control system circuit, the number of transistors needed by all the LATCHs is 336, if the structure is realized by the flip-flop, the number of the transistors needed by the structure is 672, and the number of the transistors designed by the LATCH structure is reduced by 336 compared with the implementation mode of the flip-flop, so that the area of the interrupt system circuit can be obviously reduced, and the interrupt system circuit is convenient to realize on the chip.

The on-chip configurable interrupt control system circuit can be used in integrated electronic system of microsatellite platform, and is an important component of electronic system coprocessor, and because the satellite integrated electronic system processor can be used for processing load, power supply and attitude and orbit control, and its external states are more, and the interrupt requests required to be processed are different, said interrupt system can be flexibly configured according to the actual requirements of processors with different interrupt requirements, and can be used for different on-chip systems Modularization and light weight.

The invention has not been described in detail in part in the common general knowledge of a person skilled in the art.

Claims

1. An on-chip configurable interrupt control system circuit, comprising: the system comprises an interrupt source module, a clock reset module, a control register, N interrupt state processing modules, an interrupt source configuration module, a priority encoder, a self-clearing signal generating logic of a suspension register and an interrupt vector address generator; n is more than or equal to 2;

the interrupt vector address generator receives the N-bit interrupt signal sent by the priority encoder, generates interrupt vector address data under the control of the control information sent by the control register, and sends the interrupt vector address data to the data bus, the external system starts the interrupt execution process of the external system according to the received interrupt state flag signal, takes the data sent to the data bus by the interrupt vector address data, and the data is used as the entry address of the interrupt service program of the external system program.

2. The on-chip configurable interrupt control system circuit of claim 1, wherein: the interrupt source module configures the stage control information through an interrupt source configuration register; the interrupt source configuration register is an N-bit register, and each bit corresponds to one interrupt state processing module by setting a control signal ctrl (i = 0-N-1): when ctrl =1, indicating to select the interrupt state processing module corresponding to the control signal, and when ctrl =0, abandoning the interrupt state processing module; and according to the required number of interrupt sources, making ctrl i =1 of the corresponding digit to obtain the final stage control information.

3. The on-chip configurable interrupt control system circuit of claim 2, wherein: and according to the required interrupt source number requirement, starting from i =0 according to the sequence of ctrl i, and making ctrl i =1 with the corresponding number of bits to obtain final stage control information.

4. The on-chip configurable interrupt control system circuit of claim 1, wherein: the interrupt state processing module comprises a jump detector, an interrupt suspension register, an interrupt shielding register, a register data read-write module and an interrupt signal output and shielding prohibition control module;

the jump detector judges each bit of received interrupt source information, if the interrupt source information jumps from low to high, the jump detector outputs an interrupt request signal to an interrupt suspension register, and the interrupt suspension register returns a jump detection zero clearing signal to the jump detector after receiving the interrupt request signal for zero clearing of the state of the jump detector;

under the control of control information sent by the control register, the register data reading module outputs received interrupt signal data and interrupt shielding enabling signal data to a data bus, and an external system accesses the data bus and is used for judging the states of the interrupt shielding register and the interrupt suspension register; the interrupt signal output and shielding prohibition control module judges whether shielding is effective or not according to the data state of the interrupt shielding enabling signal of the interrupt shielding register, if the interrupt signal represents that the interrupt shielding state is effective, the interrupt state processing module outputs an invalid interrupt signal, otherwise, the interrupt signal output and shielding prohibition control module outputs an effective interrupt signal and sends the effective interrupt signal and the invalid interrupt signal to the interrupt source configuration module;

5. The on-chip configurable interrupt control system circuit of claim 4, wherein: the interrupt suspension register receives hardware interrupt source information or is written by software, and the interrupt suspension register can be configured into 1-8 bits according to requirements.

6. The on-chip configurable interrupt control system circuit of claim 4, wherein:

the interrupt mask register can only be written in by software, if the state position of the interrupt mask register is set to be 1, the interrupt source of the state position of the interrupt mask register is allowed to trigger interrupt, if the state position 0 of the interrupt mask register indicates that the interrupt source corresponding to the state position is forbidden to trigger interrupt, the interrupt request is invalid, and the interrupt suspension register can be configured to be 1-8 bits according to requirements.

7. The on-chip configurable interrupt control system circuit of claim 4, wherein:

the interrupt shielding register and the interrupt suspension register can be read by software, a register data read-write module in the system can read a data bus according to a control signal of the control register, the data bus is 8 bits, and the interrupt signal output and shielding prohibition control module can output an enable information state according to an interrupt state signal of the control register to determine to output an interrupt signal.

8. The on-chip configurable interrupt control system circuit of claim 4, wherein: the control information comprises interrupt mask register write enable information, interrupt mask register read enable information, interrupt pending register software write enable information, interrupt pending register hardware write enable information, interrupt pending register read enable information, interrupt state signal output enable information and interrupt vector address generation control information.

9. The on-chip configurable interrupt control system circuit of claim 4, wherein: the control register is at least 7-bit register, and the 9-bit control register is flexibly configured according to the on-chip environment of the application, so that the interrupt control system circuit can be used in different on-chip processor systems, and each bit is defined as follows:

10. The on-chip configurable interrupt control system circuit of claim 9, wherein: according to the application requirement and the reliability requirement of an external system, a two-bit redundancy backup design is added in a control register, wherein one bit is set to start an interrupt mask register write enable mask _ wr _ ctrl2, when the mask _ wr _ ctrl2 is 1, the external system can write an interrupt mask enable signal into the interrupt mask register through a data bus, and when the mask _ wr _ ctrl2 is 0, the read operation is invalid;