CN110928499B - Flash memory embedded in chip, chip and starting method of chip - Google Patents
Flash memory embedded in chip, chip and starting method of chip Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
- G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
- G06F8/654—Updates using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories
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Abstract
The invention discloses a flash memory embedded in a chip, the chip and a starting method of the chip; the flash memory is divided into a main memory space and an auxiliary memory space; the main memory space is provided with a program code memory area for storing program codes, and the program code memory area is a writable memory area; the auxiliary storage space is divided into a calibration parameter storage area, an intrinsic parameter storage area, a chip configuration storage area and a starting code storage area; the calibration parameter storage area is used for storing the calibration parameters of the chip and is a one-time programmable and unreadable storage area; the intrinsic parameter storage area is used for storing intrinsic parameters of the chip and is a one-time programmable and readable storage area; the chip configuration storage area is used for storing a configuration scheme of the chip and is a writable storage area; the boot code storage area is used for storing Bootloader boot codes of the chip and is a writable storage area. The chip of the invention has the advantages of low cost, high flexibility and high fault tolerance.
Description
Technical Field
The invention relates to the field of chip application development, in particular to a flash memory embedded in a chip, the chip and a starting method of the chip.
Background
An IC chip (integrated circuit) is a microstructure formed by forming a large number of microelectronic devices (transistors, resistors, capacitors, etc.) on a small or several small semiconductor wafers or dielectric substrates, and then packaging the semiconductor wafers or substrates in a package.
The chip is provided with a startup code which can be executed, namely a bootloader (bootloader), and the chip must run the startup code when the chip is powered on; the chip is provided with a special ROM for storing the starting codes, and the data stored in the ROM are generally written in advance before being installed into the whole machine, and can only be read out in the working process of the chip, and can not be quickly and conveniently rewritten like a random access memory; because of the nature of ROM, the development of the boot code must be completed before the solution of the chip is developed, that is, the boot code needs to be prepared in advance and cured in the ROM of the chip, the boot code cannot be changed after the chip is produced, and once the boot code has a defect (bug) or other safety hazards (e.g., is broken), the chip needs to be reflowed, which adversely affects the production of the chip.
Disclosure of Invention
The first object of the present invention is to provide a flash memory embedded in a chip, wherein the flash memory is structurally divided, a part of the space is used for storing Bootloader starting codes, and the Bootloader starting codes can be modified in the development process of the chip, so that the purpose of saving a ROM memory to reduce the design cost of the chip is achieved, and the development of the Bootloader starting codes is more flexible. The first object of the invention is achieved by the following technical scheme:
the flash memory embedded in the chip is characterized in that the flash memory is divided into a main storage space and an auxiliary storage space; the main memory space is provided with a program code memory area for storing program codes, the program code memory area is a writable memory area, and the stored program codes are unreadable by external equipment and can be read by a CPU of the chip; the auxiliary storage space is divided into a calibration parameter storage area, an intrinsic parameter storage area, a chip configuration storage area and a starting code storage area; the calibration parameter storage area is used for storing the calibration parameters of the chip and is a one-time programmable and unreadable storage area, and the content external equipment stored in the storage area and the CPU of the chip are unreadable; the intrinsic parameter storage area is used for storing intrinsic parameters of the chip and is a one-time programmable and readable storage area; the chip configuration storage area is used for storing a configuration scheme of the chip and is a writable storage area; the boot code storage area is used for storing Bootloader boot codes of the chip and is a writable storage area.
Further, the main storage space is also divided into a boot code backup area for backing up boot codes, which are writable storage areas.
Further, the main storage space is further divided into an auxiliary space upgrading data storage area for storing data to be upgraded of the auxiliary storage space, and the auxiliary space upgrading data storage area is a writable storage area.
Further, the auxiliary storage space is further divided into a user parameter storage area for storing parameters defined by a chip developer for the chip, and the parameters are readable and writable storage areas.
Further, the auxiliary storage space is further divided into a scheme parameter storage area, and the scheme parameter storage area is a one-time programmable storage area and is used for storing scheme parameters of a chip development scheme, and the scheme parameters are parameters required to be called in the process of executing the program codes.
Furthermore, the main storage space is also divided into an unreadable RAM storage area for storing some parameters which need to be protected and are generated in the execution of the program codes of the chip, and the stored content is unreadable by external equipment and can be read by the CPU of the chip.
Further, the main memory space is also divided into a readable RAM memory area for storing some changed parameters generated in execution of the program code of the chip.
Specifically, the main memory space and the auxiliary memory space of the flash memory are divided, and the division of each memory area of the two memory spaces is formed by constructing an AND gate and/or a NOR gate and peripheral circuits thereof.
The second object of the present invention is to provide a chip which does not need to use a ROM memory for storing Bootloader start codes, thereby effectively reducing the design cost of the chip; and the Bootloader starting code is more flexible to develop. The second object of the invention is achieved by the following technical scheme:
the chip comprises a flash starting state machine and is characterized by further comprising a verification controller module, a verification module, a flash memory protection switch, a verification information configuration module, a configuration scheme configuration module and a flash memory according to any one of the above;
the flash starting state machine is used for controlling the working flow of the flash memory and is in bidirectional connection with the check controller module;
the verification controller module comprises a parameter verification controller, a starting code verification controller and a program code verification controller; the parameter verification controller is used for sending a verification instruction of a calibration parameter, a verification instruction of an inherent parameter and a verification instruction of a configuration scheme, and sending one instruction each time; the starting code checking controller is used for sending a starting code checking instruction; the program code checking controller is used for sending a program code checking instruction;
The check module is in bidirectional connection with the check controller module of the check controller module; the verification module is in communication connection with the flash memory, and reads corresponding data from the flash memory for verification according to the verification instruction;
the flash memory protection switch is arranged between a data communication port of the flash memory and an information reading module for reading information in the flash memory, and is provided with a control port which is connected with one output end of the check controller module;
the output end of the parameter verification controller is respectively connected with the input ends of the verification information configuration module and the configuration scheme configuration module; the output end of the verification information configuration module is connected with a component of the chip to be configured with verification information; the said; the output end of the configuration scheme configuration module is connected with the component of the chip to be configured with the configuration scheme.
The third object of the present invention is to provide a method for starting up the chip of the second object. The third object of the invention is achieved by the following technical scheme:
the chip starting method is characterized by comprising the following steps of:
s1, powering up a chip;
S2, checking information of each storage area of the auxiliary storage space:
if the verification is passed, initializing auxiliary storage space calibration parameters and a configuration scheme of the chip to the chip, and then executing step S3; if the verification is not passed, the chip stops starting after the flash memory enters a protection state;
s3, checking program codes in a program code storage area of the main storage space:
if the verification of the program code is passed, executing step S4; if the verification is not passed, the chip stops starting after the flash memory enters a protection state;
s4, executing Bootloader starting codes in the starting code storage area;
s5, executing the chip program codes in the program code storage area.
Specifically, step S2 specifically includes the steps of:
s21, checking calibration parameters of a calibration parameter storage area:
if the calibration parameters pass the verification, executing step S22; if the calibration parameters are not checked, the chip is stopped to start after the flash memory enters a protection state;
s22, checking intrinsic parameters in an intrinsic parameter storage area:
if the verification of the intrinsic parameters is passed, step S23 is performed; if the verification of the intrinsic parameters is not passed, the chip is stopped to start after the flash memory enters a protection state;
S23, initializing calibration parameters into the chip;
s24, checking a configuration scheme of the chip in the chip configuration storage area:
if the verification of the configuration scheme is passed, executing step S25; if the verification of the configuration scheme is not passed, the chip is stopped to start after the flash memory enters a protection state;
s25, initializing a configuration scheme of the chip to the chip;
s26, bootloader starting code verification of a starting code storage area:
if the Bootloader starting code passes the verification, executing a step S3; if the Bootloader starting code is not checked, the chip stops starting after the flash memory enters a protection state.
Further, the main storage space is divided into a starting code backup area; the configuration scheme includes configuration of the switch state of the boot code backup area, and step S26 specifically includes:
s261, checking Bootloader starting codes in a starting code storage area of the auxiliary storage space;
s262, judging whether a starting code backup area of the main storage space is opened or not:
if the boot code backup area is open, step S263 is performed; if the boot code backup area is closed, step S265 is performed;
s263, checking the backup starting code of the starting code backup area of the main storage space;
S264, confirming the verification result of the starting codes of the main storage space and the auxiliary storage space:
if the starting codes of the main storage space and the auxiliary storage space are checked successfully, executing the step S3;
if the starting codes of the main storage space and the auxiliary storage space are successfully checked, and if one check fails, updating the data of the storage area with the failed check into the data of the storage area with the successful check, and then executing the step S3;
if the starting codes of the main storage space and the auxiliary storage space are failed to be checked, the chip is stopped to start after the flash memory enters a protection state;
s265, confirming a verification result of the boot code storage area of the auxiliary storage space:
if the starting code passes the verification, executing a step S3; if the starting code is not checked, the chip stops starting after the flash memory enters a protection state.
Further, in the process of running the program code in step S5, if the instruction for writing the data into the Flash memory exists in the execution command, the following procedure is entered:
A. judging the burnt area:
if the programmed area is in the scheme parameter storage area, executing the step B; if the programmed area is a writable area except a one-time programmable area, the corresponding area is programmed by combining with a programming program of a bootloader;
B. And (3) judging the programming record of the scheme parameter storage area:
if the scheme parameter storage area is provided with a programming record, programming is not performed, and meanwhile, a CPU of the chip is alerted; if the scheme parameter storage area has no programming record, the programming program of the bootloader is combined to perform data programming on the scheme parameter storage area.
Further, the configuration scheme comprises mapping of upgrade ports of the chip and configuration of enabling states of the upgrade ports; when the enabling state of the upgrade port is configured to be in an open state, in the process of running the program code in step S5, if the chip receives the program code upgrade instruction, the CPU of the chip automatically jumps to the Bootloader starting code, executes the upgrade code therein, enters the upgrade process, and then upgrades the program code in the main storage space.
Further, the configuration scheme comprises mapping of upgrade ports of the chip and configuration of enabling states of the upgrade ports; when the enabling state of the upgrade port is configured to be in an open state, in the process of running the program code in step S5, if the chip receives an upgrade instruction of the auxiliary storage space, the chip automatically jumps to a Bootloader starting code, executes the upgrade code therein, enters an upgrade process, and stores information to be upgraded of the auxiliary storage space into an auxiliary space upgrade data storage area of the main storage space; after the chip is powered up again, the step of upgrading the information of the secondary storage space is carried out after the step S23 and before the step S24, specifically, the step of upgrading the information of the secondary storage space chip includes:
M1, judging whether upgrade data exist in an auxiliary space upgrade data storage area of the main storage space, and if so, executing the step M2; if not, executing step S24;
m2, checking an auxiliary space upgrade data storage area:
if the verification is passed, updating the data of the corresponding storage area in the auxiliary storage space, and then executing step S24; if the verification is not passed, step S24 is directly performed.
The invention has the beneficial effects that:
the chip of the invention can reduce one ROM memory, has low cost, high flexibility and high fault tolerance, and a chip developer can develop Bootloader starting codes according to own requirements. The chip has the backup function of the Bootloader starting code, so that the Bootloader starting code is protected, and the probability of chip damage caused by abnormality of the Bootloader starting code is reduced.
Drawings
Fig. 1 is one of schematic structural diagrams of a flash memory of a chip according to an embodiment of the present invention;
FIG. 2 is a second schematic diagram of the structure division of the flash memory of the chip according to the embodiment of the present invention;
FIG. 3 is a third schematic diagram illustrating the structure division of a flash memory of a chip according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a structure division of a flash memory of a chip according to an embodiment of the present invention;
FIG. 5 is a flowchart of a chip start-up provided in an embodiment of the present invention;
FIG. 6 is a flowchart of information verification of each storage area of the secondary storage space of the chip according to the embodiment of the present invention;
FIG. 7 is another flow chart of information verification of each storage area of the secondary storage space of the chip according to the embodiment of the present invention;
FIG. 8 is a flowchart of a chip executing a programming program during execution of a program code according to an embodiment of the present invention;
FIG. 9 is a flowchart of program code upgrade of a chip provided by an embodiment of the present invention;
FIG. 10 is a partial flow chart of an information upgrade of a secondary storage space of a chip provided by an embodiment of the present invention;
fig. 11 is a schematic diagram of an internal structure of a chip according to an embodiment of the present invention.
Detailed Description
In order to more clearly understand the technical solution of the present invention, the present invention is further described below with reference to the following examples, and the specific examples are only for convenience of explanation of the solution content of the present invention, and the protection content of the present invention is not limited to the disclosure content of the specific examples.
As shown in fig. 1, the present invention provides a chip embedded with a flash memory for storing program codes of the chip; the flash memory is divided into a main memory space and an auxiliary memory space; the main memory space is divided into a program code memory area for storing program codes, the program code memory area is a writable memory area which has scrambling and protecting functions, the external equipment cannot read the program codes stored therein, and the CPU of the chip can read the program codes stored therein; the auxiliary storage space is divided into a calibration parameter storage area, an intrinsic parameter storage area, a chip configuration storage area and a starting code storage area; the calibration parameter storage area is used for storing the calibration parameters of the chip and is a one-time programmable and unreadable storage area, and the content external equipment stored in the storage area and the CPU of the chip cannot be read; the intrinsic parameter storage area is used for storing intrinsic parameters of the chip and is a one-time programmable and readable storage area; the chip configuration storage area is used for storing a configuration scheme of the chip and is a writable storage area, and the content stored in the writable storage area can be modified by adopting a special burning device; the boot code storage area is used for storing Bootloader boot codes of the chip, is a writable storage area, and can be modified by a special burning device.
The auxiliary storage space is also divided into a user parameter storage area and a scheme parameter storage area; the user parameter storage area is used for storing parameters defined by a chip developer for the chip, such as the type of the chip and the like, and is a readable and writable storage area. The scheme parameter storage area is a one-time programmable storage area and is used for storing scheme parameters of some chip development schemes of users, and parameters needing to be called in the process of executing program codes; in the prior art, the OTP memory is arranged in the chip for storing information of a chip development scheme, and the auxiliary memory space of the flash memory is divided into scheme parameter storage areas to realize the function of the OTP memory, so that the chip saves one OTP memory and reduces the overall cost of the chip.
The chip with the flash memory structure can save a ROM memory for solidifying Bootloader starting codes, can also save OTP memory, reduces the cost of the chip, and the Bootloader starting codes can be changed according to the needs of developers, so that the Bootloader starting codes and the chip are more flexible to develop.
In connection with fig. 2, the main storage space is also divided into a boot code backup area for backing up boot codes. The method is equivalent to providing an insurance for the Bootloader starting code, and effectively reduces the risk of the whole chip being damaged due to errors of the Bootloader starting code.
With reference to fig. 3, the main storage space is further divided into an auxiliary space upgrade data storage area for storing data to be upgraded in the auxiliary storage space, and the auxiliary space upgrade data storage area is a writable storage area. The auxiliary space upgrading data storage area is a transfer station for information upgrading of the auxiliary storage space, and can finish data upgrading of the auxiliary storage space without affecting the operation of the chip; the configuration scheme of the chip configuration storage area of the auxiliary storage space and the Bootloader starting code of the starting code storage area can be upgraded.
With reference to fig. 4, the main memory space is further divided into an unreadable RAM memory area and a readable RAM memory area; wherein the non-readable RAM storage area is used for storing some parameters which need to be protected and are generated by the program code of the chip in execution; the parameter external equipment of the storage area cannot be read, but the CPU of the chip can read the content; the readable RAM memory area is used to store parameters of changes generated by the chip's program code during execution, which are changed all the time, and which can be used for the next time to be re-powered up, and also to locate problems when they occur, to restore the current field situation.
The configuration scheme of the chip configuration storage area is specific to some configurations of the chip, such as mapping information (debug port, upgrade port, development port) of each functional port of the chip, information such as pull-up control of each functional port, selection of UART upgrade port, etc., enabling state of debug port, enabling state of upgrade port, capacity of each storage area of main storage space, etc.
The calibration parameter storage area stores some calibration parameters of the chip in the test; when the chips are produced, due to the differences of components, processes and the like, some parameters in the chips have some deviation compared with design values, for example, the design value of the clock frequency is 26MHz, but the actual frequency of each chip is 24/25/27/28MHz which is not consistent with the design value, so that the clock frequency of the chips needs to be calibrated, and the clock frequency of each chip is as close to 26MHz as possible; parameters such as analog circuit clock, ADC, DAC, voltage and the like need to be calibrated; after calibration is completed, these calibration parameters are saved to a calibration parameter storage area.
The above-mentioned inherent parameters refer to identification information, characteristic parameters and the like of the chip; wherein the identification information of the chip refers to information capable of identifying the identity of the chip such as the ID of the chip; the characteristic parameters of the chip refer to some parameters of the chip design, such as the information that the clock frequency of the chip is 26MHz, the working voltage is 3.3V, and the like.
The chip of the invention divides the embedded flash memory into structures, so that one part is used for storing Bootloader starting codes to save a ROM memory and the other part is used for realizing the function of the OTP memory, thereby effectively saving the number of memories in the chip and reducing the overall cost of the chip; and the Bootloader starting code can be modified in the process of chip development, so that the chip development is more flexible.
The main memory space and the auxiliary memory space of the flash memory of the chip and the memory areas of the two memory spaces are divided by the AND gate and/or the NOR gate and the peripheral circuits thereof.
Referring to fig. 11, the internal structure of the chip of the present invention includes: the device comprises a flash starting state machine, a verification controller module, a verification module, the flash memory, a flash memory protection switch, a verification information configuration module and a configuration scheme configuration module.
The flash starting state machine is used for controlling the working flow of the flash memory and is in bidirectional connection with the check controller module.
The verification controller module comprises a parameter verification controller, a starting code verification controller and a program code verification controller; the verification controller module selects a certain verification controller to develop and send a verification instruction according to a workflow controlled by the flash starting state machine, wherein the parameter verification controller is used for sending a verification instruction of a calibration parameter, a verification instruction of an inherent parameter and a verification instruction of a configuration scheme, and one instruction is sent each time; the starting code checking controller is used for sending a starting code checking instruction; the program code verification controller is used for sending program code verification instructions.
The checking module is connected with each checking controller of the checking controller module in a two-way, and receives checking instructions of the checking controller module and feeds back checking results to the checking controller module; the verification module is in communication connection with the flash memory, and reads corresponding data from the flash memory for verification according to the verification instruction.
The flash memory protection switch is arranged between a data communication port of the flash memory and an information reading module for reading information in the flash memory, and is provided with a control port which is connected with one output end of the check controller module; when the check controller module receives feedback information of the check module and the check fails, the corresponding check controller of the check controller module sends a check failure signal to a control port of the flash memory protection switch, and the flash memory protection switch disconnects the information reading module from a data communication port of the flash memory, so that the flash memory enters a protection mode, and the information in the flash memory cannot be read; when the check controller module receives feedback information of the check module to pass the check, the corresponding check controller of the check controller module sends a check success signal to a control port of the flash memory protection switch, and the flash memory protection switch conducts connection between the information reading module and a data communication port of the flash memory so that information in the flash memory can be read; the information reading module can be a module inside a chip or a module outside the chip for reading information stored in the flash memory.
The output end of the parameter verification controller is connected with the input ends of the verification information configuration module and the configuration scheme configuration module; the output end of the verification information configuration module is connected with a component of the chip to be configured with verification information; the said; the output end of the configuration scheme configuration module is connected with the component of the chip to be configured with the configuration scheme.
When the verification instruction received by the verification module is a verification instruction of an intrinsic parameter from the parameter verification controller (the intrinsic parameter is set according to the starting flow of the chip, and verification is performed only when the verification of the intrinsic parameter is successful in the embodiment), and when the feedback information received by the parameter verification controller by the verification module is verification passing, the verification information configuration module initializes the verification information to the chip (that is, when both the intrinsic parameter and the verification parameter are successfully verified, the verification information is initialized to the chip); when the verification instruction received by the verification module is a verification instruction from the parameter verification controller configuration scheme, and the feedback information received by the parameter verification controller by the verification module is verification passing, the configuration scheme configuration module initializes the configuration scheme to the chip.
The verification module is integrated in the applied chip, which is beneficial to reducing the cost.
Specifically, the verification of the information in each storage area is to verify whether the data in the corresponding storage area is accurate; the data of each storage area can also store the verification information of the corresponding data in the storage process; the verification information of a certain storage area is information obtained by a certain algorithm after the data of the storage area are generated (information calculated by a non-verification module is the verification information calculated before the data are stored in a chip).
The specific verification method for the data in a certain storage area is as follows: the verification module in the chip obtains the comparison verification information of each information in the storage area read by the verification module according to the same verification algorithm; comparing the comparison check information with the check information of the storage area, and if the comparison check information and the check information are the same (matched), checking to pass, so as to prove that the data of the storage area is correct; if the two are not identical (not matched), the verification is failed, and the data of the storage area is proved to have errors.
Specifically, the verification algorithm may be, but is not limited to, the following: parity check algorithm, MD5 check algorithm, CRC check algorithm, BCC check algorithm, etc.; one embodiment of the present invention uses a CRC check algorithm, and the specific check algorithm is a common algorithm for information check in the prior art, and will not be described herein.
The production and start-up flow of the chip of the present invention is described below:
design of stage one and chip hardware structure
In the stage, the chip completes the design of a hardware structure and the structural division of the flash memory; the structure of the flash memory is divided according to the above description.
Stage two, chip testing and parameter calibration
In the production process of the chip, the possibility of bad chips possibly exists, the bad chips are screened out through the test of the chip, and the chip with good performance is reserved; parameter calibration has been described above and will not be described here again.
After the parameter calibration of the chip is finished, storing each calibration parameter in a calibration parameter storage area in the auxiliary storage space, and when the calibration is finished, completing self-locking of the calibration parameter storage area after the calibration parameter is stored, wherein the information in the calibration parameter storage area cannot be changed; that is to say the calibration parameter memory area is also a one-time programmable area.
At this stage, intrinsic parameters such as identification information and characteristic parameters of the chip are stored in an intrinsic parameter storage area of the sub-storage space.
In terms of hardware, the calibration parameter storage area and the intrinsic parameter storage area in the auxiliary storage space are set to be one-time programmable areas, so that after the data in the two storage areas are burnt in the second stage, the information of the two storage areas cannot be modified in the future; the information in the calibration parameter storage area is in an unreadable state, and the user cannot know the content of the information; the information in the intrinsic parameter storage area is public and readable.
In this stage, the chip also writes the initial Bootloader starting code into the starting code storage area, and in the later stage of chip development, according to the development scheme of the chip, the Bootloader starting code can be updated in a corresponding manner.
Stage three, development of chip and program code burning
After the development of the chip is completed, the program codes of the chip are required to be burnt into a program code storage area of a main storage space; the Bootloader starting code has a corresponding burning flow to guide the burning of the program code.
At this stage, bootloader boot code may also be upgraded according to the status of chip development.
At this stage, the chip will also write the configuration scheme of the chip in the chip configuration storage area; the storage area is a writable storage area, and when the information in the storage area needs to be changed (for example, the capacity of each storage area of the main storage space needs to be changed), the information of the user configuration area can be re-recorded.
Specifically, the chip configuration storage area is configured with a mapping and an enabling state of the upgrade port, when the enabling of the upgrade port is set to be on, the upgrade port is connected through the UART, and an upgrade process in the Bootloader is executed after a fixed upgrade sequence is input, so that in the upgrade process, the chip is connected with a special burning device to realize configuration scheme upgrade of the chip configuration storage area, upgrade of Bootloader starting codes, upgrade of program codes and the like.
In this stage, according to the development condition of the chip, the information content in the scheme parameter storage area is burnt, and after the content in the scheme parameter storage area is burnt once, the information in the scheme parameter storage area can not be changed.
At this stage, the information in the user parameter storage area is also burned according to the development condition of the user.
As shown in fig. 5, after the chip development is completed, the chip of the present invention is started up by the following steps:
s1, powering up a chip;
s2, checking information of each storage area of the auxiliary storage space:
if the verification is passed, initializing auxiliary storage space calibration parameters and a configuration scheme of the chip to the chip, and then executing step S3; if the verification is not passed, the chip stops starting after the flash memory enters a protection state.
S3, checking program codes in a program code storage area of the main storage space:
if the verification of the program code is passed, executing step S4; if the verification is not passed, the chip stops starting after the flash memory enters a protection state.
S4, executing Bootloader starting codes in the starting code storage area:
s5, executing the chip program codes in the program code storage area.
Specifically, as shown in fig. 5, the step S2 specifically includes the following steps:
S21, checking calibration parameters of a calibration parameter storage area:
if the calibration parameters pass the verification, executing step S22; if the calibration parameters are not checked, the chip is stopped to start after the flash memory enters a protection state.
S22, checking intrinsic parameters in an intrinsic parameter storage area:
if the verification of the intrinsic parameters is passed, step S23 is performed; if the verification of the inherent parameters is not passed, the chip is stopped to start after the flash memory enters a protection state.
The sequence of the steps S21 and S22 is not required, or the step S22 may be performed first, and then the step S21 may be performed, where the execution sequence is determined according to the procedure set by the flash start state machine.
S23, initializing calibration parameters into the chip;
s24, checking a configuration scheme of the chip in the chip configuration storage area:
checking the configuration scheme of the chip in the chip configuration storage area, and executing step S25 if the configuration scheme passes the check; if the verification is not passed, the chip stops starting after the flash memory enters a protection state.
S25, initializing a configuration scheme of the chip to the chip;
s26, bootloader starting code verification of a starting code storage area:
if the Bootloader starting code passes the verification, executing a step S3; if the Bootloader starting code is not checked, the chip stops starting after the flash memory enters a protection state.
As shown in fig. 7, when the main storage space has a boot code backup area, step S26 further includes a step of boot code verification for backup of the boot code backup area, and step S26 specifically includes:
s261, checking Bootloader starting codes in a starting code storage area of the auxiliary storage space;
s262, judging whether a starting code backup area of the main storage space is opened or not:
if the boot code backup area is open, step S263 is performed; if the boot code backup area is closed, step S265 is performed.
Specifically, the open/close state of the boot code backup area is set in the chip configuration memory area.
S263, checking the backup starting code of the starting code backup area of the main storage space;
s264, confirming the verification result of the starting codes of the main storage space and the auxiliary storage space:
if the starting codes of the main storage space and the auxiliary storage space are checked successfully, executing the step S3;
if the starting codes of the main storage space and the auxiliary storage space are successfully checked, and if one check fails, updating the data which fails to check into data which fails to check, and then executing the step S3;
if the starting codes of the main storage space and the auxiliary storage space are failed to be checked, the chip is stopped to start after the flash memory enters a protection state.
S265, confirming the verification result of the boot code storage area of the auxiliary storage space
If the starting code passes the verification, executing a step S3; if the starting code is not checked, the chip stops starting after the flash memory enters a protection state.
Specifically, in connection with fig. 8, when the chip is started, in the process of running the program code in step S5, if an instruction for writing data into the Flash memory is included in the execution command, the following procedure is entered:
A. judging the burnt area:
if the programmed area is in the scheme parameter storage area, executing the step B; if the programmed area is a writable area except a one-time programmable area, the corresponding area is programmed by combining with a programming program of a bootloader;
B. and (3) judging the programming record of the scheme parameter storage area:
if the scheme parameter storage area is provided with a programming record, programming is not performed, and meanwhile, a CPU of the chip is alerted; if the scheme parameter storage area has no programming record, the programming program of the bootloader is combined to perform data programming on the scheme parameter storage area.
Referring to fig. 9, the method for upgrading the program code of the chip of the present invention is as follows, when the upgrade port is in an open state (according to the configuration of the chip configuration storage area), if the chip receives the program code upgrade instruction in the process of running the program code in step S5, the CPU of the chip automatically jumps to the Bootloader starting code, executes the upgrade code therein, enters the upgrade process, and then upgrades (content updates) the program code in the main storage space, so as to update the program code by using a proprietary burning device matched with the chip.
If the main memory space is divided into auxiliary space upgrade data memory areas, the method for upgrading the information of the auxiliary memory space of the chip is as follows, wherein the contents of a chip configuration memory area, a starting code memory area and a user parameter memory area of the auxiliary memory space can be upgraded, and the contents of a scheme parameter memory area, a calibration parameter memory area and an inherent parameter memory area cannot be changed; when the upgrade port is in an open state (configuration of a chip configuration storage area), in the process of running the program code in step S5, if the chip receives an upgrade instruction of the auxiliary storage space, the chip automatically jumps to a Bootloader starting code, executes the upgrade code therein, enters an upgrade flow, and stores the information to be upgraded of the auxiliary storage space into an auxiliary space upgrade data storage area of the main storage space; then, after the chip is powered up again, an upgrade step of the information of the sub memory space is carried out before S24 after step S23. The auxiliary space upgrading data storage area is a transfer station for information upgrading of the auxiliary storage space, when an upgrading instruction exists, the information to be upgraded is stored in the transfer station, and after the transfer station is electrified again, the information upgrading of the auxiliary storage space is completed through a certain flow.
Specifically, in connection with fig. 10, the step of upgrading the information of the secondary storage space chip includes:
m1, judging whether upgrade data exist in an auxiliary space upgrade data storage area of the main storage space, and if so, executing the step M2; if not, executing step S24;
m2, checking an auxiliary space upgrade data storage area:
checking, namely updating data of a corresponding area in the auxiliary storage space, and then executing step S24; if the verification is not passed, step S24 is directly performed.
Specifically, the verification of the auxiliary space upgrading data storage area comprises verification of a configuration scheme to be upgraded and verification of a Bootloader starting code to be upgraded, and if one of the verification and the verification fails, the data of the auxiliary storage space cannot be updated.
If the verification is not passed, it indicates that the chip may be attacked by the outside or the information security of the chip may be threatened by other reasons, so once the verification is not passed, the flash memory of the chip will enter a protection state, and the outside cannot read any information in the flash memory.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. without being creatively made are included in the protection scope of the present invention.
Claims (15)
1. The flash memory embedded in the chip is characterized in that the flash memory is divided into a main storage space and an auxiliary storage space; the main memory space is provided with a program code memory area for storing program codes, the program code memory area is a writable memory area, and the stored program codes are unreadable by external equipment and can be read by a CPU of the chip; the auxiliary storage space is divided into a calibration parameter storage area, an intrinsic parameter storage area, a chip configuration storage area and a starting code storage area; the calibration parameter storage area is used for storing the calibration parameters of the chip and is a one-time programmable and unreadable storage area, and the content external equipment stored in the storage area and the CPU of the chip are unreadable; the intrinsic parameter storage area is used for storing intrinsic parameters of the chip and is a one-time programmable and readable storage area; the chip configuration storage area is used for storing a configuration scheme of the chip and is a writable storage area; the boot code storage area is used for storing Bootloader boot codes of the chip and is a writable storage area.
2. The flash memory according to claim 1, wherein the main memory space is further divided into a boot code backup area for backing up boot codes, which are writable storage areas.
3. The flash memory according to claim 1, wherein the main memory space is further divided into an auxiliary space upgrade data storage area for storing data to be upgraded of the auxiliary memory space, and the auxiliary space upgrade data storage area is a writable storage area.
4. The flash memory according to claim 1, wherein the sub-memory space is further divided into a user parameter storage area for storing parameters defined by a chip developer for the chip, and is a readable/writable storage area.
5. The flash memory according to claim 1, wherein the auxiliary memory space is further divided into a scheme parameter storage area, the scheme parameter storage area is a one-time programmable storage area for storing scheme parameters of a chip development scheme, which are parameters to be called in the process of executing the program code.
6. The flash memory according to any one of claims 1 to 5, wherein the main memory space is further divided into an unreadable RAM memory area for storing some parameters to be protected generated by the program code of the chip during execution, and the content stored therein is unreadable by an external device and readable by the CPU of the chip.
7. The flash memory of claim 6, wherein the main memory space is further divided into a readable RAM memory area for storing parameters of some variations in execution of the program code of the chip.
8. The flash memory according to claim 7, wherein the division of the main memory space and the sub memory space of the flash memory, the division of the respective memory areas of the two memory spaces are formed by and gate and/or nor gate and peripheral circuit construction thereof.
9. A chip comprising a flash starting state machine, and further comprising a verification controller module, a verification module, a flash memory protection switch, a verification information configuration module, a configuration scheme configuration module, and the flash memory according to any one of claims 1 to 8;
the flash starting state machine is used for controlling the working flow of the flash memory and is in bidirectional connection with the check controller module;
the verification controller module comprises a parameter verification controller, a starting code verification controller and a program code verification controller; the parameter verification controller is used for sending a verification instruction of a calibration parameter, a verification instruction of an inherent parameter and a verification instruction of a configuration scheme, and sending one instruction each time; the starting code checking controller is used for sending a starting code checking instruction; the program code checking controller is used for sending a program code checking instruction;
The check module is in bidirectional connection with the check controller module of the check controller module; the verification module is in communication connection with the flash memory, and reads corresponding data from the flash memory for verification according to the verification instruction;
the flash memory protection switch is arranged between a data communication port of the flash memory and an information reading module for reading information in the flash memory, and is provided with a control port which is connected with one output end of the check controller module;
the output end of the parameter verification controller is respectively connected with the input ends of the verification information configuration module and the configuration scheme configuration module; the output end of the verification information configuration module is connected with a component of the chip to be configured with verification information; the said; the output end of the configuration scheme configuration module is connected with the component of the chip to be configured with the configuration scheme.
10. A method of starting a chip as claimed in claim 9, comprising the steps of:
s1, powering up a chip;
s2, checking information of each storage area of the auxiliary storage space:
if the verification is passed, initializing auxiliary storage space calibration parameters and a configuration scheme of the chip to the chip, and then executing step S3; if the verification is not passed, the chip stops starting after the flash memory enters a protection state;
S3, checking program codes in a program code storage area of the main storage space:
if the verification of the program code is passed, executing step S4; if the verification is not passed, the chip stops starting after the flash memory enters a protection state;
s4, executing Bootloader starting codes in the starting code storage area;
s5, executing the chip program codes in the program code storage area.
11. The method for starting a chip according to claim 10, wherein step S2 specifically comprises the steps of:
s21, checking calibration parameters of a calibration parameter storage area:
if the calibration parameters pass the verification, executing step S22; if the calibration parameters are not checked, the chip is stopped to start after the flash memory enters a protection state;
s22, checking intrinsic parameters in an intrinsic parameter storage area:
if the verification of the intrinsic parameters is passed, step S23 is performed; if the verification of the intrinsic parameters is not passed, the chip is stopped to start after the flash memory enters a protection state;
s23, initializing calibration parameters into the chip;
s24, checking a configuration scheme of the chip in the chip configuration storage area:
if the verification of the configuration scheme is passed, executing step S25; if the verification of the configuration scheme is not passed, the chip is stopped to start after the flash memory enters a protection state;
S25, initializing a configuration scheme of the chip to the chip;
s26, bootloader starting code verification of a starting code storage area:
if the Bootloader starting code passes the verification, executing a step S3; if the Bootloader starting code is not checked, the chip stops starting after the flash memory enters a protection state.
12. The method for starting a chip according to claim 11, wherein the main memory space is divided into a boot code backup area; the configuration scheme includes configuration of the switch state of the boot code backup area, and step S26 specifically includes:
s261, checking Bootloader starting codes in a starting code storage area of the auxiliary storage space;
s262, judging whether a starting code backup area of the main storage space is opened or not:
if the boot code backup area is open, step S263 is performed; if the boot code backup area is closed, step S265 is performed;
s263, checking the backup starting code of the starting code backup area of the main storage space;
s264, confirming the verification result of the starting codes of the main storage space and the auxiliary storage space:
if the starting codes of the main storage space and the auxiliary storage space are checked successfully, executing the step S3;
if the starting codes of the main storage space and the auxiliary storage space are successfully checked, and if one check fails, updating the data of the storage area with the failed check into the data of the storage area with the successful check, and then executing the step S3;
If the starting codes of the main storage space and the auxiliary storage space are failed to be checked, the chip is stopped to start after the flash memory enters a protection state;
s265, confirming a verification result of the boot code storage area of the auxiliary storage space:
if the starting code passes the verification, executing a step S3; if the starting code is not checked, the chip stops starting after the flash memory enters a protection state.
13. The method according to claim 11 or 12, wherein, during the running of the program code in step S5, if the command is executed with an instruction to write data into the Flash memory, the following procedure is entered:
A. judging the burnt area:
if the programmed area is in the scheme parameter storage area, executing the step B; if the programmed area is a writable area except a one-time programmable area, the corresponding area is programmed by combining with a programming program of a bootloader;
B. and (3) judging the programming record of the scheme parameter storage area:
if the scheme parameter storage area is provided with a programming record, programming is not performed, and meanwhile, a CPU of the chip is alerted; if the scheme parameter storage area has no programming record, the programming program of the bootloader is combined to perform data programming on the scheme parameter storage area.
14. The method according to claim 11 or 12, wherein the configuration scheme includes mapping of upgrade ports of a chip and configuration of enable states of the upgrade ports; when the enabling state of the upgrade port is configured to be in an open state, in the process of running the program code in step S5, if the chip receives the program code upgrade instruction, the CPU of the chip automatically jumps to the Bootloader starting code, executes the upgrade code therein, enters the upgrade process, and then upgrades the program code in the main storage space.
15. The method according to claim 11 or 12, wherein the configuration scheme includes mapping of upgrade ports of a chip and configuration of enable states of the upgrade ports; when the enabling state of the upgrade port is configured to be in an open state, in the process of running the program code in step S5, if the chip receives an upgrade instruction of the auxiliary storage space, the chip automatically jumps to a Bootloader starting code, executes the upgrade code therein, enters an upgrade process, and stores information to be upgraded of the auxiliary storage space into an auxiliary space upgrade data storage area of the main storage space; after the chip is powered up again, the step of upgrading the information of the secondary storage space is carried out after the step S23 and before the step S24, specifically, the step of upgrading the information of the secondary storage space chip includes:
M1, judging whether upgrade data exist in an auxiliary space upgrade data storage area of the main storage space, and if so, executing the step M2; if not, executing step S24;
m2, checking an auxiliary space upgrade data storage area:
if the verification is passed, updating the data of the corresponding storage area in the auxiliary storage space, and then executing step S24; if the verification is not passed, step S24 is directly performed.
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| CN112256338B (en) * | 2020-10-27 | 2023-12-05 | 记忆科技(深圳)有限公司 | SOC starting method and device, computer equipment and storage medium |
| CN112634976A (en) * | 2020-12-17 | 2021-04-09 | 苏州兆方微电子科技有限公司 | Chip calibration method and device, storage medium and chip |
| CN112463242A (en) * | 2020-12-17 | 2021-03-09 | 南方电网电力科技股份有限公司 | Starting method and device for electric energy meter operating system, electric energy meter and storage medium |
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| CN115454517B (en) * | 2022-11-11 | 2023-03-10 | 山东云海国创云计算装备产业创新中心有限公司 | Method, system, storage medium, device and chip for multi-medium secure boot |
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