CN110888767A - Interface multiplexing module verification platform architecture and quick expansion implementation method - Google Patents
Interface multiplexing module verification platform architecture and quick expansion implementation method Download PDFInfo
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The utility model provides an interface multiplexing module verification platform architecture and a rapid expansion realization method.A data end integrates a plurality of agents, each agent integrates a monitor monitoring module for sampling control and data signals on a bus, and a communication port adds a monitor monitoring module in a behavior level functional model provided by an independent agent or a third party for monitoring and sampling the communication port; the monitor monitoring module analyzes the sampling signal into a data transaction taking a unit address as a unit, and sends the data transaction to scoreboard through a pipeline for comparison and verification; the utility model discloses can be applicable to the verification of most interface class modules to can be applicable to the verification of other functional modules through only changing a small amount, help the verification engineer set up the module fast and verify the platform or transplant to other project platforms, very big saving verify the time that the platform was set up, improved and verified work efficiency.
Description
Technical Field
The present disclosure relates to the field of interface module verification platform technologies, and in particular, to an interface multiplexing module verification platform architecture and a fast expansion implementation method.
Background
The statements in this section merely provide background information related to the present disclosure and may not necessarily constitute prior art.
At present, Chip design is converted into SoC (System on Chip) Integrated design through traditional ASIC (Application Specific Integrated Circuit) design, and the SoC can help Chip research and development teams to greatly save development time and complete Chip design through IP multiplexing technology, so that products are brought to the market as soon as possible. All SoC chips contain abundant data transmission interfaces or interface control modules, and high-speed interfaces such as: USB interface, SATA interface, Ethernet interface etc. low-speed interface is like: UART interface, IIC interface, GPIO interface, etc., and even the interface or bridge chip can customize special multiplexing interface to realize multiplexing of three or four transmission modes. As is known, the time and labor required for chip verification is about 2-3 times of the chip design, and it will certainly take a long time to complete all module verification.
The interface module generally includes auxiliary ports such as command ports, data ports, interrupts, and the like, as well as communication ports that conform to protocol timing. The command port and the data port are ports for internal configuration and data transmission of a chip, and according to a chip Bus Architecture and a transmission speed and a mounting position of an Interface module, the command port and the data port may be any one of an AHB (Advanced high-performance Bus) Bus, an AXI (Advanced eXtensible Bus) Bus or an APB (Advanced Peripheral Bus) Bus in an AMBA (Advanced micro controller Bus Architecture) Bus, wherein the command port is a Master port, and the data port may be a Slave port or a Slave port; the communication port is generally a transmission port for communication between the chip and the outside of the chip, and such a port may be a Master port or a Slave port, and the timing of the port is determined according to a self protocol, and the protocol may be an autonomously designed interface timing protocol or a general standard protocol in the industry.
The inventor finds that the traditional interface module Verification platform integrates ahb or axi according to the Design thereof, a command and data agent and a communication end agent, the agent of the data and communication end is responsible for generating random excitation meeting the Design specification, the random excitation is driven to a DUV (Design Under Verification: Design to be tested) through a driver in the agent, meanwhile, the excitation is sent to a reference model through a pipeline, the analysis is carried out in the reference model according to the established rule, and then the analyzed data transaction is sent to a scoreboard through the pipeline by the reference model for data comparison and Verification. Under the condition that the subsequent design of the verification platform is changed or the protocol of the communication port is changed, the related agent, reference model and scoreboard in the verification platform are greatly changed, the workload is increased, and the verification progress is seriously influenced.
Disclosure of Invention
In order to solve the deficiency of the prior art, the utility model provides an interface multiplexing module verification platform framework and quick extension implementation method, compare with traditional verification platform structure, this platform has the portability strong and expands quick convenient advantage, can be applicable to the verification of most interface class modules, and can be applicable to the verification of other functional modules through only changing a small amount, help the verification engineer set up module verification platform fast or transplant to other project platforms, very big saving the time that the verification platform was set up, verification work efficiency has been improved.
In order to achieve the purpose, the following technical scheme is adopted in the disclosure:
a first aspect of the present disclosure provides an interface multiplexing module validation platform architecture.
An interface multiplexing module verification platform architecture, a data end integrates multiple agents, and after each agent generates random excitation, the data end is driven to a DUV through a driver in the agent;
each agent is integrated with a monitor monitoring module for sampling control and data signals on the bus, analyzing the data signals into data transactions with unit addresses as units (such as Byte addresses), and directly sending the data transactions to the scoreboard through a pipeline for comparison and verification.
As some possible implementations, the agent of the data side integration at least includes ahb _ master, ahb _ slave, axi _ master, axi _ slave and apb _ master.
As some possible implementation ways, data ports which are not used in the design are shielded in a macro-defined way in the platform environment.
As some possible implementation manners, the communication port integrates an autonomous agent meeting the protocol time sequence or a behavior level function model provided by a third party, and a monitor monitoring module is added in the behavior level function model provided by the autonomous agent or the third party and is used for monitoring and sampling the communication port, analyzing the data transaction into a data transaction which is unified with the data port and takes the unit address as a unit, and sending the data transaction to the scoreboard through a pipeline for comparison and verification.
As a further limitation, the communication port can integrate a plurality of agents according to the multiplexing mode defined by the interface module, and when different working modes are adopted, different agents are called.
As some possible implementation manners, the cpu agent generates random control information according to the design specification of the interface module, configures the random control information to the DUV command port through the reg _ agent, sends an instruction to the agent of each data end through the pipeline, and starts data transmission.
As a further limitation, reg _ agent integrates three interfaces, i.e. ahb, axi and apb, and selects one interface to realize register configuration by adopting a macro definition mode.
As a further limitation, an interrupt response mechanism is implemented in the cpu agent, and an interrupt signal generated in the data transmission process is monitored, and when an interrupt occurs, a response is made according to the interrupt mechanism.
The second aspect of the present disclosure provides a method for implementing fast expansion of an interface multiplexing module verification platform architecture.
A method for realizing quick expansion of an interface multiplexing module verification platform architecture comprises the following steps:
step (9-1): establishing interface interfaces required by a command port, a data port and a communication port according to design specifications;
step (9-2): creating data terminals ahb master agent, ahb slave agent, axi master agent, axi slave agent and apb master agent, and adding a sending pipeline port for receiving a cpu instruction and a data transaction sending pipeline port to the scoreboard;
step (9-3): establishing an agent of a communication end, if the verification module is a multiplexing interface module, respectively establishing different agents according to different multiplexing modes and interface protocols, and adding a data transaction sending pipeline port sent to the scoreboard;
step (9-4): establishing a macro definition file, wherein the macro definition file comprises a data port macro definition, a command interface type macro definition and an interface multiplexing mode which are required to be used according to a design definition;
step (9-5): creating a scoreboard, respectively adding corresponding data transaction receiving pipeline ports aiming at each data end and each communication end agent, and defining corresponding tasks to realize comparison and verification of data from each pipeline port;
step (9-6): creating a cpu agent, generating various configurations according with design functions according to design specifications, configuring a DUV through a command port, sending an instruction to a data end agent, generating random excitation to start data transmission, monitoring an interrupt signal of the DUV, and responding according to an interrupt mechanism when interrupt is generated;
step (9-7): creating env, constructing various agents and scoreboards defined above, defining interactive communication pipelines according to an integrated data end and a communication end, and butting the used pipeline ports and pipelines together to ensure that data transactions can correctly circulate in a platform;
step (9-8): integrating the DUV to the whole design platform through the interface, so that random excitation generated by each agent can be driven to the DUV through the interface, and the response generated by the DUV can be monitored through a monitor in the interface agent;
step (9-9): and constructing a test case, starting a verification platform, calling the verification platform in order according to the constructed agent function, circulating data transactions in the whole verification platform and the DUV, finally collecting the data transactions to scoreboard, and automatically completing verification and comparison work.
As some possible implementations, in step (9-2), the ahb master agent, ahb slave agent, axi master agent, axi slave agent and apb master agent implement a driver driving module and a monitor monitoring module through UVM, which at least includes actions of generating a random stimulus with constraints, driving to an interface, and monitoring a bus interface.
Compared with the prior art, the beneficial effect of this disclosure is:
1. compared with the traditional verification platform structure, the verification platform structure has the advantages of strong portability, quick and convenient expansion and the like, can be suitable for verification of most interface modules, can be suitable for verification of other functional modules through only a small amount of change, helps a verification engineer to quickly build the module verification platform or transplant to other project platforms, greatly saves the time for building the verification platform, and improves the verification work efficiency.
2. According to the content disclosed by the disclosure, under the interface multiplexing mode, agents with different working modes and different module items can be added at a communication end, the agent of the communication end is replaced, or BFM provided by a third party is integrated, and different data end agents and command interface types are selected through a macro definition file, so that the establishment of a verification platform can be completed.
3. According to the method and the device, the data ports which are not used in the design can be shielded in a macro definition mode in the platform environment, and the burden of a CPU (Central processing Unit) processor during the operation of the simulator can not be increased due to the fact that too many agents are integrated in the platform.
4. According to the method, no analysis is needed at the scoreboard or the reference model, and the data transaction sent from the data port can be directly compared and verified, so that the workload increase caused by large changes of the related agent, the reference model and the scoreboard in the verification platform under the condition that the subsequent design is changed or the protocol of the communication port is changed is prevented.
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Fig. 1 is a schematic diagram of an interface multiplexing module verification platform architecture provided in embodiment 1 of the present disclosure.
Detailed Description
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
The embodiments and features of the embodiments in the present application may be combined with each other without conflict.
Example 1:
as shown in fig. 1, embodiment 1 of the present disclosure provides an interface multiplexing module verification platform architecture, which includes:
ahb _ master, ahb _ slave, axi _ master, axi _ slave and apb _ master are integrated at a data end, and after each agent generates random excitation, the random excitation is driven to a DUV (such as a multiplex interface module) through a driver in the agent;
meanwhile, a monitor monitoring module integrated in the agent samples control and data signals on the bus, analyzes the control and data signals into data transactions with byte addresses as units, and directly sends the data transactions to the scoreboard through a pipeline for comparison and verification.
For data ports which are not used in design, the data ports can be shielded in a macro definition mode in a platform environment, and therefore the burden of a CPU (Central processing Unit) processor during the operation of the simulator cannot be increased due to the fact that too many agents are integrated in the platform.
The communication port integrates an autonomous agent meeting a protocol time sequence or a BFM (behavior function Model: behavior level function Model) provided by a third party, a monitor monitoring module is added in the BFM provided by the autonomous agent or the third party to monitor and sample the communication port, the communication port is also analyzed into a data transaction which is unified with the data port and takes a byte address as a unit, and the data transaction is sent to the scoreboard through a pipeline, so that the data transaction which is sent from the data port can be directly compared and checked without being analyzed at the scoreboard or reference Model.
The communication port can integrate a plurality of agents according to the multiplexing mode defined by the interface module, and when different working modes are adopted, the platform calls different agents.
And the cpu _ agent generates random control information according to the design specification of the interface module, configures the random control information to the DUV command port through the reg _ agent, sends an instruction to the agent of each data end through the pipeline and starts data transmission.
reg _ agent also integrates ahb, axi and apb interfaces, and selects one interface to realize register configuration by adopting a macro definition mode according to design.
An interrupt response mechanism is realized in the cpu agent, an interrupt signal generated in the data transmission process is monitored, and corresponding processing is carried out.
Example 2:
the embodiment 2 of the present disclosure provides a method for implementing fast expansion of an interface multiplexing module verification platform architecture, including the following steps:
(1) and establishing interface interfaces required by the command port, the data port and the communication port according to the design specification.
(2) And creating ahb master agent, ahb slave agent, axi master agent, axi slave agent and apb master agent of the data terminals. The driver driving module and the monitor monitoring module are realized mainly by UVM (Universal Verification method), including the functions of generating random excitation with constraint, driving to the interface, monitoring the behavior of the bus interface and the like; and adds a send pipe port that receives the cpu command, and a data transaction send pipe port to the scoreboard.
(3) And if the verification module is a multiplexing interface module, different agents, namely a master agent and a slave agent, can be respectively created according to different multiplexing modes and interface protocols, and the agents are also added to the data transaction transmitting pipeline port sent to the scoreboard.
(4) And establishing a macro definition file, wherein the macro definition file is used for defining selective parameters such as data port macro, command interface type macro and interface multiplexing mode according to design definition.
(5) Creating scoreboard, respectively adding corresponding data transaction receiving pipeline ports aiming at each data end and each communication end agent, and defining corresponding task to realize comparison and verification of data from each pipeline port.
(6) Creating a cpu agent, generating various configurations according with design functions according to design specifications, configuring the DUV through a command port, sending an instruction to a data end agent, generating random excitation to start data transmission, monitoring an interrupt signal of the DUV, and responding according to an interrupt mechanism when interrupt is generated.
(7) Creating env, constructing various agents and scoreboards defined above, defining interactive communication pipelines according to the integrated data end and communication end, and butting the used pipeline ports and pipelines together to ensure that data transactions can correctly circulate in the platform.
(8) The DUV is integrated into the whole design platform through the interface, so that random excitation generated by each agent can be driven to the DUV through the interface, and the response generated by the DUV can be monitored through the monitor in the interface agent.
(9) And constructing a test case, starting a verification platform, calling the verification platform in order according to the constructed agent function, circulating data transactions in the whole verification platform and the DUV, finally collecting the data transactions to scoreboard, and automatically completing verification and comparison work.
This embodiment is through the cpu agent, order end agent, communication end agent and various data end agent, adopt new data transaction transmission mode, the verification platform framework of the multiplexing module of interface has been built, compare with traditional verification platform structure, this platform has portability strong, advantages such as the extension is convenient fast, can be applicable to the verification of most interface class modules, and can be applicable to the verification of other functional modules through only changing a small amount, help verifies that the engineer builds the module verification platform fast, or transplant to other project platforms, the time of verifying the platform and building has been saved greatly, the work efficiency of verifying is improved.
1) Under the interface multiplexing mode, agents with different working modes can be added at the communication end.
2) And replacing the communication end agent with different module items or integrating BFMs provided by a third party, and selecting different data end agents and command interface types through the macro definition file to complete the construction of the verification platform.
The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure, and various modifications and changes may be made to the present disclosure by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.
Claims (10)
1. An interface multiplexing module verification platform architecture is characterized in that a data end integrates multiple agents, and after each agent generates random excitation, the random excitation is driven to a DUV through a driver in the agent;
each agent is integrated with a monitor monitoring module for sampling control and data signals on the bus, analyzing the data signals into data transactions taking unit addresses as units, and directly sending the data transactions to the scoreboard through a pipeline for comparison and verification.
2. The interface multiplexing module validation platform architecture of claim 1, wherein agents integrated at the data side include at least ahb _ master, ahb _ slave, axi _ master, axi _ slave, and apb _ master.
3. The interface multiplexing module validation platform architecture of claim 1, wherein unused data ports in the design are shielded in the platform environment by means defined by the macro.
4. The interface multiplexing module verification platform architecture of claim 1, wherein the communication port integrates a behavior level function model provided by an autonomous agent or a third party that conforms to a protocol timing sequence, and a monitor monitoring module is added to the behavior level function model provided by the autonomous agent or the third party for monitoring and sampling the communication port, analyzing the data transaction into a data transaction unified with the data port and using a unit address as a unit, and sending the data transaction to a scoreboard through a pipeline for comparison and verification.
5. The interface multiplexing module validation platform architecture of claim 4, wherein the communication port is capable of integrating multiple agents according to a multiplexing mode defined by the interface module, and different agents are invoked when different operating modes are employed.
6. The interface multiplexing module validation platform architecture of claim 1, wherein the cpu agent generates random control information according to design specifications of the interface module, configures to the DUV command port through reg _ agent, and sends an instruction to agent of each data end through a pipe to start data transmission.
7. The interface multiplexing module verification platform architecture of claim 6, wherein reg _ agent integrates three interfaces, ahb, axi, and apb, and selects one interface to implement register configuration by macro definition.
8. The interface multiplexing module validation platform architecture of claim 7, wherein the cpu agent implements an interrupt response mechanism, monitors interrupt signals generated during data transmission, and responds according to the interrupt mechanism when an interrupt occurs.
9. A method for realizing quick expansion of an interface multiplexing module verification platform architecture is characterized by comprising the following steps:
step (9-1): establishing interface interfaces required by a command port, a data port and a communication port according to design specifications;
step (9-2): creating data terminals ahb master agent, ahb slave agent, axi master agent, axi slave agent and apb master agent, and adding a sending pipeline port for receiving a cpu instruction and a data transaction sending pipeline port to the scoreboard;
step (9-3): establishing an agent of a communication end, if the verification module is a multiplexing interface module, respectively establishing different agents according to different multiplexing modes and interface protocols, and adding a data transaction sending pipeline port sent to the scoreboard;
step (9-4): establishing a macro definition file, wherein the macro definition file comprises a data port macro definition, a command interface type macro definition and an interface multiplexing mode which are required to be used according to a design definition;
step (9-5): creating a scoreboard, respectively adding corresponding data transaction receiving pipeline ports aiming at each data end and each communication end agent, and defining corresponding tasks to realize comparison and verification of data from each pipeline port;
step (9-6): creating a cpu agent, generating various configurations according with design functions according to design specifications, configuring a DUV through a command port, sending an instruction to a data end agent, generating random excitation to start data transmission, monitoring an interrupt signal of the DUV, and responding according to an interrupt mechanism when interrupt is generated;
step (9-7): creating env, constructing various agents and scoreboards defined above, defining interactive communication pipelines according to an integrated data end and a communication end, and butting the used pipeline ports and pipelines together to ensure that data transactions can correctly circulate in a platform;
step (9-8): integrating the DUV to the whole design platform through the interface, so that random excitation generated by each agent can be driven to the DUV through the interface, and the response generated by the DUV can be monitored through a monitor in the interface agent;
step (9-9): and constructing a test case, starting a verification platform, calling the verification platform in order according to the constructed agent function, circulating data transactions in the whole verification platform and the DUV, finally collecting the data transactions to scoreboard, and automatically completing verification and comparison work.
10. The method for implementing fast expansion of an interface multiplexing module verification platform architecture according to claim 9, wherein in step (9-2), the ahb master agent, ahb slave agent, axi master agent, axislave agent and apb master agent implement a driver driving module and a monitor monitoring module through UVM, and at least include behaviors of generating random stimulus with constraints, driving to an interface, and monitoring a bus interface.
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