CN110880500A - Bidirectional high-voltage ESD protection device of full-symmetry LDMOS trigger SCR structure - Google Patents
Bidirectional high-voltage ESD protection device of full-symmetry LDMOS trigger SCR structure Download PDFInfo
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- 230000002457 bidirectional effect Effects 0.000 title claims abstract description 20
- 238000002347 injection Methods 0.000 claims abstract description 99
- 239000007924 injection Substances 0.000 claims abstract description 99
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 59
- 229920005591 polysilicon Polymers 0.000 claims abstract description 59
- 238000002955 isolation Methods 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 230000003071 parasitic effect Effects 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims description 74
- 230000007704 transition Effects 0.000 claims description 6
- 230000009471 action Effects 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 5
- 230000004888 barrier function Effects 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims 1
- 230000001681 protective effect Effects 0.000 abstract description 5
- 238000002513 implantation Methods 0.000 description 16
- 239000007943 implant Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
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- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
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- 229910052710 silicon Inorganic materials 0.000 description 1
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- 239000000243 solution Substances 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
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- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
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- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
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Abstract
The invention discloses a bidirectional high-voltage ESD protective device of a full-symmetry LDMOS trigger SCR structure, and belongs to the field of electrostatic discharge protection and surge resistance of integrated circuits. The protective device mainly comprises a P substrate, a deep N well, a first P well, an N well, a second P well, a first P + injection region, a first N + injection region, a first polysilicon gate, a first thin gate oxide layer, a first field oxide isolation region, a second P + injection region, a second field oxide isolation region, a second polysilicon gate, a second thin gate oxide layer, a second N + injection region and a third P + injection region. According to the invention, two NLDMOS devices are embedded to form an auxiliary trigger SCR current path in which an open-state NLDMOS device and an off-state NLDMOS device are connected in series, so that the voltage endurance capability of the device is improved, the device meets the ESD protection requirement of a high-voltage power supply domain, the ESD robustness of the device is enhanced, the discharge efficiency of the device in unit area is improved, the base region carrier concentration in a parasitic SCR structure is reduced, and the holding voltage of the device is improved.
Description
Technical Field
The invention relates to a bidirectional ESD or surge protection method, in particular to a bidirectional high-voltage ESD protection device of a full-symmetry LDMOS trigger SCR structure, and belongs to the field of electrostatic discharge protection and surge resistance of integrated circuits.
Background
With the wide application of power semiconductors in the industries of power management, driving circuits, automotive electronics and the like, high-voltage integrated circuits have occupied an important position in the semiconductor industry. Because the working environment of the high-voltage chip is complex and severe, a more complex process level must be added to the high-voltage chip to meet the requirement of a circuit system on high working voltage. However, with the complexity of chip process level and layout, the parasitic effect of the device is gradually increased, and the electrostatic discharge capability is reduced. Therefore, with the increasingly wide application of high-voltage chips, the electrostatic discharge (ESD) protection requirement of the high-voltage integrated circuit is increasingly urgent, and designing a high-voltage ESD protection device with high ESD robustness, high sustain voltage and high discharge efficiency per unit area is an important research direction in the current ESD protection field.
In the field of high-voltage ESD protection, LDMOS (laterally-diffused metal-oxide semiconductor) has been a research hotspot of ESD protection because of its strong voltage-withstanding capability and driving capability. When the LDMOS is used for ESD protection, ESD current is discharged mainly by a parasitic NPN triode, however, the Kirk effect of the device is generated by high-voltage high-current injection, so that the hysteresis amplitude of the device is larger, and the robustness is poorer. Silicon Controlled Rectifiers (SCR) have the advantages of small on-resistance, few parasitic effects, and high discharge efficiency per unit area, and are receiving great attention in ESD or surge protection applications. However, the breakdown voltage of the SCR cannot meet the protection requirement of high-voltage ESD, and both the LDMOS and the SCR can only perform ESD protection in a fixed direction, and cannot meet the requirement of bidirectional ESD protection.
Disclosure of Invention
[ problem ] to
The ESD protection circuit aims at the problem of high-voltage bidirectional ESD protection.
[ solution ]
The invention provides a bidirectional high-voltage ESD protection device with a fully-symmetrical LDMOS trigger SCR structure, which is characterized in that two LDMOS are embedded to form an auxiliary trigger SCR current path in series connection of an on-state NLDMOS and an off-state NLDMOS, wherein a field oxide isolation region can improve the voltage endurance of the device and meet the ESD protection requirements of a circuit on high working voltage and a wide power domain, and the ESD robustness of the device and the discharge efficiency of the device in unit area can be enhanced by utilizing the current conduction path of the SCR structure. The P + injection region embedded in the drain end of the NLDMOS can reduce the base transition carrier concentration in the parasitic SCR structure, and can improve the holding voltage of the device. The completely symmetrical device structure enables the device to realize bidirectional ESD protection or anti-surge functions.
The invention provides a bidirectional high-voltage ESD protective device with a fully-symmetrical LDMOS trigger SCR structure, which mainly comprises a P substrate, a deep N well, a first P well, an N well, a second P well, a first P + injection region, a first N + injection region, a first polysilicon gate, a first thin gate oxide layer, a first field oxygen isolation region, a second P + injection region, a second field oxygen isolation region, a second polysilicon gate, a second thin gate oxide layer, a second N + injection region and a third P + injection region;
a deep N well is arranged in the surface region of the P substrate, the left side edge of the deep N well is connected with the left side edge of the P substrate, and the right side edge of the deep N well is connected with the right side edge of the P substrate;
a first P trap, an N trap and a second P trap are sequentially arranged in the surface region of the deep N trap from left to right, the left side edge of the first P trap is connected with the left side edge of the deep N trap, the right side edge of the first P trap is connected with the left side edge of the N trap, the right side edge of the N trap is connected with the left side edge of the second P trap, and the right side edge of the second P trap is connected with the right side edge of the deep N trap;
a first P + injection region and a first N + injection region are sequentially arranged in a surface region of the first P trap from left to right, a safety distance is arranged between the first P + injection region and the first N + injection region, the first polysilicon gate covers the first thin gate oxide layer and part of the surface region of the first field oxide isolation region, the first polysilicon gate, the first thin gate oxide layer and the first field oxide isolation region which cover the first polysilicon gate cross the surface regions of the first P trap and the N trap, and the right side edge of the first N + injection region is connected with the left side edge of the first polysilicon gate;
a second P + injection region is arranged in the surface region of the N well, and the right side edge of the first field oxide isolation region is connected with the left side edge of the second P + injection region; the second polysilicon gate covers part of the surface regions of the second field oxide isolation region and the second thin gate oxide layer, the second polysilicon gate, the second field oxide isolation region and the second thin gate oxide layer which cover the second polysilicon gate stretch over the surface regions of the N well and the second P well, and the right side edge of the second P + injection region is connected with the left side edge of the second field oxide isolation region;
a second N + injection region and a third P + injection region are sequentially arranged in the surface region of the second P well from left to right, the right side edge of the second polysilicon gate is connected with the left side edge of the second N + injection region, and a safety distance is arranged between the second N + injection region and the third P + injection region;
the first P + injection region is connected with the first metal 1, the first N + injection region is connected with the second metal 1, the first polysilicon gate is connected with the third metal 1, the second polysilicon gate is connected with the fourth metal 1, the second N + injection region is connected with the fifth metal 1, and the third P + injection region is connected with the sixth metal 1;
the first metal 1, the second metal 1 and the third metal 1 are all connected with the first metal 2, and a first electrode is led out from the first metal 2;
the fourth metal 1, the fifth metal 1 and the sixth metal 1 are all connected with the second metal 2, and a second electrode is led out from the second metal 2.
The beneficial technical effects of the invention are as follows:
when the first electrode is under the action of electrical stress, the first P well, the first N + injection region, the first polysilicon gate, the first thin gate oxide layer and the N well which are covered by the first P well and the first polysilicon gate form the open-state NLDMOS, the N well, the second field oxide isolation region, the second polysilicon gate, the second thin gate oxide layer, the second P well and the second N + injection region form the off-state NLDMOS, the first P + injection region, the first P well, the N well, the second P well and the second N + injection region form the SCR current conduction path, and the open-state NLDMOS and the off-state NLDMOS form the current path which is connected with an auxiliary trigger SCR.
According to the protection device, a depletion barrier layer can be formed between the second P + injection region and the N trap, the base region transition carrier concentration in the parasitic SCR structure is reduced, and the holding voltage of the device can be improved.
The cross section structure of the protective device provided by the invention is a layout and circuit structure which is completely symmetrical left and right by taking the second P + injection region (111) as a center, when a forward electrical stress and a reverse electrical stress are applied between a first electrode and a second electrode of the device, the internal electrical property under the action of the forward electrical stress in the device is the same as the internal electrical property under the action of the reverse electrical stress, and the protective device has the functions of bidirectional overvoltage, overcurrent protection or surge resistance.
Drawings
FIG. 1 is a cross-sectional view of the structure of a device of the present invention;
FIG. 2 is a diagram of the metal connections of the device of the present invention;
fig. 3 is a current path of an on-state NLDMOS and an off-state NLDMOS in series-assisted triggering SCR in the device of the present invention;
fig. 4 is a schematic diagram of the SCR current bleed off path in the device of the present invention.
101: p substrate, 102: deep N-well, 103: first P-well, 104: n-well, 105: second P-well, 106: first P + implant region, 107: first N + implant region, 108: first polysilicon gate, 109: first thin gate oxide layer, 110: first field oxide isolation region, 111: second P + implant region, 112: second field oxide isolation region, 113: second polysilicon gate, 114: second thin gate oxide, 115: second N + implant region, 116: a third P + implantation region;
201: first metal 1, 202: second metal 1, 203: third metal 1, 204: fourth metal 1, 205: fifth metal 1, 206: sixth metal 1, 207: first metal 2, 208: a second metal 2;
301: first electrode, 302: a second electrode.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Example 1
The embodiment provides a bidirectional high-voltage ESD protection device with a fully-symmetrical LDMOS trigger SCR structure, wherein two LDMOS devices are embedded to form an auxiliary trigger SCR current path formed by connecting an open-state NLDMOS and an off-state NLDMOS in series, a field oxide isolation region can improve the voltage resistance of the device, the device meets the ESD protection requirement of a high-voltage power supply domain, and the SCR current conduction path can enhance the ESD robustness of the device and improve the discharge efficiency of the device in unit area. The P + injection region embedded into the drain end of the NLDMOS reduces the base transition carrier concentration in the parasitic SCR structure, and can improve the holding voltage of the device. The completely symmetrical device structure enables the device to realize bidirectional ESD protection or anti-surge functions.
Fig. 1 is a schematic structural cross-sectional view of a bidirectional high-voltage ESD protection device in this embodiment, specifically, a bidirectional high-voltage ESD protection device with a fully-symmetric LDMOS triggered SCR structure, which mainly comprises a P substrate 101, a deep N well 102, a first P well 103, an N well 104, a second P well 105, a first P + implantation region 106, a first N + implantation region 107, a first polysilicon gate 108, a first thin gate oxide layer 109, a first field oxide isolation region 110, a second P + implantation region 111, a second field oxide isolation region 112, a second polysilicon gate 113, a second thin gate oxide layer 114, a second N + implantation region 115, and a third P + implantation region 116;
a deep N well 102 is arranged on the surface area of the P substrate 101, the left edge of the deep N well 102 is connected with the left edge of the P substrate 101, and the right edge of the deep N well 102 is connected with the right edge of the P substrate 101;
a first P well 103, an N well 104 and a second P well 105 are sequentially arranged in the surface region of the deep N well 102 from left to right, the left edge of the first P well 103 is connected with the left edge of the deep N well 102, the right edge of the first P well 103 is connected with the left edge of the N well 104, the right edge of the N well 104 is connected with the left edge of the second P well 105, and the right edge of the second P well 105 is connected with the right edge of the deep N well 102;
a first P + injection region 106 and a first N + injection region 107 are sequentially arranged in a surface region of the first P well 103 from left to right, a safety distance is arranged between the first P + injection region 106 and the first N + injection region 107, the first polysilicon gate 108 covers the first thin gate oxide layer 109 and part of the surface region of the first field oxide isolation region 110, the first polysilicon gate 108, the covered first thin gate oxide layer 109 and the covered first field oxide isolation region 110 cross the surface regions of the first P well 103 and the N well 104, and the right edge of the first N + injection region 107 is connected with the left edge of the first polysilicon gate 108;
a second P + injection region 111 is arranged in the surface region of the N-well 104, and the right edge of the first field oxide isolation region 110 is connected with the left edge of the second P + injection region 111; the second polysilicon gate 113 covers part of the surface regions of the second field oxide isolation region 112 and the second thin gate oxide layer 114, the second polysilicon gate 113 and the covered second field oxide isolation region 112 and second thin gate oxide layer 114 cross the surface regions of the N-well 104 and the second P-well 105, and the right edge of the second P + implantation region 111 is connected with the left edge of the second field oxide isolation region 112;
a second N + implantation region 115 and a third P + implantation region 116 are sequentially disposed in the surface region of the second P well 105 from left to right, the right edge of the second polysilicon gate 113 is connected to the left edge of the second N + implantation region 115, and a safety gap is disposed between the second N + implantation region 115 and the third P + implantation region 116.
As shown in fig. 2, the metal connection of the protection device in this embodiment is that a first P + implantation region 106 is connected to a first metal 1201, a first N + implantation region 107 is connected to a second metal 1202, a first polysilicon gate 108 is connected to a third metal 1203, a second polysilicon gate 113 is connected to a fourth metal 1204, a second N + implantation region 115 is connected to a fifth metal 1205, and a third P + implantation region 116 is connected to a sixth metal 1206;
the first metal 1201, the second metal 1202 and the third metal 1203 are all connected with the first metal 2207, and the first electrode 301 is led out of the first metal 2207;
the fourth metal 1204, the fifth metal 1205 and the sixth metal 1206 are all connected with the second metal 2208, and the second electrode 302 is led out of the second metal 2208.
When electrical stress acts on the first electrode 301 of the device of the present invention, the first polysilicon gate 108 is connected to a high potential, so that the NLDMOS composed of the first P-well 103, the first N + injection region 107, the first polysilicon gate 108 and the first thin gate oxide 109 and the N-well 104 covered by the first polysilicon gate 108 is in an on state to generate a weak conduction current channel, the second polysilicon gate 113 is connected to a low potential, the NLDMOS composed of the N-well 104, the second field oxide isolation region 112, the second polysilicon gate 113, the second thin gate oxide 114, the second P-well 105 and the second N + injection region 115 is in an off state, the on state NLDMOS and the off state NLDMOS are connected in series to form an auxiliary trigger SCR current path as shown in fig. 3, wherein the second field oxide isolation region (112) can improve the withstand voltage capability of the device, and the device can meet the ESD protection requirement of the high voltage power domain. The parasitic NPN transistor formed by the first P + injection region 106, the first P well 103, the N well 104, and the second P well 105, and the parasitic PNP transistor formed by the N well 104, the second P well 105, and the second N + injection region 105, are turned on when the LDMOS current reaches a voltage drop of 0.7V over the N well 104 or the second P well 105, so as to form an SCR current conduction path as shown in fig. 4, which can enhance the ESD robustness of the device and improve the discharge efficiency of the device per unit area. A depletion barrier layer can be formed between the second P + injection region 111 and the N-well 104, so as to reduce the base transition carrier concentration in the parasitic SCR structure and improve the holding voltage of the device. The completely symmetrical device structure enables the device to realize bidirectional ESD protection or anti-surge functions.
Although the present invention has been described with reference to the preferred embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (9)
1. A high voltage ESD protection device, characterized by: the LDMOS trigger SCR structure is symmetrical in structure and capable of preventing bidirectional current electrostatic discharge and mainly comprises a P substrate (101), a deep N well (102), a first P well (103), an N well (104), a second P well (105), a first P + injection region (106), a first N + injection region (107), a first polysilicon gate (108), a first thin gate oxide layer (109), a first field oxide isolation region (110), a second P + injection region (111), a second field oxide isolation region (112), a second polysilicon gate (113), a second thin gate oxide layer (114), a second N + injection region (115) and a third P + injection region (116);
a deep N well (102) is arranged on the surface area of the P substrate (101), the left side edge of the deep N well (102) is connected with the left side edge of the P substrate (101), and the right side edge of the deep N well (102) is connected with the right side edge of the P substrate (101);
a first P trap (103), an N trap (104) and a second P trap (105) are sequentially arranged on the surface region of the deep N trap (102) from left to right, the left side edge of the first P trap (103) is connected with the left side edge of the deep N trap (102), the right side edge of the first P trap (103) is connected with the left side edge of the N trap (104), the right side edge of the N trap (104) is connected with the left side edge of the second P trap (105), and the right side edge of the second P trap (105) is connected with the right side edge of the deep N trap (102);
a first P + injection region (106) and a first N + injection region (107) are sequentially arranged in the surface region of the first P well (103) from left to right, a safety distance is arranged between the first P + injection region (106) and the first N + injection region (107), a first polysilicon gate (108) covers the surface regions of a first thin gate oxide layer (109) and a part of a first field oxide isolation region (110), the first polysilicon gate (108) and the first thin gate oxide layer (109) and the first field oxide isolation region (110) which cover the first polysilicon gate (108) cross the surface regions of the first P well (103) and the N well (104), and the right edge of the first N + injection region (107) is connected with the left edge of the first polysilicon gate (108);
a second P + injection region (111) is arranged on the surface region of the N well (104), and the right side edge of the first field oxide isolation region (110) is connected with the left side edge of the second P + injection region (111); a second polysilicon gate (113) covers part of the surface regions of the second field oxide isolation region (112) and the second thin gate oxide layer (114), the second polysilicon gate (113) and the covered second field oxide isolation region (112) and the second thin gate oxide layer (114) cross the surface regions of the N well (104) and the second P well (105), and the right side edge of the second P + injection region (111) is connected with the left side edge of the second field oxide isolation region (112);
a second N + injection region (115) and a third P + injection region (116) are sequentially arranged in the surface region of the second P well (105) from left to right, the right side edge of the second polysilicon gate (113) is connected with the left side edge of the second N + injection region (115), and a safety distance is arranged between the second N + injection region (115) and the third P + injection region (116);
the first P + injection region (106) is connected with the first metal 1(201), the first N + injection region (107) is connected with the second metal 1(202), the first polysilicon gate (108) is connected with the third metal 1(203), the second polysilicon gate (113) is connected with the fourth metal 1(204), the second N + injection region (115) is connected with the fifth metal 1(205), and the third P + injection region (116) is connected with the sixth metal 1 (206);
the first metal 1(201), the second metal 1(202) and the third metal 1(203) are all connected with the first metal 2(207), and a first electrode (301) is led out from the first metal 2 (207);
the fourth metal 1(204), the fifth metal 1(205) and the sixth metal 1(206) are all connected with the second metal 2(208), and the second electrode (302) is led out from the second metal 2 (208).
2. A high voltage ESD protection device as claimed in claim 1, wherein: when the first electrode is acted by an electric stress, the first P well (103), the first N + injection region (107), the first polysilicon gate (108) and the first thin gate oxide layer (109) and the N well (104) which are covered by the first P well (107), the first polysilicon gate (108) and the N well (104) form an open-state NLDMOS, the N well (104), the second field oxide isolation region (112), the second polysilicon gate (113), the second thin gate oxide layer (114), the second P well (105) and the second N + injection region (115) form an off-state NLDMOS, the first P + injection region (106), the first P well (103), the N well (104), the second P well (105) and the second N + injection region (105) form a current conducting path of an SCR, and the open-state NLDMOS and the off-state DMOS form a current path of a series auxiliary trigger SCR, the ESD robustness of the device can be enhanced, the second field oxide isolation region (112) can improve the voltage resistance of the device, and the device can meet the ESD protection requirement of a high-voltage power supply region.
3. A high voltage ESD protection device as claimed in claim 1, wherein: a depletion barrier layer can be formed between the second P + injection region (111) and the N trap (104), and the base transition carrier concentration in the parasitic SCR structure is reduced, so that the holding voltage of the device is improved.
4. A high voltage ESD protection device as claimed in claim 1, wherein: the cross section structure of the device is a layout and a circuit structure which are completely symmetrical left and right by taking the second P + injection region (111) as a center, when a forward electrical stress and a reverse electrical stress are applied between a first electrode and a second electrode of the device, the internal electrical characteristics of the interior of the device under the action of the forward electrical stress are the same as the internal electrical characteristics of the interior of the device under the action of the reverse electrical stress, and the device has the functions of bidirectional overvoltage protection, overcurrent protection or surge resistance.
5. Use of a high voltage ESD protection device according to any of claims 1 to 4 for high voltage ESD protection.
6. An integrated circuit comprising a high voltage ESD protection device according to any of claims 1 to 4.
7. A method of manufacturing a high voltage ESD protection device according to any of claims 1 to 4.
8. A high-voltage ESD protection method is characterized in that two LDMOS are embedded to form an auxiliary trigger SCR current path in series connection of an on-state NLDMOS and an off-state NLDMOS, wherein a field oxide isolation region can improve the voltage endurance of a device and can meet the ESD protection requirements of a circuit on high working voltage and a wide power domain; the base region transition carrier concentration in the parasitic SCR structure can be reduced through the P + injection region embedded in the drain end of the NLDMOS, and the holding voltage of the device can be improved; the completely symmetrical device structure enables the device to realize bidirectional ESD protection or anti-surge functions.
9. The method according to claim 8, wherein a device having the following structure is prepared and used for protection;
the LDMOS trigger SCR structure is symmetrical in structure and capable of preventing bidirectional current electrostatic discharge and mainly comprises a P substrate (101), a deep N well (102), a first P well (103), an N well (104), a second P well (105), a first P + injection region (106), a first N + injection region (107), a first polysilicon gate (108), a first thin gate oxide layer (109), a first field oxide isolation region (110), a second P + injection region (111), a second field oxide isolation region (112), a second polysilicon gate (113), a second thin gate oxide layer (114), a second N + injection region (115) and a third P + injection region (116);
a deep N well (102) is arranged on the surface area of the P substrate (101), the left side edge of the deep N well (102) is connected with the left side edge of the P substrate (101), and the right side edge of the deep N well (102) is connected with the right side edge of the P substrate (101);
a first P trap (103), an N trap (104) and a second P trap (105) are sequentially arranged on the surface region of the deep N trap (102) from left to right, the left side edge of the first P trap (103) is connected with the left side edge of the deep N trap (102), the right side edge of the first P trap (103) is connected with the left side edge of the N trap (104), the right side edge of the N trap (104) is connected with the left side edge of the second P trap (105), and the right side edge of the second P trap (105) is connected with the right side edge of the deep N trap (102);
a first P + injection region (106) and a first N + injection region (107) are sequentially arranged in the surface region of the first P well (103) from left to right, a safety distance is arranged between the first P + injection region (106) and the first N + injection region (107), a first polysilicon gate (108) covers the surface regions of a first thin gate oxide layer (109) and a part of a first field oxide isolation region (110), the first polysilicon gate (108) and the first thin gate oxide layer (109) and the first field oxide isolation region (110) which cover the first polysilicon gate (108) cross the surface regions of the first P well (103) and the N well (104), and the right edge of the first N + injection region (107) is connected with the left edge of the first polysilicon gate (108);
a second P + injection region (111) is arranged on the surface region of the N well (104), and the right side edge of the first field oxide isolation region (110) is connected with the left side edge of the second P + injection region (111); a second polysilicon gate (113) covers part of the surface regions of the second field oxide isolation region (112) and the second thin gate oxide layer (114), the second polysilicon gate (113) and the covered second field oxide isolation region (112) and the second thin gate oxide layer (114) cross the surface regions of the N well (104) and the second P well (105), and the right side edge of the second P + injection region (111) is connected with the left side edge of the second field oxide isolation region (112);
a second N + injection region (115) and a third P + injection region (116) are sequentially arranged in the surface region of the second P well (105) from left to right, the right side edge of the second polysilicon gate (113) is connected with the left side edge of the second N + injection region (115), and a safety distance is arranged between the second N + injection region (115) and the third P + injection region (116);
the first P + injection region (106) is connected with the first metal 1(201), the first N + injection region (107) is connected with the second metal 1(202), the first polysilicon gate (108) is connected with the third metal 1(203), the second polysilicon gate (113) is connected with the fourth metal 1(204), the second N + injection region (115) is connected with the fifth metal 1(205), and the third P + injection region (116) is connected with the sixth metal 1 (206);
the first metal 1(201), the second metal 1(202) and the third metal 1(203) are all connected with the first metal 2(207), and a first electrode (301) is led out from the first metal 2 (207);
the fourth metal 1(204), the fifth metal 1(205) and the sixth metal 1(206) are all connected with the second metal 2(208), and the second electrode (302) is led out from the second metal 2 (208).
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| CN114664816A (en) * | 2022-05-19 | 2022-06-24 | 芯峰科技(广州)有限公司 | Quick-charging electrostatic surge protection circuit with four-trap bidirectional silicon controlled structure |
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