CN110874809A

CN110874809A - Image processing method and device, electronic equipment and storage medium

Info

Publication number: CN110874809A
Application number: CN201810997642.1A
Authority: CN
Inventors: 何安; 李清正; 毛宁元; 刘文志
Original assignee: Shanghai Sensetime Intelligent Technology Co Ltd
Current assignee: Shanghai Sensetime Intelligent Technology Co Ltd
Priority date: 2018-08-29
Filing date: 2018-08-29
Publication date: 2020-03-10

Abstract

The present disclosure relates to an image processing method and apparatus, an electronic device, and a storage medium. The method comprises the following steps: the programmable logic unit reads the block mapping relation and the pixel mapping relation from the memory; the programmable logic unit sequentially reads pixels of local area image blocks in the first image corresponding to each second image block from the memory in a mode of reading second image blocks one by one according to the block mapping relation and stores the pixels into a cache in the programmable logic unit; and when the programmable logic unit reads the pixels of the local area image blocks in the first image corresponding to the next second image block from the memory, the programmable logic unit performs conversion processing on the pixels of the local area image blocks in the first image corresponding to the cache according to the pixel mapping relation to obtain the previous second image block. The embodiment of the disclosure can realize parallel processing of different second image blocks, and improve the processing efficiency of image processing.

Description

Image processing method and device, electronic equipment and storage medium

Technical Field

The present disclosure relates to the field of image processing technologies, and in particular, to an image processing method and apparatus, an electronic device, and a storage medium.

Background

In the field of image processing technology, conventional image processing methods can perform resolution conversion and distortion removal processing on an image. After the image is processed, the image can be used after subsequent processing is carried out according to requirements. The efficiency of image processing is low.

Disclosure of Invention

The present disclosure proposes an image processing technical solution.

According to an aspect of the present disclosure, there is provided an image processing method including:

the programmable logic unit reads the block mapping relation and the pixel mapping relation from the memory;

the programmable logic unit sequentially reads pixels of local area image blocks in the first image corresponding to each second image block from the memory in a mode of reading second image blocks one by one according to the block mapping relation and stores the pixels into a cache in the programmable logic unit; and when the programmable logic unit reads the pixels of the local area image blocks in the first image corresponding to the next second image block from the memory, the programmable logic unit performs conversion processing on the pixels of the local area image blocks in the first image corresponding to the cache according to the pixel mapping relation to obtain the previous second image block.

In a possible implementation manner, the block mapping relationship represents a correspondence relationship between a plurality of second image blocks and local area image blocks in the first image, respectively; the pixel mapping relationship represents a correspondence relationship between pixels in the second image block and pixels in the first image.

In one possible implementation, the method further includes: and the programmable logic unit obtains a third image according to each obtained second image block.

In a possible implementation manner, the number of the second image blocks is determined according to the resolution of the third image, the resolution of the first image, and the cache capacity.

In a possible implementation manner, the size of the local area image block in the first image corresponding to at least two of the plurality of second image blocks is different.

In a possible implementation manner, the image blocks of the local area in the first image corresponding to at least two second image blocks partially overlap.

In a possible implementation manner, the pixel mapping relationship is determined according to the resolution of the third image and the resolution of the first image.

In a possible implementation manner, the pixel mapping relationship is determined according to the resolution of the third image, the resolution of the first image and a distortion removal parameter.

In one possible implementation, the pixel mapping relationship is determined according to a resolution of the third image, a resolution of the first image, a distortion removal parameter, and a rotation parameter.

In one possible implementation, the pixel mapping relationship is determined according to a resolution of the third image, a resolution of the first image, a distortion removal parameter, a rotation parameter, and a scaling parameter.

In a possible implementation manner, the local area image block in the first image is determined according to the mapping relationship among each second image block, the first image, and the pixel.

In a possible implementation manner, the transforming, by the programmable logic unit, pixels of a local area image block in the first image corresponding to the cache according to the pixel mapping relationship to obtain a previous second image block includes:

for a target pixel in the second image block, the programmable logic unit extracts, according to the pixel mapping relationship, a pixel value of an associated pixel in a local area image block in the first image corresponding to the second image block in the cache, where the target pixel is any pixel in the second image block, and the associated pixel is a pixel in the local area image block in the first image corresponding to the second image block and having an association relationship with the target pixel;

the programmable logic unit obtains the pixel value of the target pixel according to the pixel value of the associated pixel;

and the programmable logic unit obtains the second image block according to the pixel value of the target pixel.

In a possible implementation manner, the obtaining, by the programmable logic unit, the pixel value of the target pixel according to the pixel value of the associated pixel includes:

and the programmable logic unit carries out interpolation processing based on the pixel value of the associated pixel to obtain the pixel value of the target pixel.

In one possible implementation, a plurality of associated pixels corresponding to at least one of the target pixels are distributed discretely on the first image.

In one possible implementation, the method further includes:

and the programmable logic unit reports a hardware interrupt signal to a CPU according to the obtained third image so that the CPU starts the processing of the next image.

In one possible implementation, the method further includes:

the preprocessing module takes or processes the image collected by the camera as a first image and stores the first image into the memory.

In one possible implementation, the camera includes: fisheye camera.

According to an aspect of the present disclosure, there is provided an image processing apparatus, the apparatus including:

the memory is used for storing the block mapping relation and the pixel mapping relation;

the programmable logic unit is provided with a cache and is used for reading the block mapping relation and the pixel mapping relation from the memory; sequentially reading pixels of local area image blocks in the first image corresponding to each second image block from the memory in a mode of reading second image blocks one by one according to the block mapping relation and storing the pixels into a cache in the programmable logic unit; and when the programmable logic unit reads the pixels of the local area image blocks in the first image corresponding to the next second image block from the memory, the programmable logic unit performs conversion processing on the pixels of the local area image blocks in the first image corresponding to the cache according to the pixel mapping relation to obtain the previous second image block.

In one possible implementation, the apparatus further includes: and the merging module is used for obtaining a third image from each obtained second image block.

In one possible implementation, the apparatus further includes a CPU:

In one possible implementation, the apparatus further includes:

and the preprocessing module is used for taking or processing the image acquired by the camera as a first image and storing the first image into the memory.

In one possible implementation, the apparatus further includes: at least one said camera.

In one possible implementation, the at least one camera includes: fisheye camera.

According to an aspect of the present disclosure, there is provided an electronic device including:

a processor;

a memory for storing processor-executable instructions;

wherein the processor is configured to: any of the image processing methods described above is performed.

According to an aspect of the present disclosure, there is provided a computer readable storage medium having stored thereon computer program instructions which, when executed by a processor, implement any of the image processing methods described above.

In this disclosure, the programmable logic unit may read the block mapping relationship and the pixel mapping relationship from the memory, and the programmable logic unit may perform, during the process of reading the pixels of the local area image block in the first image corresponding to one second image block, the conversion processing of the last second image block that has been read. The programmable logic unit in the embodiment of the disclosure can implement parallel processing on different second image blocks, and improve the processing efficiency of image processing.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the disclosure.

FIG. 1 shows a flow diagram of an image processing method according to an embodiment of the present disclosure;

FIG. 2 shows a flow diagram of an image processing method according to an embodiment of the present disclosure;

fig. 3 shows a flowchart of step S20 in the image processing method according to an embodiment of the present disclosure;

FIG. 4 shows a flow diagram of an image processing method according to an embodiment of the present disclosure;

fig. 5 shows a block diagram of an image processing apparatus according to an embodiment of the present disclosure;

fig. 6 shows a block diagram of an image processing apparatus according to an embodiment of the present disclosure;

FIG. 7 is a block diagram illustrating an electronic device in accordance with an exemplary embodiment;

FIG. 8 is a block diagram illustrating an electronic device in accordance with an example embodiment.

Detailed Description

Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers can indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

The term "and/or" herein is merely an association describing an associated object, meaning that three relationships may exist, e.g., a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of A, B, C, and may mean including any one or more elements selected from the group consisting of A, B and C.

Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the present disclosure.

Fig. 1 illustrates a flowchart of an image processing method according to an embodiment of the present disclosure, which includes, as illustrated in fig. 1:

in step S10, the programmable logic unit reads the block mapping relationship and the pixel mapping relationship from the memory.

In one possible implementation, the Programmable logic unit is an FPGA (Field Programmable gate array). The user can design the program according to the use requirement and deploy the program in the programmable logic unit to realize the personalized application. In various types of image processing processes such as resolution conversion and distortion removal on an image, the image can be divided into different image blocks, and the image blocks can be processed in parallel by using an editable logic unit so as to improve the efficiency of image processing.

In one possible implementation, the memory may be various types of memories such as a DDR (Double Data Rate) memory. The image to be processed may be stored in the memory as the first image. The first image may be an original image captured by a camera. According to different types, shooting parameters and processing requirements of the camera, different image processing can be carried out on the first image so as to obtain a corrected image meeting the requirements. Various image processing such as resolution adjustment and distortion removal processing can be performed on the image. For example, when the resolution of the first image is different from the required image resolution, resolution adjustment may be performed on the first image to obtain a processed image that meets the requirements.

In one possible implementation, for the first image with different resolutions and different image processing requirements, different mapping relationships exist between pixels in the processed image and pixels in the first image. For a first image to be processed, according to parameters such as the resolution of the first image and a given resolution after processing, the pixels in the first image can be transformed to obtain the pixels in the processed image. A pixel value in the processed image may be derived from pixel values of a plurality of pixels in the first image. The processed image may be divided into a plurality of second image blocks, and the programmable logic unit may be used to transform the first image and then sequentially obtain the second image blocks. And the corresponding relation exists between the pixels in each second image block and the pixels in the first image. A pixel mapping relationship may be constructed according to a correspondence relationship between pixels in each second image block and pixels in the first image.

In a possible implementation manner, the second image block may be a square, and the side length of the second image block may be N powers of 2, so as to facilitate subsequent calculation.

In a possible implementation manner, local area image blocks corresponding to the second image blocks may be determined in the first image according to the second image blocks, the first image and the pixel mapping relationship. The block mapping relationship may be constructed according to a correspondence between each second image block and a local area image block corresponding thereto in the first image.

In a possible implementation manner, different pixel mapping relationships and block mapping relationships may be constructed and stored in the memory according to the resolution before image processing, the resolution after image processing, the number of blocks, and other image processing parameters. When a first image needs to be subjected to image processing, the corresponding pixel mapping relationship and block mapping relationship can be extracted from the memory according to the resolution of the first image and the required image processing parameters, and then the image processing is performed. For example, the resolution a1 before image processing, the resolution B1 after image processing, and the number of blocks C1 may be stored in the memory after the pixel mapping 1 and the block mapping 1 are constructed. For the resolution a2 before image processing, the resolution B2 after image processing, the number of blocks C2, and the distortion removal parameter D2 may be stored in the memory after the pixel mapping relationship 2 and the block mapping relationship 2 are constructed.

In one possible implementation, the editable logic unit may read the block mapping relationship and the pixel mapping relationship associated with the image processing requirement of the first image to the memory. For example, the size of the first image a is M × N (unit is pixel, the same applies below), the size of the processed image is 64 × 64 (unit is pixel, the same applies below), and the number of blocks is 4. The editable logic unit can read the corresponding block mapping relation and pixel mapping relation in the memory to perform image processing on the first image a. The size of each second image block after blocking is 32 × 32. If the processed image size is not a multiple of 32, the remaining portions in the horizontal and vertical directions may be processed as a single block. E.g., 72x70, then the number of tiles is 9, the size of the 3 rd and 6 th tiles is 8x32, the size of the 3 th to 9 th tiles is 8x6, and the size of the remaining tiles is 32x 32. For any second image block, the local area image block corresponding to the second image block in the first image may be determined according to the block mapping relationship, and the pixel value of the pixel in each second image block may be determined according to the pixel mapping relationship and the pixel value of the pixel in the first image.

In one possible implementation, the programmable logic unit may read the block mapping relationship and the pixel mapping relationship from the memory and store the block mapping relationship and the pixel mapping relationship in the cache.

Step S20, the programmable logic unit sequentially reads pixels of local area image blocks in the first image corresponding to each second image block from the memory in a manner of reading second image blocks one by one according to the block mapping relationship, and stores the pixels in a cache in the programmable logic unit; and when the programmable logic unit reads the pixels of the local area image blocks in the first image corresponding to the next second image block from the memory, the programmable logic unit performs conversion processing on the pixels of the local area image blocks in the first image corresponding to the cache according to the pixel mapping relation to obtain the previous second image block.

In one possible implementation, the parallel processing of the second image block in the image processing of the embodiment of the present disclosure may be implemented by using a programmable logic unit. When the pixels of the local area image block in the first image corresponding to one second image block are read, image processing such as resolution adjustment and distortion removal processing can be performed on the pixels of another second image block in the cache, parallel processing among different second image blocks is achieved, and the speed and efficiency of image processing are improved.

For example, the first image a is subjected to image processing, and the processed image is divided into four second image blocks. The programmable logic unit may read, in the memory, pixels of the local area image block in the first image corresponding to the first second image block according to the block mapping relationship, and store the pixels in the cache. After the pixels of the local area image block in the first image corresponding to the first second image block are completely read, the programmable logic unit may read the pixels of the local area image block in the first image corresponding to the second image block in the memory according to the block mapping relationship and store the pixels in the cache, and the programmable logic unit may perform transformation processing, for example, various image processing such as resolution adjustment and distortion removal processing, on the pixels of the local area image block in the first image corresponding to the first second image block stored in the cache according to the pixel mapping relationship to obtain the first second image block.

After the pixels of the local area image block in the first image corresponding to the second image block are completely read, the programmable logic unit may read the pixels of the local area image block in the first image corresponding to the third second image block in the memory according to the block mapping relationship and store the pixels in the cache, and the programmable logic unit may perform transformation processing, such as resolution adjustment and distortion removal processing, on the pixels of the local area image block in the first image corresponding to the second image block stored in the cache according to the pixel mapping relationship to obtain the second image block. And the rest is repeated until a fourth second image block is obtained.

In this embodiment, the programmable logic unit may read the block mapping relationship and the pixel mapping relationship from the memory, and the programmable logic unit may perform, during the process of reading the pixels of the local area image block in the first image corresponding to one second image block, the conversion processing of the last second image block that has been read. The programmable logic unit in the embodiment of the disclosure can implement parallel processing on different second image blocks, and improve the processing efficiency of image processing.

Fig. 2 shows a flowchart of an image processing method according to an embodiment of the present disclosure, which further includes, as shown in fig. 2:

in step S30, the programmable logic unit obtains a third image according to each obtained second image block.

In a possible implementation manner, the second image blocks may be combined to obtain a third image, where the third image is a processed image. When the processed image needs to be output or displayed, the second image blocks can be sequentially output or displayed, and a third image can be obtained according to the second image blocks and then output or displayed.

In this embodiment, the programmable logic unit obtains a third image according to each obtained second image block. The second images may be combined to obtain a third image after image processing. The third image may be output or presented to facilitate subsequent use of the image processing.

In a possible implementation manner, during the process of image processing on the first image, the processed image, that is, the third image may be divided into different numbers of second image blocks. When the resolution of the third image and/or the resolution of the first image are/is higher, the calculation amount of the image block processing is large, and the third image can be divided into a larger number of second image blocks so as to improve the parallel efficiency of the image processing. When the cache capacity is smaller, the programmable logic unit can read a smaller number of pixels of the image block in the local area in the first image at a time, and can also divide the third image into a larger number of second image blocks, so as to avoid the reduction of the image processing efficiency caused by the insufficient processing capability of the programmable logic unit. The number of second image blocks may be determined according to a combination of at least two of a resolution of the third image, a resolution of the first image, and a buffer capacity.

In this embodiment, the number of the second image blocks may be determined according to the resolution of the third image, the resolution of the first image, and the buffer capacity. The number of the second image blocks can be determined according to different image processing requirements and application scenes, so that the image processing efficiency is improved, and the real-time performance of image processing is improved.

In a possible implementation manner, the third image may be divided into a plurality of second image blocks with the same size, or the third image may be divided into a plurality of second image blocks with different sizes. The present disclosure is not limited thereto.

In one possible implementation, one pixel in the second image block may correspond to a plurality of discretely distributed pixels in the local area image block in the first image. When the sizes of the second image blocks are the same or different, the sizes of the local area image blocks in the first image corresponding to the second image blocks may be different, and the local area image blocks in the first image corresponding to at least two second image blocks are partially overlapped.

In this embodiment, the size of the local area image blocks in the first image corresponding to at least two of the plurality of second image blocks is different, and different local area image blocks are partially overlapped. Partial overlapping exists between the image blocks of the local areas in the first images with different sizes, and the partial overlapping can be used for accurately calculating the corresponding second image blocks.

In one possible implementation, a pixel may be considered to be a non-repartitionable unit or element in an image. The resolution of an image refers to the precision of the image screen, and may include how many pixels are displayed when the image is displayed. Points, lines and planes on the image may all be made up of pixels. The higher the resolution of the image, the more pixels of the image, the finer the picture displayed by the image, and the more information that can be displayed in the same image area. Image processing includes adjusting the resolution of the image. The pixel mapping relationship may be determined according to a resolution of the first image and a resolution of the third image.

In a possible implementation manner, the first image may be subjected to image processing for adjusting the resolution according to a pixel mapping relationship determined by the resolution of the third image and the resolution of the first image, so as to obtain a third image with a resolution meeting the requirement.

In the present embodiment, the pixel mapping relationship is determined according to the resolution of the third image and the resolution of the first image. According to the pixel mapping relation determined by the resolution of the first image and the third image, the resolution of the image can be adjusted according to the determined pixel mapping relation.

In one possible implementation, the distortion of the image refers to deformation such as squeezing, stretching, shifting, and twisting of the geometric position of the image pixel with respect to a reference system (ground actual position or topographic map) during imaging of the image, including during capturing with a capturing device to generate the image, or during rendering by a creator to render the image, such that the geometric position, size, shape, orientation, and the like of the image pixel are changed. During image processing, the distortion of the input image may be image processed to obtain an output image such that the geometric location, size, shape, orientation, etc. of the output image pixels are not distorted with respect to the reference system. The distortion parameter of the image may include a parameter for performing distortion correction on the image, and for example, may include a radial distortion parameter, a tangential distortion parameter, and the like.

In a possible implementation manner, a sample image with the same resolution as the first image may be subjected to a distortion removal process according to the resolution of the first image, the resolution of the third image, and a distortion removal parameter, so as to obtain a distortion-removed image. A pixel mapping relationship may be determined from the undistorted image and the sample image. Resolution adjustment and distortion removal can be simultaneously performed on the image according to the determined pixel mapping relationship.

In this embodiment, the pixel mapping relationship may be determined according to the resolution of the third image, the resolution of the first image, and the distortion removal parameter, and resolution adjustment and distortion removal processing may be performed on the image simultaneously using the pixel mapping relationship.

In one possible implementation, the rotation of the image refers to the rotation of the geometric position of the image pixels relative to the reference system during the imaging of the image. During image processing, the input image may be image processed to obtain an output image such that the geometric positions of the pixels of the output image are not rotated with respect to the reference system. The rotation parameters of the image may include a rotation angle parameter, and the like.

In a possible implementation manner, a sample image with the same resolution as that of the first image may be subjected to a distortion removal process according to the resolution of the third image, the resolution of the first image, and a distortion removal parameter, so as to obtain a distortion-removed image. The rotation parameter can be used for carrying out rotation processing on the distortion-removed image to obtain a rotation image. The pixel mapping relationship may be determined from the rotated image and the sample image. Resolution adjustment, distortion removal processing and rotation processing can be simultaneously performed on the image according to the determined pixel mapping relation.

In this embodiment, the pixel mapping relationship may be determined according to the resolution of the third image, the resolution of the first image, the distortion removal parameter, and the rotation parameter. Resolution adjustment, distortion removal and rotation processing can be simultaneously performed on the image according to the determined pixel mapping relation.

In one possible implementation, the image may be subjected to an enlargement process or a reduction process. The first image may be down-sampled or down-sampled to obtain a reduced third image. The first image may be upsampled or interpolated to obtain an enlarged third image.

In a possible implementation manner, a sample image with the same resolution as that of the first image may be subjected to a distortion removal process according to the resolution of the third image, the resolution of the first image, and a distortion removal parameter, so as to obtain a distortion-removed image. The rotation parameter can be used for carrying out rotation processing on the distortion-removed image to obtain a rotation image. The scaling processing can be performed on the rotation image according to the scaling parameters to obtain a scaled image. The pixel mapping relationship may be determined from the scaled image and the sample image. Resolution adjustment, distortion removal processing, rotation processing and scaling processing can be simultaneously performed on the image according to the determined pixel mapping relationship.

In the present embodiment, the pixel mapping relationship is determined according to the resolution of the third image, the resolution of the first image, the distortion removal parameter, the rotation parameter, and the scaling parameter. Resolution adjustment, distortion removal, rotation and scaling can be simultaneously performed on the image according to the determined pixel mapping relation.

Fig. 3 shows a flowchart of step S20 in the image processing method according to the embodiment of the present disclosure, and as shown in fig. 3, step S20 in the image processing method includes:

step S21, for a target pixel in the second image block, the programmable logic unit extracts, according to the pixel mapping relationship, a pixel value of an associated pixel in a local area image block in the first image corresponding to the second image block in the cache, where the target pixel is any pixel in the second image block, and the associated pixel is a pixel in the local area image block in the first image corresponding to the second image block and having an association relationship with the target pixel.

In one possible implementation, an image coordinate system may be established, coordinate values of the target pixel in the image coordinate system of the second image block may be obtained, and coordinate values of the associated pixel in the image coordinate system of the first image may be obtained. The pixel mapping relationship may include a correspondence relationship between the coordinate values of the target pixel and the coordinate values of the associated pixel. According to the coordinates of the target pixel and the pixel mapping relation, the coordinates of the associated pixel can be determined.

In one possible implementation, the pixels of the second image block and the pixels of the first image may be identified, and the pixels may be identified by at least one of letters, numbers or symbols. The pixel mapping relationship may comprise a correspondence between an identification of the target pixel and an identification of the associated pixel. According to the identification of the target pixel and the pixel mapping relation, the identification of the associated pixel can be determined.

In one possible implementation, a plurality of associated pixels corresponding to at least one of the target pixels are distributed discretely on the first image. In the pixel mapping relationship, one target pixel may correspond to one or more associated pixels, and the associated pixels are discretely distributed. The discrete distribution among a plurality of associated pixels corresponding to the target pixel is common in the presence of image distortion and the like. The buffer capacity set by the FPGA is usually limited, and if the FPGA reads pixel by pixel in the conventional row/column scanning manner, the FPGA needs to wait for a longer data reading time to process the data, so that the efficiency is low, and the requirement of data processing real-time performance cannot be met. Due to the fact that the associated pixels of part or all of the pixels are distributed discretely, the FPGA acquires data of a certain image block from the DDR by taking the image block as granularity (instead of taking the pixels as the granularity), and data reading efficiency can be improved; for the data which is read into the FPGA cache, the FPGA can perform post-processing such as pixel value determination of a target pixel, and meanwhile, the FPGA can also acquire the data of the next image block from the DDR at the same time, so that the parallel processing efficiency is improved, and the requirement of data processing real-time property can be met.

In step S22, the programmable logic unit obtains the pixel value of the target pixel according to the pixel value of the associated pixel.

In one possible implementation, the pixel values comprise color values or grayscale values. The color value may include an RGB (RED GREEN BLUE) value, among others.

In one possible implementation, when the target pixel corresponds to a plurality of associated pixels, an average value, a maximum value, or a minimum value of pixel values of the plurality of associated pixels may be determined as the pixel value of the target pixel. The pixel value of one of the associated pixels corresponding to the target pixel may also be determined as the pixel value of the target pixel.

In one possible implementation, step S22 includes:

In one possible implementation, the interpolation method includes inputting the value of the known point into a specific function, and determining an approximate value of the unknown point according to the function value output by the specific function. The pixel value of the target pixel may be obtained by using a preset interpolation function according to the pixel value of the associated pixel of the target pixel. The present disclosure does not limit the concrete representation of the interpolation function.

In one possible implementation, the pixel value of the target pixel may be obtained by using a bilinear interpolation method according to the value of the associated pixel. For example, according to the mapping relationship, the coordinates of four associated pixels corresponding to the target pixel 1 may be determined as: x (n) y (m), x (n +1) y (m), x (n) y (m +1), and x (n +1) y (m + 1). The pixel value of the target pixel 1 on the output image can be calculated in the input image by using a bilinear interpolation method according to the pixel values of the pixels on the four coordinates. Interpolation processing is carried out according to the pixel values of the related pixels, so that the pixel value of the target pixel can be more accurate, and the output image is more real.

In step S23, the programmable logic unit obtains the second image block according to the pixel value of the target pixel.

In a possible implementation manner, the second image block may be obtained according to a pixel value of a target pixel in the second image block.

In this embodiment, the pixel value of the target pixel in the second image block may be obtained according to the pixel value of the associated pixel. The pixel value of the target pixel calculated according to the pixel value of the associated pixel can ensure that the image processing effect is real and reliable.

Fig. 4 shows a flowchart of an image processing method according to an embodiment of the present disclosure, which further includes, as shown in fig. 4:

and step S40, the programmable logic unit reports a hardware interrupt signal to a CPU according to the obtained third image, so that the CPU starts the processing of the next image.

In a possible implementation, after the third image is obtained by the programmable logic unit, it may be considered that the image processing of the current first image is completed, and the image processing of the next image may be performed. The programmable logic unit may report a hardware interrupt signal to the CPU to notify the CPU that the image processing of the current first image has been completed. The CPU may start a corresponding program to perform image processing of the next image. The next image may be read from memory, for example.

In this embodiment, the programmable logic unit may report a hardware interrupt signal to the CPU, so that the CPU starts processing of a next image. The hardware interrupt signal can simply and quickly inform the CPU that the processing of the current first image is finished.

In one possible implementation, the image processing method further includes:

In a possible implementation manner, the image acquired by the camera may be stored in the memory as the first image by using the preprocessing module. The images collected by the camera can be stored in the memory after preprocessing such as splicing and duplicate removal.

In one possible implementation, the camera comprises a fisheye camera.

In a possible implementation manner, images captured by a plurality of fisheye cameras may be merged and then stored in the memory. For the overlapped parts of the images shot by different fisheye cameras, the first image can be obtained after the duplication elimination processing and stored in the memory.

Application example:

1. and determining to divide the third image into N second image blocks according to the resolution of the first image (to-be-processed image), the resolution of the third image (processed image) and the buffer capacity of the programmable logic unit.

2. The memory is pre-stored with a plurality of block mapping relationships and pixel mapping relationships. The block mapping relationship and the pixel mapping relationship may be obtained according to the method in the above embodiment. And determining a block mapping relation and a pixel mapping relation required for image processing on the first image according to the number N of the second image blocks, the resolution of the first image, the resolution of the third image and image processing parameters (including a distortion removal parameter, a rotation parameter or a scaling parameter and the like). The programmable logic unit can read the required block mapping relation and pixel mapping relation in the memory.

3. The programmable logic unit sequentially reads pixels of the image blocks in the local area in the first image corresponding to each second image block from the memory in a mode of reading the image blocks one by one according to the read block mapping relation and stores the pixels in the cache; and when the programmable logic unit reads the pixels of the local area image block in the first image corresponding to the next second image block from the memory, the programmable logic unit performs conversion processing on the pixels of the local area image block in the first image corresponding to the cache according to the pixel mapping relation to obtain the previous second image block. And the programmable logic unit sequentially processes each second image block until each second image block is obtained.

4. And the programmable logic unit obtains a third image according to each obtained second image block.

It is understood that the above-mentioned method embodiments of the present disclosure can be combined with each other to form a combined embodiment without departing from the logic of the principle, which is limited by the space, and the detailed description of the present disclosure is omitted.

In addition, the present disclosure also provides an image processing apparatus, an electronic device, a computer-readable storage medium, and a program, which can be used to implement any one of the image processing methods provided by the present disclosure, and the descriptions and corresponding descriptions of the corresponding technical solutions and the corresponding descriptions in the methods section are omitted for brevity.

It will be understood by those skilled in the art that in the method of the present invention, the order of writing the steps does not imply a strict order of execution and any limitations on the implementation, and the specific order of execution of the steps should be determined by their function and possible inherent logic.

Fig. 5 illustrates a block diagram of an image processing apparatus according to an embodiment of the present disclosure, which includes, as illustrated in fig. 5:

a memory 10 for storing a block mapping relationship and a pixel mapping relationship;

the programmable logic unit 20 is provided with a cache 21 and is used for reading a block mapping relation and a pixel mapping relation from a memory; sequentially reading pixels of the local area image blocks in the first image corresponding to each second image block from the memory in a mode of reading the second image blocks one by one according to the block mapping relationship and storing the pixels into a cache 21 in the programmable logic unit; when the programmable logic unit 20 reads the pixels of the local area image block in the first image corresponding to a next second image block from the memory 10, the programmable logic unit 20 performs transformation processing on the pixels of the local area image block in the first image corresponding to the cache according to the pixel mapping relationship to obtain a previous second image block.

Fig. 6 shows a block diagram of an image processing apparatus according to an embodiment of the present disclosure, as shown in fig. 6, in one possible implementation, the apparatus further includes:

and the merging module 30 is configured to obtain a third image from each obtained second image block.

In a possible implementation manner, the transforming, by the programmable logic unit 20, the pixels of the local area image block in the first image corresponding to the cache 21 according to the pixel mapping relationship to obtain the previous second image block includes:

for a target pixel in the second image block, the programmable logic unit 20 extracts, according to the pixel mapping relationship, a pixel value of an associated pixel in a local area image block in the first image corresponding to the second image block in the cache 21, where the target pixel is any pixel in the second image block, and the associated pixel is a pixel in the local area image block in the first image corresponding to the second image block and having an association relationship with the target pixel;

the programmable logic unit 20 obtains the pixel value of the target pixel according to the pixel value of the associated pixel;

the programmable logic unit 20 obtains the second image block according to the pixel value of the target pixel.

In a possible implementation manner, the obtaining, by the programmable logic unit 20, the pixel value of the target pixel according to the pixel value of the associated pixel includes:

the programmable logic unit 20 performs interpolation processing based on the pixel value of the associated pixel to obtain the pixel value of the target pixel.

In one possible implementation, the apparatus further includes the CPU 40:

the programmable logic unit 20 reports a hardware interrupt signal to the CPU40 according to the obtained third image, so that the CPU40 starts processing of a next image.

In one possible implementation, the apparatus further includes:

and the preprocessing module 50 is configured to take or process the image acquired by the camera 60 as a first image and store the first image in the memory 10.

In one possible implementation, the apparatus further includes: at least one of said cameras 60.

In one possible implementation, the at least one camera 60 includes: fisheye camera.

In some embodiments, functions of or modules included in the apparatus provided in the embodiments of the present disclosure may be used to execute the method described in the above method embodiments, and for specific implementation, reference may be made to the description of the above method embodiments, and for brevity, details are not described here again

Embodiments of the present disclosure also provide a computer-readable storage medium having stored thereon computer program instructions, which when executed by a processor, implement the above-mentioned method. The computer readable storage medium may be a non-volatile computer readable storage medium.

An embodiment of the present disclosure further provides an electronic device, including: a processor; a memory for storing processor-executable instructions; wherein the processor is configured as the above method.

The electronic device may be provided as a terminal, server, or other form of device.

Fig. 7 is a block diagram illustrating an electronic device 800 in accordance with an example embodiment. For example, the electronic device 800 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, or the like terminal.

Referring to fig. 7, electronic device 800 may include one or more of the following components: processing component 802, memory 804, power component 806, multimedia component 808, audio component 810, input/output (I/O) interface 812, sensor component 814, and communication component 816.

The processing component 802 generally controls overall operation of the electronic device 800, such as operations associated with display, telephone calls, data communications, camera operations, and recording operations. The processing components 802 may include one or more processors 820 to execute instructions to perform all or a portion of the steps of the methods described above. Further, the processing component 802 can include one or more modules that facilitate interaction between the processing component 802 and other components. For example, the processing component 802 can include a multimedia module to facilitate interaction between the multimedia component 808 and the processing component 802.

The memory 804 is configured to store various types of data to support operations at the electronic device 800. Examples of such data include instructions for any application or method operating on the electronic device 800, contact data, phonebook data, messages, pictures, videos, and so forth. The memory 804 may be implemented by any type or combination of volatile or non-volatile memory devices such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disks.

The power supply component 806 provides power to the various components of the electronic device 800. The power components 806 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 800.

The multimedia component 808 includes a screen that provides an output interface between the electronic device 800 and a user. In some embodiments, the screen may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive an input signal from a user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundary of a touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 808 includes a front facing camera and/or a rear facing camera. The front camera and/or the rear camera may receive external multimedia data when the electronic device 800 is in an operation mode, such as a shooting mode or a video mode. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

The audio component 810 is configured to output and/or input audio signals. For example, the audio component 810 includes a Microphone (MIC) configured to receive external audio signals when the electronic device 800 is in an operational mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signals may further be stored in the memory 804 or transmitted via the communication component 816. In some embodiments, audio component 810 also includes a speaker for outputting audio signals.

The I/O interface 812 provides an interface between the processing component 802 and peripheral interface modules, which may be keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to: a home button, a volume button, a start button, and a lock button.

The sensor assembly 814 includes one or more sensors for providing various aspects of state assessment for the electronic device 800. For example, the sensor assembly 814 may detect an open/closed state of the electronic device 800, the relative positioning of components, such as a display and keypad of the electronic device 800, the sensor assembly 814 may also detect a change in the position of the electronic device 800 or a component of the electronic device 800, the presence or absence of user contact with the electronic device 800, orientation or acceleration/deceleration of the electronic device 800, and a change in the temperature of the electronic device 800. Sensor assembly 814 may include a proximity sensor configured to detect the presence of a nearby object without any physical contact. The sensor assembly 814 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 814 may also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

The communication component 816 is configured to facilitate wired or wireless communication between the electronic device 800 and other devices. The electronic device 800 may access a wireless network based on a communication standard, such as WiFi, 2G or 3G, or a combination thereof. In an exemplary embodiment, the communication component 816 receives a broadcast signal or broadcast related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 816 further includes a Near Field Communication (NFC) module to facilitate short-range communications. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID) technology, infrared data association (IrDA) technology, Ultra Wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

In an exemplary embodiment, the electronic device 800 may be implemented by one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), controllers, micro-controllers, microprocessors or other electronic components for performing the above-described methods.

In an exemplary embodiment, a non-transitory computer-readable storage medium, such as the memory 804, is also provided that includes computer program instructions executable by the processor 820 of the electronic device 800 to perform the above-described methods.

Fig. 8 is a block diagram illustrating an electronic device 1900 in accordance with an example embodiment. For example, the electronic device 1900 may be provided as a server. Referring to fig. 8, electronic device 1900 includes a processing component 1922 further including one or more processors and memory resources, represented by memory 1932, for storing instructions, e.g., applications, executable by processing component 1922. The application programs stored in memory 1932 may include one or more modules that each correspond to a set of instructions. Further, the processing component 1922 is configured to execute instructions to perform the above-described method.

The electronic device 1900 may also include a power component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input/output (I/O) interface 1958. The electronic device 1900 may operate based on an operating system stored in memory 1932, such as Windows Server, Mac OS XTM, UnixTM, LinuxTM, FreeBSDTM, or the like.

In an exemplary embodiment, a non-transitory computer readable storage medium, such as the memory 1932, is also provided that includes computer program instructions executable by the processing component 1922 of the electronic device 1900 to perform the above-described methods.

The present disclosure may be systems, methods, and/or computer program products. The computer program product may include a computer-readable storage medium having computer-readable program instructions embodied thereon for causing a processor to implement various aspects of the present disclosure.

The computer readable storage medium may be a tangible device that can hold and store the instructions for use by the instruction execution device. The computer readable storage medium may be, for example, but not limited to, an electronic memory device, a magnetic memory device, an optical memory device, an electromagnetic memory device, a semiconductor memory device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a Static Random Access Memory (SRAM), a portable compact disc read-only memory (CD-ROM), a Digital Versatile Disc (DVD), a memory stick, a floppy disk, a mechanical coding device, such as punch cards or in-groove projection structures having instructions stored thereon, and any suitable combination of the foregoing. Computer-readable storage media as used herein is not to be construed as transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., optical pulses through a fiber optic cable), or electrical signals transmitted through electrical wires.

The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to a respective computing/processing device, or to an external computer or external storage device via a network, such as the internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. The network adapter card or network interface in each computing/processing device receives computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium in the respective computing/processing device.

The computer program instructions for carrying out operations of the present disclosure may be assembler instructions, Instruction Set Architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, the electronic circuitry that can execute the computer-readable program instructions implements aspects of the present disclosure by utilizing the state information of the computer-readable program instructions to personalize the electronic circuitry, such as a programmable logic circuit, a Field Programmable Gate Array (FPGA), or a Programmable Logic Array (PLA).

Various aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions. These computer-readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer-readable medium storing the instructions comprises an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.

The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions/acts specified in the flowchart and/or block diagram block or blocks.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Having described embodiments of the present disclosure, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein were chosen in order to best explain the principles of the embodiments, the practical application, or technical improvements to the techniques in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. An image processing method, characterized in that the method comprises:

2. The method of claim 1, further comprising: and the programmable logic unit obtains a third image according to each obtained second image block.

3. The method according to claim 2, wherein the number of the second image blocks is determined according to the resolution of the third image, the resolution of the first image, and the buffer capacity.

4. The method according to any of claims 1 to 3, wherein the size of the local area tiles in the first image corresponding to at least two of the plurality of second tiles is different.

5. An image processing apparatus characterized by comprising:

6. The apparatus of claim 5, further comprising: and the merging module is used for obtaining a third image from each obtained second image block.

7. The apparatus of claim 6, wherein the number of the second image blocks is determined according to a resolution of the third image, a resolution of the first image, and the buffer capacity.

8. The apparatus according to any of claims 5 to 7, wherein the size of the local area tile in the first image corresponding to at least two of the plurality of second tiles is different.

9. An electronic device, comprising:

a processor;

a memory for storing processor-executable instructions;

wherein the processor is configured to: performing the method of any one of claims 1 to 4.

10. A computer readable storage medium having computer program instructions stored thereon, which when executed by a processor implement the method of any one of claims 1 to 4.