CN110866599A - Chip and method for establishing data path in chip - Google Patents
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Abstract
The embodiment of the application provides a chip and a method for establishing a data path in the chip. The chip includes a plurality of integrated processing devices; an interconnect network adapted to interconnect the plurality of integrated processing devices and comprising a configurable path element disposed between adjacent ones of the plurality of integrated processing devices, the configurable path element adapted to receive data from the integrated processing devices and forwarded to the integrated processing devices; a control unit adapted to selectively configure the configurable path unit to establish a data path between two of the plurality of integrated processing devices based on a particular demand level of an operating parameter of the chip in different applications. According to the technical scheme of the embodiment of the application, the data path can be dynamically configured at the chip level, so that the calculation efficiency is improved, the power consumption of the chip is reduced, and the like.
Description
Technical Field
The present invention relates to the field of chips, and more particularly, to a chip and a method for establishing a data path in the chip.
Background
For example, with the development of neural network technology, Artificial Intelligence (AI) chips need to be more intensive, which can be realized by adding more computing elements on the AI chip, and the more computing elements need a large amount of data to be calculated.
The amount of data entering the computation unit per unit time is called bandwidth, which limits the actual performance of the AI chip. For each AI chip architecture, one big challenge is how to ensure sufficient bandwidth to enable data to be provided to the compute unit in a timely manner. Typically, within the AI architecture, the data path to the compute unit is fixed; there are two data paths into the computation unit, each supplying data (called the multiplier's operands) to the multiplier. The disadvantage is that the data paths are fixed for all neural network scenarios under the AI chip architecture, where the bandwidth of the two data paths limits the efficiency of the computational unit.
To improve efficiency, the computing unit is arranged to maximally reuse data entering the computing unit from both data paths. However, reusing data for various calculations fixes the operation of acquiring such data, which limits the flexibility of operation.
Disclosure of Invention
The invention solves the technical problem that the flexibility of the operation of the computing unit is limited, and the like.
To solve the foregoing technical problem, an embodiment of the present invention provides a chip, including a plurality of integrated processing devices; an interconnect network adapted to interconnect the plurality of integrated processing devices and comprising a configurable path element disposed between adjacent ones of the plurality of integrated processing devices, the configurable path element adapted to receive data from the integrated processing devices and forwarded to the integrated processing devices; a control unit adapted to selectively configure the configurable path unit to establish a data path between two of the plurality of integrated processing devices based on a particular demand level of an operating parameter of the chip in different applications.
Optionally, the two integrated processing devices comprise a source integrated processing device for receiving data and a destination integrated processing device for transmitting data, the control unit being adapted to determine the source integrated processing device and to determine the destination integrated processing device based on the source integrated processing device.
Optionally, each of the plurality of integrated processing devices comprises a computation unit, the data path being adapted to transfer operands for computation by the computation unit or data for combining the operands.
Optionally, an interface module is further included, which is adapted to encapsulate the computation data from the integrated processing device into transmission data that can be processed by the configurable path element and to decapsulate the transmission data from the configurable path element into computation data that can be processed by the integrated processing device.
Optionally, the configurable path element is adapted to receive data from and forward to the integrated processing device based on a network layer protocol or a data link layer protocol.
Optionally, the control unit is adapted to send a specific requirement level of the chip to the configurable path unit, the configurable path unit comprising configuration information or a forwarding policy and being adapted to receive the specific requirement level and to select a specific path preset in the configuration information or a specific path determined according to the forwarding policy based on the specific requirement level to establish a data path between the two integrated processing devices.
Optionally, the specific demand level of the operation parameter of the chip in different applications is a high demand level of data transmission time, a low demand level of data transmission time, a high demand level of chip operation power, a low demand level of chip operation power, a high demand level of network congestion control, or a low demand level of network congestion control in different applications of the neural network.
Optionally, the control unit is adapted to set priorities corresponding to a high demand level of data transmission time, a low demand level of data transmission time, a high demand level of chip operating power, a low demand level of chip operating power, a high demand level of network congestion control, and a low demand level of network congestion control, respectively, and to selectively configure the configurable path unit to establish the data path between two integrated processing devices of the plurality of integrated processing devices based on a highest priority among the priorities.
Optionally, the control unit is adapted to set up a group of integrated processing devices based on a particular level of demand for the chip to run parameters in different applications, and to selectively configure the configurable path unit to preferentially establish a data path between two integrated processing devices set up in the same group of integrated processing devices.
The embodiment of the invention also provides a method for establishing a data path in a chip, wherein the chip comprises a plurality of integrated processing devices, a control unit and a configurable path unit for interconnecting the integrated processing devices, and the method comprises the steps that the control unit sends the specific requirement level of the chip to the configurable path unit; the configurable path unit receives a particular demand level and establishes a data path between two integrated processing devices of the plurality of integrated processing devices based on the particular demand level.
Optionally, the two integrated processing devices comprise a source integrated processing device for receiving data and a destination integrated processing device for sending data, the method comprising the control unit determining the source integrated processing device; the control unit determines a destination integrated processing device based on the source integrated processing device.
Optionally, the configurable path unit receiving the specific demand level and establishing the data path between two integrated processing devices of the plurality of integrated processing devices based on the specific demand level comprises: the configurable path unit receives a specific demand level and determines a specific path in its configuration information or a specific path generated by its forwarding policy based on the specific demand level, thereby establishing a data path between two integrated processing devices.
Optionally, the specific demand level is a high demand level of data transmission time, a low demand level of data transmission time, a high demand level of chip operating power, a low demand level of chip operating power, a high demand level of network congestion control, or a low demand level of network congestion control, and the method includes the control unit setting priorities respectively corresponding to the high demand level of data transmission time, the low demand level of data transmission time, the high demand level of chip operating power, the low demand level of chip operating power, the high demand level of network congestion control, and the low demand level of network congestion control; the configurable path unit establishes a data path between two integrated processing devices of the plurality of integrated processing devices based on a highest priority of the priorities.
Optionally, the control unit is arranged to set the integrated processing device group based on the specific requirement level of the running parameters of the chip in different applications; the configurable path unit preferentially establishes a data path between two integrated processing devices disposed in the same integrated processing device group.
Compared with the prior art, the technical scheme of the embodiment of the invention has the beneficial effects that for example, the data path can be configured at the chip level, so that data can be moved between any integrated processing devices, the calculation efficiency can be improved, and the power consumption of the chip can be reduced.
Drawings
FIG. 1 is a block diagram of a chip according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a specific structure of a chip according to an embodiment of the present invention;
FIG. 3 is a flow chart of a method for establishing a data path within a chip according to an embodiment of the invention.
Detailed Description
The prior art does not consider that there are different requirements for data transmission time, operating power of a chip or Integrated processing Unit (also called Integrated processing Unit, abbreviated as "IPU") on a chip, and network congestion control, among other different chip applications. For example, the AI chip may be used at different times for different neural networks, and the computations applied to one type of neural network may not be necessary for another type of neural network, and thus, the various requirements for the computations may not be the same for the different types of neural networks.
The existing chip architecture in which the integrated processing device receives data is fixed, and a data path cannot be flexibly selected for different chip applications to receive data for the integrated processing device to calculate, which may result in low utilization rate of the integrated processing device and low operation performance of the chip.
In the embodiment of the present invention, considering that the chip may have different requirements on the operation parameters in different applications, for example, one AI chip may be used in different application scenarios of the neural network (such as voice recognition, natural language processing, computer vision and image processing, machine learning, intelligent robot, automatic driving, intelligent drone), and the AI chip may have different requirements on the operation parameters such as data transmission time, chip operation power, network congestion control, and the like in these different application scenarios. Embodiments of the present application determine a particular level of demand, such as a high level of demand for data transfer time, a low level of demand for data transfer time, a high level of demand for chip operating power, a low level of demand for chip operating power, a high level of demand for network congestion control, or a low level of demand for network congestion control, such that one integrated processing device (which may be referred to as a "destination integrated processing device", i.e., an integrated processing device that ultimately receives data when a data path is established between integrated processing devices) can selectively establish a data path with another integrated processing device (which may be referred to as a "source integrated processing device", i.e., an integrated processing device that initially transmits data when a data path is established between integrated processing devices) based on a particular level of demand, the one integrated processing device may thus obtain operands for calculations or data for combining operands. The data path is configurable so that the destination integrated processing device and the associated data path can be flexibly selected, which can both meet different implementation requirements of the associated operating parameters in the integrated processing device and enable the integrated processing device to receive data sufficiently to make maximum use of the computing power of the integrated processing device (or the computing units therein) and to improve the utilization efficiency of the storage units (which are used to provide operands or data used to combine operands) in the integrated processing device.
In the technical solution of the present invention, the chip has a computing architecture, and includes a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a Field-Programmable Gate Array (FPGA), an application-specific Integrated Circuit (ASIC), a Digital Signal Processor (DSP), a multi-core processor (TPU), and a heterogeneous processor. The chip may be an artificial intelligence (i.e., AI) chip, such as a GPU, an FPGA, an ASIC, or a heterogeneous processor of at least two of the three.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 is a schematic block diagram of a chip 100 according to an embodiment of the present invention, where the chip 100 includes a plurality of integrated processing devices 110, an interconnection network 120, and a control unit 130.
The plurality of integrated processing devices 110, as shown in fig. 1, includes a 1 st integrated processing device, a 2 nd integrated processing device, up to an nth integrated processing device. Each integrated processing device includes a computing Unit (also called Arithmetic and Logic Unit, abbreviated as "ALU") and a storage Unit. The computing unit executes arithmetic and logic operations, and a large amount of multiplication is needed during operation; the computing unit includes a plurality of multipliers (multipliers), and for each multiplication, the multiplier in the computing unit needs to be called, and two operands (operands) of the multiplication are input into the multipliers, and then the result is output by the multipliers. The integrated processing device may comprise a Multiplexer (Multiplexer) which provides the calculation unit with operands for the calculation or data for combining the operands.
The interconnection network 120 interconnects the plurality of integrated processing devices 110 to transfer data including operands for computation by the computation units or data for combining the operands between the integrated processing devices; the interconnection network 120 includes data lines and Configurable Routing Units (CRUs) that connect the plurality of integrated processing devices 110. The configurable path unit receives data from the source integrated processing device and forwards the data to the destination integrated processing device, so as to establish a data path between the source integrated processing device and the destination integrated processing device; the configurable path unit has a plurality of which are arranged in the data line and located between adjacent integrated processing devices of the plurality of integrated processing devices 110; the receiving port of each configurable path unit receives data from the source integrated processing equipment, and the sending port sends the data to the destination integrated processing equipment. As shown in fig. 2, a portion of the integrated processing devices 110 (i.e., "IPUs" are illustrated in the figure) are interconnected via an interconnection network 120, wherein the interconnection network 120 includes data lines and configurable path units (i.e., "CRUs" are illustrated in the figure) for connecting a plurality of the integrated processing devices 110.
The configurable path element includes configuration information and forwarding policies for forwarding data in real-time. The configuration information is static preset information, and the preset information includes specific preset information respectively corresponding to specific demand levels of operating parameters of the chip in different applications (for example, a high or low demand level of data transmission time, a high or low demand level of chip operating power, and a high or low demand level of network congestion control). The forwarding policy is a dynamic path configuration, and the configurable path unit may open the receiving port or the transmitting port in real time, close the receiving port or the transmitting port in real time, and/or adjust the data forwarding path from the receiving port to the transmitting port in real time based on different requirement levels of the chip operation parameters in different applications received from the control unit 130.
The control unit 130 controls the plurality of integrated processing devices 110 and the internet 120. For example, the control unit 130 determines a source integrated processing device that needs to receive data, and determines a destination integrated processing device based on the source integrated processing device; the control unit 130 selectively configures the configurable path elements to establish data paths between the source integrated processing device and the destination integrated processing device based on the particular demand level of the chip's operating parameters in the different applications.
Specifically, the control unit 130 transmits a specific demand level (e.g., a high demand level of data transmission time, a low demand level of data transmission time, a high demand level of chip operating power, a low demand level of chip operating power, a high demand level of network congestion control, or a low demand level of network congestion control) to the configurable path unit. After the configurable element receives a particular demand level, it may operate based on configuration information or a forwarding policy. In the case of operation based on configuration information, specific preset information may be determined in real time in accordance with the specific demand level, based on the specific preset information, a transmission port corresponding to the received demand level may be determined in real time in one configurable path unit, and after all the related configurable path units determine the transmission port, a data path is established between the source integrated processing device and the destination integrated processing device. In the case of operation based on a forwarding policy, when the configurable path unit receives a high demand level of data transmission time (i.e. data is required to be transmitted to the destination integrated processing device in a faster time), it forwards the data to a corresponding transmission port, which can reach the destination integrated processing device in a shorter time through real-time calculation; when the configurable path unit receives a low demand level of data transmission time (i.e. data is not required to be transmitted to the destination integrated processing device in a faster time), it forwards the data to any transmitting port or determines a transmitting port based on the configuration information; when the configurable path unit receives a high requirement level of the chip running power (namely, the running power of the control chip is required), the configurable path unit forwards data to a corresponding sending port, the sending port has a shorter path and passes through a smaller number of configurable path units after being calculated in real time, and when the configurable path unit receives a low requirement level of the chip running power (namely, the running power of the control chip is not required), the configurable path unit forwards the data to any sending port or determines the sending port based on the configuration information; when the configurable path unit receives a high demand level of network congestion control (i.e., it is required to control network congestion), it forwards data to the corresponding send port, which has a large free bandwidth calculated in real time to the destination integrated processing device, and when the configurable path unit receives a low demand level of network congestion control (i.e., it is not required to control network congestion), it forwards data to any send port or determines a send port based on configuration information.
The different demand levels may have conflicts in establishing the data path, for example, there may be conflicts in selection of the source integrated processing device, the data lines, the configurable path units and their receiving ports and transmitting ports, etc., and the control unit 130 may set priorities respectively corresponding to a high demand level of data transmission time, a low demand level of data transmission time, a high demand level of chip operating power, a low demand level of chip operating power, a high demand level of network congestion control, and a low demand level of network congestion control, and selectively configure the configurable path units based on the highest priority among these priorities, thereby establishing the data path between the source integrated processing device and the destination integrated processing device. For example, the control unit 130 sends the highest priority information to the configurable path unit, and after the configurable unit receives a specific requirement level, the configurable path unit may operate based on the configuration information or the forwarding policy, which is similar to the above description of the configuration information and the forwarding policy.
Since operands stored at the integrated processing device, e.g., at its storage location, or data used to combine the operands (i.e., "compute data") may not be identical in data format to data stored at the interconnect network 120, e.g., at its configurable path elements (which may be referred to as "transmit data"), the chip 100 may also include an interface module that encapsulates the compute data from the integrated processing device into transmit data that the configurable path elements may process and de-encapsulates the transmit data from the configurable path elements into compute data that the integrated processing device may process. The interface module may be separate from the integrated processing device or may be integrated with the integrated processing device.
As is known in the art, the TCP/IP protocol suite includes a network layer protocol and a data link layer protocol, and the configurable path unit may encapsulate data into IP packets based on the network layer protocol or into data frames based on the data link layer protocol.
The control unit 130 may set the groups of integrated processing devices to which data are frequently transmitted and received from each other or based on a specific demand level of an operation parameter of the chip in different applications, for example, divide one or more groups of integrated processing devices within the plurality of integrated processing devices 110 based on a high or low demand level of data transmission time, a high or low demand level of chip operation power, or a high or low demand level of network congestion control, so that these demand levels may be dynamically adapted to increase data transmission time, reduce chip operation power, or improve network congestion, etc. In the situation that only a small number of integrated processing devices exist in an integrated processing device group and a data path needs to be established between two integrated processing devices in the group, a processing mode of encapsulating data frames can be adopted, and compared with a processing mode of encapsulating IP data packets, the processing mode of encapsulating data frames into IP data packets has a simpler encapsulation format, so that the data processing efficiency is improved; this smaller number of integrated processing devices may, for example, account for 1/3, 1/5, 1/10, 1/20, 1/50, or 1/100 in number for all integrated processing devices in the chip, wherein this ratio is by way of example only and should not be construed in a limiting sense.
The control unit 130 may selectively configure the configurable path unit to preferentially establish a data path between two integrated processing devices disposed in the same group of integrated processing devices. Further, one integrated processing device may be disposed in different integrated processing device groups based on different demand levels, the control unit 130 may set priorities of the different integrated processing device groups, and may selectively configure the configurable path unit to preferentially establish a data path between two integrated processing devices disposed in the same integrated processing device group having a higher priority. For example, the control unit 130 sends information of the same integrated processing device group and information of the integrated processing device group with higher priority to the configurable path unit, and after the configurable unit receives the information, the configurable path unit may operate based on the configuration information or the forwarding policy, which is similar to the above description regarding the configuration information and the forwarding policy.
FIG. 3 is a flow chart of a method 300 for establishing a data path within a chip according to an embodiment of the present invention, the chip including a plurality of integrated processing devices, a control unit, and a configurable routing unit for interconnecting the plurality of integrated processing devices. The method 300 includes the steps of:
step S310: the control unit sends the specific requirement level of the chip to the configurable path unit;
step S320: the configurable path unit receives a particular demand level and establishes a data path between two integrated processing devices of the plurality of integrated processing devices based on the particular demand level.
In the execution of step S310, the control unit analyzes different applications of the chip, determines a specific demand level of the chip in the current application, and transmits the specific demand level to the configurable path unit.
In execution of step S320, the configurable path unit receives the specific demand level and establishes a data path between two integrated processing devices of the plurality of integrated processing devices based on the specific demand level, thereby dynamically configuring the data path between the integrated processing devices in real time.
Further, the two integrated processing devices include a source integrated processing device for receiving data and a destination integrated processing device for transmitting data, and the method 300 includes the control unit determining the source integrated processing device, the control unit determining the destination integrated processing device based on the source integrated processing device.
Further, step S320 includes the configurable path unit receiving the specific requirement level and determining the specific path in its configuration information or the specific path generated by its forwarding policy based on the specific requirement level, thereby establishing a data path between the two integrated processing devices.
Further, the specific demand level is a high demand level of data transmission time, a low demand level of data transmission time, a high demand level of chip operating power, a low demand level of chip operating power, a high demand level of network congestion control, or a low demand level of network congestion control, and the method 300 includes the control unit setting priorities respectively corresponding to the high demand level of data transmission time, the low demand level of data transmission time, the high demand level of chip operating power, the low demand level of chip operating power, the high demand level of network congestion control, and the low demand level of network congestion control, and the configurable path unit establishing a data path between two integrated processing devices of the plurality of integrated processing devices based on a highest priority among the priorities.
Further, the method 300 includes the control unit setting up a set of integrated processing devices based on a particular demand level of a chip operating parameter in a different application, the configurable path unit preferentially establishing a data path between two integrated processing devices disposed in the same set of integrated processing devices.
For specific principles, embodiments and the like of the method 300 for establishing a data path in a chip, reference may be made to the above description of the chip 100 in conjunction with fig. 1 and 2, and further description is omitted here.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (14)
1. A chip, comprising:
a plurality of integrated processing devices;
an interconnect network adapted to interconnect the plurality of integrated processing devices and comprising a configurable path element disposed between adjacent ones of the plurality of integrated processing devices, the configurable path element adapted to receive data from and forwarded to the integrated processing devices;
a control unit adapted to selectively configure the configurable path unit to establish a data path between two of the plurality of integrated processing devices based on a particular demand level for operating parameters of the chip in different applications.
2. The chip according to claim 1, wherein the two integrated processing devices comprise a source integrated processing device for receiving data and a destination integrated processing device for transmitting data, the control unit being adapted to determine the source integrated processing device and to determine the destination integrated processing device based on the source integrated processing device.
3. The chip according to claim 1 or 2, wherein each of the plurality of integrated processing devices comprises a computation unit, the data path being adapted to transfer operands for computation by the computation unit or data for combining the operands.
4. The chip of claim 1, further comprising an interface module adapted to encapsulate the computation data from the integrated processing device into transmission data that can be processed by the configurable path element and to decapsulate the transmission data from the configurable path element into the computation data that can be processed by the integrated processing device.
5. The chip of claim 1, wherein the configurable path element is adapted to receive data from and forward to an integrated processing device based on a network layer protocol or a data link layer protocol.
6. The chip according to claim 1, wherein the control unit is adapted to send a specific requirement level of the chip to the configurable path unit, the configurable path unit comprises configuration information or a forwarding policy and is adapted to receive the specific requirement level and to select a specific path preset in the configuration information or a specific path determined according to the forwarding policy based on the specific requirement level to establish the data path between the two integrated processing devices.
7. The chip of claim 1, wherein the specific demand level of the operating parameter of the chip in different applications is a high demand level of data transmission time, a low demand level of data transmission time, a high demand level of chip operating power, a low demand level of chip operating power, a high demand level of network congestion control, or a low demand level of network congestion control of the chip in different applications of the neural network.
8. The chip of claim 7, wherein the control unit is adapted to set priorities corresponding to a high demand level for the data transfer time, a low demand level for the data transfer time, a high demand level for the chip operating power, a low demand level for the chip operating power, a high demand level for network congestion control, and a low demand level for network congestion control, respectively, and to selectively configure the configurable path unit to establish the data path between two of the plurality of integrated processing devices based on a highest priority of the priorities.
9. The chip of claim 1, wherein the control unit is adapted to set up a set of integrated processing devices based on a particular level of demand for operating parameters of the chip in different applications, and to selectively configure the configurable path unit to preferentially establish a data path between two integrated processing devices disposed in the same set of integrated processing devices.
10. A method of establishing a data path within a chip, the chip comprising a plurality of integrated processing devices, a control unit and a configurable path unit for interconnecting the plurality of integrated processing devices, the method comprising:
the control unit sends the specific demand level of the chip to the configurable path unit;
the configurable path unit receives the particular demand level and establishes a data path between two of the plurality of integrated processing devices based on the particular demand level.
11. The method of claim 10, wherein the two integrated processing devices comprise a source integrated processing device for receiving data and a destination integrated processing device for transmitting data, the method comprising:
the control unit determines the source integrated processing device;
the control unit determines the destination integrated processing device based on the source integrated processing device.
12. The method of claim 10, wherein the configurable path unit receiving the particular demand level and establishing a data path between two of the plurality of integrated processing devices based on the particular demand level comprises: the configurable path unit receives the specific demand level and determines a specific path in its configuration information or a specific path resulting from its forwarding policy based on the specific demand level, thereby establishing a data path between the two integrated processing devices.
13. The method of claim 10, wherein the particular demand level is a high demand level for data transmission time, a low demand level for data transmission time, a high demand level for chip operating power, a low demand level for chip operating power, a high demand level for network congestion control, or a low demand level for network congestion control, the method comprising:
the control unit sets priorities respectively corresponding to a high demand level of the data transmission time, a low demand level of the data transmission time, a high demand level of the chip operating power, a low demand level of the chip operating power, a high demand level of network congestion control, and a low demand level of network congestion control;
the configurable path unit establishes the data path between two of the plurality of integrated processing devices based on a highest priority of the priorities.
14. The method of claim 10, comprising:
the control unit sets an integrated processing device group based on specific requirement levels of operating parameters of the chip in different applications;
the configurable path unit preferentially establishes a data path between two integrated processing devices disposed in the same integrated processing device group.
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