CN110855909B - Seamless low-delay switching method for video signals - Google Patents

Seamless low-delay switching method for video signals Download PDF

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CN110855909B
CN110855909B CN201911113479.9A CN201911113479A CN110855909B CN 110855909 B CN110855909 B CN 110855909B CN 201911113479 A CN201911113479 A CN 201911113479A CN 110855909 B CN110855909 B CN 110855909B
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CN110855909A (en
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方华
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Guangdong Meishi Technology Co.,Ltd.
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Ative Corp (china)
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/222—Studio circuitry; Studio devices; Studio equipment
    • H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
    • H04N5/268—Signal distribution or switching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
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Abstract

The invention discloses a video signal seamless low-delay switching method and a system, wherein the method mainly comprises the following steps: the first FPGA receiving module continues to receive a last frame video picture of a first video input signal after receiving a video input signal switching instruction and caches the last frame video picture to the DDR module, then the video input signal switching instruction is sent to the MCU module to serve as a video input signal switching ready instruction, the last frame video picture of the first video input signal is output until a second video input signal is ready, and after the MCU module receives the video input signal switching ready instruction, the video picture of the second video input signal is immediately switched to the first FPGA receiving module. The system is composed of a video input signal, an FPGA sending module, an optical switching matrix module, an FPGA receiving module and a terminal display device. The method and the system realize seamless and low-delay transmission of the video signal and bring better user experience.

Description

Seamless low-delay switching method for video signals
Technical Field
The present invention relates to the field of communications, and in particular, to a method and a system for seamless low-latency switching of video signals.
Background
In the video signal transmission process, different video sources adopt respective independent clocks and independent sending opportunities, so that different video signals are inconsistent in frame phase and inconsistent in clock speed. When different pictures are switched, due to the fact that the speeds are different and the phases are different, frame rate and speed adaptation is carried out on the buffered frames, the problems of screen splash and screen blackness before and after signal switching can be solved, but the delay frames cannot meet the requirements in occasions with extremely low delay requirements of many transmission systems, and the screen splash and screen blackness problems are caused by direct switching.
Therefore, there is a need for a method and system for seamless low-latency switching of video signals to solve the problem of seamless low-latency transmission of video signals.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a method and a system for seamless low-delay switching of video signals.
In order to achieve the above object, embodiments of the present invention provide a method and a system for seamless low-latency switching of video signals, where the technical solution is as follows.
In a first aspect, a method for seamless low-latency switching of a video signal is provided, the method comprising the following steps.
S1, the first FPGA receiving module outputs the video picture of the first video input signal to the first terminal display device normally.
And S2, the first FPGA receiving module receives a video input signal switching instruction.
S3, the first FPGA receiving module continues to receive the first video input signal until receiving the frame end signal of the first video input signal.
And S4, the first FPGA receiving module sends the video input signal switching instruction to the MCU module to serve as a video input signal switching ready instruction, and meanwhile, the last frame of video picture of the received first video input signal is cached in the DDR module, and then the last frame of video picture of the first video input signal is output until the second video input signal is ready.
And S5, immediately switching the video picture of the second video input signal to the first FPGA receiving module after the MCU module receives the video input signal switching ready instruction.
S6, when the first FPGA receiving module outputs the last line of the last frame video picture of the first video input signal cached by the DDR module line by line, judging whether the video picture of the second video input signal captures the first line, if so, judging whether the current line of the video picture of the second video input signal is at the upper end or the lower end of the middle line of the current frame; and if not, continuously outputting the last frame video picture of the first video input signal cached by the DDR module until the last line of the next video picture.
S7, if the current line of the video picture of the second video input signal is at the upper end of the middle line of the current frame, the second video input signal accelerates the speed of outputting the pixel clock by itself, and the seamless low-delay switching of the second video input signal is realized; and if the current line of the video picture of the second video input signal is at the lower end of the middle line of the current frame, the second video input signal slows down the self-output pixel clock speed, and the seamless low-delay switching of the second video input signal is realized.
Further, a video picture of the first video input signal is sent to the first FPGA receiving module through the first FPGA sending module; and the video picture of the second video input signal is sent to the first FPGA receiving module through a second FPGA sending module.
Further, if the position of the first line of the last frame of the video picture of the first video input signal output by the first FPGA receiving module and the position of the first line of the video picture of the second video input signal within the frame at the same time point are different, only when the first FPGA receiving module receives the last line of the video picture of the first video input signal, the first FPGA receiving module sends a video input signal switching ready instruction to the MCU module, and buffers the complete video picture of the last frame of the first video input signal and uses it as an output video picture, so as to realize no screen omission or black screen in the switching process.
Further, the first FPGA receiving module judges a speed difference between the first and second video input signals before and after switching according to a pixel number difference value in the frame synchronization signal in the first and second video input signals, and increases or decreases a clock speed of outputting the video signal by itself.
Further, according to the position of the frame synchronization signal in the video input signal, calculating the pixel number difference between the input of the first FPGA transmission module and the output of the first FPGA reception module, which achieves zero delay, and marking the pixel number difference as S0, setting the frame synchronization signal in the position range where the video input signal is fixed according to the resolution of different terminal display devices, and marking the pixel number difference as S01, thereby calculating the total value of the pixel number difference required to reduce the difference for synchronizing the input of the first FPGA transmission module and the output of the first FPGA reception module as S, where S is min { | S0-S01|, | H-S0+ S01| }, where H is the total pixel number of the input video signal.
Further, the maximum number of pixels with a variable video refresh rate supported by the terminal display device is marked as a constant b, the video refresh rate of the terminal display device is marked as e, the maximum pixel clock frequency deviation of each frame that can be supported by the terminal display device is marked as a constant a, and under the current pixel clock frequency a, the speed difference value of the frequencies of the first frame video picture and the second frame video picture received by the first FPGA receiving module is marked as c.
Further, calculating the inflection point time t of the output pixel clock adjustment of the first FPGA receiving module to realize the input and output synchronization,
Figure GDA0002479463850000031
or
Figure GDA0002479463850000036
Or
Figure GDA0002479463850000037
In a second aspect, a video signal seamless low-delay switching system is provided, and the system is composed of a video input signal, an FPGA transmitting module, an optical switching matrix module, an FPGA receiving module and a terminal display device, wherein the FPGA transmitting module is composed of a video acquisition module and an optical module, the optical switching matrix module comprises an MCU module and a DDR module, and the FPGA receiving module is composed of an optical module and a video output module.
Furthermore, the FPGA sending module collects the video input signal through the video collecting module, and sends the collected video input signal to the optical switching matrix module in real time through the optical module, and no buffer is made on the optical switching matrix module, wherein a frame synchronization signal fixed at a specific position of the video input signal is sent before each frame of the video input signal is sent.
Further, the first FPGA receiving module judges a speed difference between the first and second video input signals before and after switching according to a difference between pixel numbers in the frame synchronization signals in the first and second video input signals, and increases or decreases a clock speed of outputting the video signal by itself.
Compared with the prior art, the beneficial effects of the utility model reside in that: the method and the system can realize seamless and low-delay transmission of the video signal, and bring better user experience.
Drawings
Fig. 1 is a flow chart of a video signal seamless low-latency switching method according to an embodiment of the present invention.
FIG. 2 shows a step a in the practice of the present invention>0、c<＝0、
Figure GDA0002479463850000032
Then, the first FPGA receiving module outputs a pixel clock to adjust the inflection point time t1Schematic diagram of the calculation of (1).
FIG. 3 shows a step a in the practice of the present invention<0、c>＝0、
Figure GDA0002479463850000033
Then, the first FPGA receiving module outputs a pixel clock to adjust the inflection point time t1Schematic diagram of the calculation of (1).
FIG. 4 shows a step a in the practice of the present invention>0、c>0、
Figure GDA0002479463850000034
Then, the first FPGA receiving module outputs a pixel clock to adjust the inflection point time t1Schematic diagram of the calculation of (1).
FIG. 5 shows a step a in the practice of the present invention<0、c<0、
Figure GDA0002479463850000035
Then, the first FPGA receiving module outputs a pixel clock to adjust the inflection point time t1Schematic diagram of the calculation of (1).
Fig. 6 is a block diagram of a video signal seamless low latency switch system according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 is a flowchart of a video signal seamless low-latency switching method according to an embodiment of the present invention, which includes the following steps.
S1, the first FPGA receiving module outputs the video picture of the first video input signal to the first terminal display device normally.
And S2, the first FPGA receiving module receives a video input signal switching instruction.
S3, the first FPGA receiving module continues to receive the first video input signal until receiving the frame end signal of the first video input signal.
And S4, the first FPGA receiving module sends the video input signal switching instruction to the MCU module to serve as a video input signal switching ready instruction, and meanwhile, the last frame of video picture of the received first video input signal is cached in the DDR module, and then the last frame of video picture of the first video input signal is output until the second video input signal is ready.
And S5, immediately switching the video picture of the second video input signal to the first FPGA receiving module after the MCU module receives the video input signal switching ready instruction.
S6, when the first FPGA receiving module outputs the last line of the last frame video picture of the first video input signal cached by the DDR module line by line, judging whether the video picture of the second video input signal captures the first line, if so, judging whether the current line of the video picture of the second video input signal is at the upper end or the lower end of the middle line of the current frame; and if not, continuously outputting the last frame video picture of the first video input signal cached by the DDR module until the last line of the next video picture.
S7, if the current line of the video frame of the second video input signal is at the top of the middle line of the current frame, the first FPGA receiving module accelerates its own output pixel clock speed within the maximum tolerance range acceptable for the second video input signal, and after the difference between the output line and the input line is within the allowable minimum range, adjusts the pixel clock speed to approach the pixel clock speed of the first video input signal again, so as to implement seamless low-delay switching of the second video input signal, and at the same time, the delay of the second video input signal is reduced to approach 0; and if the current line of the video picture of the second video input signal is at the lower end of the middle line of the current frame, the second video input signal slows down the speed of outputting the pixel clock of the second video input signal, and the pixel clock speed is adjusted to approach the pixel clock speed of the first video input signal again after the difference between the output line and the video input line is in the allowable minimum range, so that the seamless low-delay switching of the second video input signal is realized.
Because the first video input signal and the switched second video input signal have different phases and different accurate frame speeds, in order to ensure smooth switching of the video input signals and minimize time delay, frame switching time, time for adjusting start and stop of clock speed and adjusting speed are required to be calculated, and finally a switching strategy is formed to realize smooth switching, no black screen, no splash screen and no signal instability of the video input signals and keep minimum time delay between input and output.
In step S7, if the resolution of the current frame is 1920 × 1080, the horizontal middle line 960 of the current frame is provided. If the first line of the video picture of the second video input signal is at the upper end of the middle line of the current frame (such as the 900 th line), the second video input signal accelerates the switching speed, and seamless low-delay switching is realized; if the first line of the video picture of the second video input signal is at the lower end of the middle line of the current frame (for example, at line 1100), the second video input signal slows down the switching speed, and the seamless low-delay switching is realized.
The video picture of the first video input signal is sent to the first FPGA receiving module through the first FPGA sending module; and the video picture of the second video input signal is sent to the first FPGA receiving module through a second FPGA sending module.
If the position of the first line of the last frame of the video picture of the first video input signal output by the first FPGA receiving module and the position of the first line of the video picture of the second video input signal in the same time point are different, only when the first FPGA receiving module receives the last line of the video picture of the first video input signal, the first FPGA receiving module can send a video input signal switching ready instruction to the MCU module, and buffer the complete video picture of the last frame of the first video input signal and use the complete video picture as an output video picture, so as to realize no screen omission or black screen in the switching process. The reason for the screen splash is that switching is performed when a complete frame of picture is not received, and the reason for the screen blackness is that a frame of signal is sent out again when a complete frame is not sent, so that receiving equipment such as a display is disordered and the screen blackness is reset, or the receiving end is locked by a clock speed suddenly.
The first FPGA receiving module judges the speed difference of the first and second video input signals before and after switching according to the pixel number difference value in the frame synchronization signal in the first and second video input signals (when the first and second video input signals are balanced, the clock speed of the first video input signal before switching is the video output clock speed of the first FPGA receiving module, so that the speed difference of the second video input signal and the video output of the first FPGA receiving module is the speed difference of the first video input signal and the second video input signal), and the clock speed of the video output of the FPGA receiving module is increased or reduced.
And calculating the pixel number difference between the input of the first FPGA sending module and the output of the first FPGA receiving module to realize zero delay according to the position of the frame synchronization signal in the video input signal, wherein the pixel number difference is marked as S0, setting the frame synchronization signal in a position range fixed by the video input signal according to the resolution of different terminal display equipment, and marking the frame synchronization signal as S01, thereby calculating the total value of the pixel number difference required for reducing the difference when the input of the first FPGA sending module is synchronized with the output of the first FPGA receiving module as S, wherein S is min { | S0-S01|, | -H-S0 + S01| }, and H is the total pixel value of the input video signal.
For example, the video input signal is a 4K signal (the number of pixels in each row is 4096), the terminal display device is a 4K display device, the first FPGA sending module inputs the number of pixels S0 different from the first FPGA receiving module to output zero delay, 3500 and 2000, the resolution of the terminal display device is 4K, and the frame synchronization signal is set in the 1000 th (S01) row of the video input signal, thereby calculating that the total value of the number of pixels required to reduce the difference to synchronize the input of the first FPGA sending module with the output of the first FPGA receiving module is S min { |1500 and 1000|, |4096 and 1500+1000| } 500.
The maximum number of pixels with variable video refresh rate supported by the terminal display device is marked as a constant b (for example, b is equal to 3), the video refresh rate of the terminal display device is marked as e (for example, e is equal to 60hz), the maximum pixel clock frequency deviation per frame that can be supported by the terminal display device is marked as a constant a (for example, a is equal to 30), and under the current pixel clock frequency a, the speed difference value of the frequencies of the first frame video picture and the second frame video picture received by the first FPGA receiving module is marked as c.
In FIGS. 2-5, a is the slope of the line connecting the point F and the origin.
And calculating the time t of the inflection point of the output pixel clock adjustment of the first FPGA receiving module to realize the input and output synchronization. Here, the time t is a time point at which the switching speed needs to be accelerated or decelerated in the step S7, and when t is a positive number, the switching speed needs to be accelerated, and when t is a negative number, the switching speed needs to be decelerated.
FIG. 2 shows a step a in the practice of the present invention>0、c<＝0、
Figure GDA0002479463850000061
Then, the first FPGA receiving module outputs a pixel clock to adjust the inflection point time t1Schematic diagram of the calculation of (1).
Figure GDA00024794638500000614
Further can reversely deduce
Figure GDA0002479463850000063
Wherein
Figure GDA0002479463850000064
For example, when S is 500, a is 30, b is 3, c is-30, e is 60hz,
Figure GDA0002479463850000065
input and output synchronization can be achieved by adjusting the first FPGA receive module output pixel clock at 87 milliseconds (ms).
Of course, when satisfied
Figure GDA0002479463850000066
Then, t can be directly obtained1Without the need for the complex calculation process described above.
FIG. 3 shows a step a in the practice of the present invention<0、c>＝0、
Figure GDA0002479463850000067
Then, the first FPGA receiving module outputs a pixel clock to adjust the inflection point time t1Schematic diagram of the calculation of (1).
Figure GDA00024794638500000615
Further can reversely deduce
Figure GDA0002479463850000069
Wherein
Figure GDA00024794638500000610
Of course, when satisfied
Figure GDA00024794638500000611
Then, t can be directly obtained1Without the need for the complex calculation process described above.
FIG. 4 shows a step a in the practice of the present invention>0、c>0、
Figure GDA00024794638500000612
Then, the first FPGA receiving module outputs a pixel clock to adjust the inflection point time t1Schematic diagram of the calculation of (1).
Figure GDA00024794638500000616
Further can reversely deduce
Figure GDA0002479463850000071
Wherein
Figure GDA0002479463850000072
For example, when S is 100, a is 3, b is 5, c is 3, and e is 60hz, the method is performed
Figure GDA0002479463850000073
The input and output synchronization can be realized by adjusting the output pixel clock of the first FPGA receiving module at 0.68 second.
FIG. 5 shows a step a in the practice of the present invention<0、c<0、
Figure GDA0002479463850000074
Then, the first FPGA receiving module outputs a pixel clock to adjust the inflection point time t1Schematic diagram of the calculation of (1).
Figure GDA0002479463850000078
Further can reversely deduce
Figure GDA0002479463850000076
Wherein
Figure GDA0002479463850000077
The method can realize seamless and low-delay transmission of the video signal, and brings better user experience.
Fig. 6 is a block diagram of a video seamless low latency switch system according to an embodiment of the present invention. The system comprises a video input signal, an FPGA sending module, an optical switching matrix module, an FPGA receiving module and a terminal display device, wherein the FPGA sending module comprises a video acquisition module and an optical module, the optical switching matrix module comprises an MCU module and a DDR module, and the FPGA receiving module comprises an optical module and a video output module.
In this embodiment, the system includes a first video input signal, a second video input signal, a first FPGA transmission module, a second FPGA transmission module, an optical switching matrix module, a first FPGA reception module, a second FPGA reception module, a first terminal display device, and a second terminal display device, where the first FPGA transmission module includes a first video acquisition module and a first optical module, the second FPGA transmission module includes a second video acquisition module and a third optical module, the optical switching matrix module includes a MCU module and a DDR module, the first FPGA reception module includes a second optical module and a first video output module, and the second FPGA reception module includes a fourth optical module and a second video output module. The signal acquisition module is responsible for acquiring video input signals; the MCU module is a configuration processor and is used for transmitting configuration data to the FPGA module; the DDR module is used for storing relevant data processed by the FPGA module; the FPGA module is a logic programmable chip and is responsible for image display, image storage, data cache and logic control of the whole module; the optical module and the optical fiber interface module are mainly used for high-speed transmission of data.
The FPGA sending module collects the video input signal through the video collecting module, sends the collected video input signal to the optical switching matrix module in real time through the optical module, and does not buffer on the optical switching matrix module, wherein a frame synchronization signal fixed at a specific position of the video input signal is sent before each frame of the video input signal is sent. In this embodiment, the frame synchronization signal is sent every time the first row of valid data is acquired, that is, the synchronization signal of the item frame is fixed at the position of the first row of valid data of the video input signal.
And the first FPGA receiving module judges the speed difference of the first video input signal and the second video input signal before and after switching according to the pixel number difference value in the frame synchronization signal in the first video input signal and the second video input signal, and accelerates or decelerates the clock speed of the video signal output by the first FPGA receiving module.
The position at which the frame sync signal is fixed in the video input signal in this embodiment takes different values at different resolutions, for example where the 4K resolution is set between the 800 th row and the 1000 th row of the valid data of the video input signal, and thus the delay is calculated to be between 6.5ms (800/4096/30) and 8ms (1000/4096/30) at a 30hz refresh rate, and similarly between 3.25ms and 4ms at a 60hz refresh rate; the 2K resolution is set between line 200 and line 300 of the video input signal with valid data, whereby the delay is calculated to be between 3.25ms and 4.9ms at a 30hz refresh rate and between 1.6ms and 2.4ms at a 60hz refresh rate.
The system can realize seamless and low-delay transmission of the video signal, and brings better user experience.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
While embodiments of the invention have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims (7)

1. A method for seamless low-latency switching of video signals, said method comprising the steps of:
s1, the first FPGA receiving module outputs the video picture of the first video input signal to the first terminal display device normally;
s2, the first FPGA receiving module receives a video input signal switching instruction;
s3, the first FPGA receiving module continues to receive the first video input signal until receiving a frame end signal of the first video input signal;
s4, the first FPGA receiving module sends the video input signal switching instruction to the MCU module to serve as a video input signal switching ready instruction, meanwhile, the last frame of video picture of the received first video input signal is cached in the DDR module, and then the last frame of video picture of the first video input signal is output until a second video input signal is ready;
s5, immediately switching the video picture of the second video input signal to the first FPGA receiving module after the MCU module receives the video input signal switching ready instruction;
s6, when the first FPGA receiving module outputs the last line of the last frame video picture of the first video input signal cached by the DDR module line by line, judging whether the video picture of the second video input signal captures the first line, if so, judging whether the current line of the video picture of the second video input signal is at the upper end or the lower end of the middle line of the current frame; if not, continuously outputting the last frame video picture of the first video input signal cached by the DDR module until the last line of the next video picture;
s7, if the current line of the video picture of the second video input signal is at the upper end of the middle line of the current frame, the second video input signal accelerates the speed of outputting the pixel clock by itself, and the seamless low-delay switching of the second video input signal is realized; and if the current line of the video picture of the second video input signal is at the lower end of the middle line of the current frame, the second video input signal slows down the self-output pixel clock speed, and the seamless low-delay switching of the second video input signal is realized.
2. The method of claim 1, wherein the video signal is switched between the seamless low-latency mode and the seamless low-latency mode: the video picture of the first video input signal is sent to the first FPGA receiving module through the first FPGA sending module; and the video picture of the second video input signal is sent to the first FPGA receiving module through a second FPGA sending module.
3. The method of claim 1, wherein the video signal is switched between the seamless low-latency mode and the seamless low-latency mode: if the position of the first line of the last frame of the video picture of the first video input signal output by the first FPGA receiving module and the position of the first line of the video picture of the second video input signal in the same time point are different, only when the first FPGA receiving module receives the last line of the video picture of the first video input signal, the first FPGA receiving module can send a video input signal switching ready instruction to the MCU module, and buffer the complete video picture of the last frame of the first video input signal and use the complete video picture as an output video picture, so as to realize no screen waste or black screen in the switching process.
4. The method of claim 2, wherein the video signal is switched between the seamless low-latency mode and the seamless low-latency mode: and the first FPGA receiving module judges the speed difference of the first video input signal and the second video input signal before and after switching according to the pixel number difference value in the frame synchronization signal in the first video input signal and the second video input signal, and accelerates or decelerates the clock speed of the video signal output by the first FPGA receiving module.
5. The method of claim 4, wherein the video signal is switched between the seamless low-latency mode and the seamless low-latency mode: and calculating the pixel number difference between the input of the first FPGA sending module and the output of the first FPGA receiving module to realize zero delay according to the position of the frame synchronization signal in the video input signal, wherein the pixel number difference is marked as S0, setting the frame synchronization signal in a position range fixed by the video input signal according to the resolution of different terminal display equipment, and marking the frame synchronization signal as S01, thereby calculating the total value of the pixel number difference required for reducing the difference when the input of the first FPGA sending module is synchronized with the output of the first FPGA receiving module as S, wherein S is min { | S0-S01|, | -H-S0 + S01| }, and H is the total pixel value of the input video signal.
6. The method of claim 5, wherein the video signal is switched between the seamless low-latency mode and the seamless low-latency mode: marking the highest variable pixel number of the video refresh rate supported by the terminal display equipment as a constant b, marking the video refresh rate of the terminal display equipment as an e, marking the maximum pixel clock frequency deviation of each frame supported by the terminal display equipment as a constant a, and marking the speed difference value of the frequency of the first frame video picture and the second frame video picture received by the first FPGA receiving module as a c under the current pixel clock frequency a.
7. The method of claim 6, wherein the video signal is switched between the seamless low-latency mode and the seamless low-latency mode: calculating the inflection point time t of the output pixel clock adjustment of the first FPGA receiving module to realize the input and output synchronization,
Figure FDA0002479463840000021
or
Figure FDA0002479463840000022
Or
Figure FDA0002479463840000023
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