CN110854240A - PERC battery and preparation method thereof - Google Patents
PERC battery and preparation method thereof Download PDFInfo
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- CN110854240A CN110854240A CN201911256027.6A CN201911256027A CN110854240A CN 110854240 A CN110854240 A CN 110854240A CN 201911256027 A CN201911256027 A CN 201911256027A CN 110854240 A CN110854240 A CN 110854240A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 16
- 101001073212 Arabidopsis thaliana Peroxidase 33 Proteins 0.000 title claims abstract 8
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- 102100028961 Peroxisome proliferator-activated receptor gamma coactivator 1-beta Human genes 0.000 title claims abstract 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 109
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 108
- 239000010703 silicon Substances 0.000 claims abstract description 108
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 99
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 47
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 46
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims abstract description 36
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 35
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 33
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 24
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 24
- 238000000151 deposition Methods 0.000 claims abstract description 18
- 238000009792 diffusion process Methods 0.000 claims abstract description 18
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 18
- 230000003647 oxidation Effects 0.000 claims abstract description 17
- 239000007789 gas Substances 0.000 claims abstract description 16
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 13
- 239000001301 oxygen Substances 0.000 claims abstract description 13
- 238000000137 annealing Methods 0.000 claims abstract description 10
- 239000011248 coating agent Substances 0.000 claims abstract description 10
- 238000000576 coating method Methods 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 8
- 238000005498 polishing Methods 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 34
- 239000000758 substrate Substances 0.000 claims description 22
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 14
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 8
- 229910052698 phosphorus Inorganic materials 0.000 claims description 8
- 239000011574 phosphorus Substances 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 239000007888 film coating Substances 0.000 claims description 5
- 238000009501 film coating Methods 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 4
- 230000009977 dual effect Effects 0.000 claims 1
- 230000003749 cleanliness Effects 0.000 abstract description 5
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 5
- 230000004069 differentiation Effects 0.000 abstract 1
- 230000010354 integration Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 115
- 238000000231 atomic layer deposition Methods 0.000 description 29
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 13
- 238000002161 passivation Methods 0.000 description 10
- 239000010408 film Substances 0.000 description 9
- 238000007650 screen-printing Methods 0.000 description 9
- 238000006243 chemical reaction Methods 0.000 description 8
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- 238000005245 sintering Methods 0.000 description 6
- 230000000052 comparative effect Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical group ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
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- 125000004437 phosphorous atom Chemical group 0.000 description 3
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- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 239000003513 alkali Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 238000010329 laser etching Methods 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 230000002035 prolonged effect Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 229910017107 AlOx Inorganic materials 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- SMZOGRDCAXLAAR-UHFFFAOYSA-N aluminium isopropoxide Chemical compound [Al+3].CC(C)[O-].CC(C)[O-].CC(C)[O-] SMZOGRDCAXLAAR-UHFFFAOYSA-N 0.000 description 1
- VSCWAEJMTAWNJL-UHFFFAOYSA-K aluminium trichloride Chemical compound Cl[Al](Cl)Cl VSCWAEJMTAWNJL-UHFFFAOYSA-K 0.000 description 1
- JPUHCPXFQIXLMW-UHFFFAOYSA-N aluminium triethoxide Chemical compound CCO[Al](OCC)OCC JPUHCPXFQIXLMW-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000006388 chemical passivation reaction Methods 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- JGHYBJVUQGTEEB-UHFFFAOYSA-M dimethylalumanylium;chloride Chemical compound C[Al](C)Cl JGHYBJVUQGTEEB-UHFFFAOYSA-M 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000001579 optical reflectometry Methods 0.000 description 1
- RLOWWWKZYUNIDI-UHFFFAOYSA-N phosphinic chloride Chemical compound ClP=O RLOWWWKZYUNIDI-UHFFFAOYSA-N 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- KWYUFKZDYYNOTN-UHFFFAOYSA-M potassium hydroxide Substances [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
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- 239000002344 surface layer Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- VOITXYVAKOUIBA-UHFFFAOYSA-N triethylaluminium Chemical compound CC[Al](CC)CC VOITXYVAKOUIBA-UHFFFAOYSA-N 0.000 description 1
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
- H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
- H01L31/03529—Shape of the potential jump barrier or surface barrier
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
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- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
- H01L31/1868—Passivation
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- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
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Abstract
The application provides a PERC battery and a preparation method thereof, and belongs to the technical field of photovoltaic batteries. The preparation method comprises the steps of texturing, diffusion, etching, back polishing, annealing, back coating and front coating. The back surface coating step comprises: and introducing ozone gas into the equipment provided with the annealed silicon wafer for oxidation treatment, so that a back silicon dioxide layer is formed on the back of the silicon wafer. And then continuously introducing ozone serving as an oxygen source in the same equipment, adding an aluminum source, and depositing a back aluminum oxide layer on the back silicon dioxide layer. A back side silicon nitride layer is deposited on the back side aluminum oxide layer. According to the preparation method, the back silicon oxide layer is formed by introducing ozone, the ozone is used as an oxygen source, the back aluminum oxide layer can be continuously deposited in the ozone introducing equipment, the back silicon dioxide layer and the back aluminum oxide layer can be formed in the same equipment, ozone oxidation equipment does not need to be added, the cleanliness of a film contact interface is kept, and the PID (proportion integration differentiation) performance of the PERC battery can be improved.
Description
Technical Field
The application relates to the technical field of photovoltaic cells, in particular to a PERC cell and a preparation method thereof.
Background
PERC (Passivated emitter and Rear Cell) has gained wide attention in the industry due to its high conversion efficiency. The core of the technology is that the back of a silicon chip is covered by an aluminum oxide or silicon oxide film to play a role in passivating the back surface and improving long-wave response, so that the conversion efficiency of the battery is improved.
The back of the silicon wafer is coated with an alumina film to passivate the silicon. However, the matching between the back side alumina film and silicon is not good, and after passivation by the alumina film, the back side still has larger defects, and the passivation effect is general.
In order to enhance the chemical passivation effect of the back surface of the silicon wafer, CN106992229A discloses a passivation process for the back surface of a PERC cell, in which a silicon dioxide layer is formed on the back surface of the silicon wafer by an ozone machine, an aluminum oxide film is deposited on the silicon dioxide layer by ALD equipment, and then a silicon nitride layer is deposited on the aluminum oxide film by a plasma enhanced chemical vapor deposition method.
Disclosure of Invention
The PERC battery and the preparation method thereof have the advantages that the process compatibility is stronger, the battery production cost is reduced, the conversion efficiency of the battery can be improved, and the reliability of the battery is improved.
The embodiment of the application provides a preparation method of a PERC battery, which comprises the steps of texturing, diffusion, etching, back polishing, annealing, back film coating and front film coating. The back surface coating step comprises: and introducing ozone gas into the equipment provided with the annealed silicon wafer for oxidation treatment, so that a back silicon dioxide layer is formed on the back of the silicon wafer. And then continuously introducing ozone serving as an oxygen source in the same equipment, adding an aluminum source, and depositing a back aluminum oxide layer on the back silicon dioxide layer. A back side silicon nitride layer is deposited on the back side aluminum oxide layer.
The inventors have found that CN106992229A discloses a passivation process for the back surface of a PERC cell resulting in a PERC cell with poor PID performance. Therefore, the inventors have made intensive studies and found that the formation of a silicon oxide layer is carried out in an ozone machine, the deposition of an alumina thin film is carried out in an ALD apparatus, both processes need to be carried out in two apparatuses, and the cleanliness of a film layer contact interface is affected during the transfer of a silicon wafer from the ozone machine to the ALD apparatus. In the prior art, oxygen is introduced into the ALD equipment as an oxygen source when the back side alumina layer is prepared, so that the preparation of the back side silica layer and the back side alumina layer in CN106992229A is performed in two equipment.
The preparation method of the PERC battery provided by the embodiment of the application has the beneficial effects that: the silicon dioxide layer obtained can be made denser by introducing ozone into the apparatus to deposit the back silicon dioxide layer. And then, ozone is used as an oxygen source in the same equipment, the back alumina layer is continuously deposited, two processes can be carried out in the same equipment, ozone oxidation equipment is not required to be added, the cleanliness of a film layer contact interface can be kept, and the reliability and the conversion efficiency of the battery are improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments are briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive efforts and also belong to the protection scope of the present application.
Fig. 1 is a schematic structural diagram of a single-sided PERC cell provided in an embodiment of the present application;
fig. 2 is a schematic structural diagram of a double-sided PERC battery provided in an embodiment of the present application;
icon: a 10-P type silicon substrate; a 20-N + emitter junction layer; a 30-N + + silicon layer; 40-front side silicon dioxide layer; 50-a back side silicon dioxide layer; 60-back side alumina layer; 70-a back side silicon nitride layer; 80-front antireflection layer; 90-front electrode; 91-aluminum back field; 92-aluminum grid line.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions of the embodiments of the present application will be clearly and completely described below. The examples, in which specific conditions are not specified, were conducted under conventional conditions or conditions recommended by the manufacturer. The reagents or instruments used are not indicated by the manufacturer, and are all conventional products available commercially.
Fig. 1 is a schematic structural diagram of a single-sided PERC cell provided in an embodiment of the present application; fig. 2 is a schematic structural diagram of a double-sided PERC battery provided in an embodiment of the present application. Referring to fig. 1 and 2, in an embodiment of the present application, a method for manufacturing a PERC battery includes the following steps:
s10, texturing: and cleaning and texturing the silicon wafer, removing a damage layer on the surface of the silicon wafer, and texturing the front side of the silicon wafer to form a pyramid textured surface with the height of 0.5-5 microns. Optionally, the height of the texture is 0.5 μm, 1 μm, 2 μm, 3 μm, 4 μm, or 5 μm. Alternatively, the silicon wafer provided by the embodiment of the present application is a single crystal silicon wafer, and the texturing is performed by using an alkali solution (e.g., strong alkali, NaOH or KOH). In other embodiments, the silicon wafer is a polycrystalline silicon wafer and is textured using an acid solution (e.g., a strong acid, nitric acid or/and hydrofluoric acid).
S20, diffusion: and doping phosphorus on the textured silicon wafer to form a phosphorus-doped N + emitter junction layer 20. Optionally, the silicon wafer is placed in a diffusion furnace, and diffusion is performed for 30-60min at the diffusion temperature of 750-850 ℃, so that a doping source is deposited on the front surface of the silicon wafer and thermal diffusion is performed to prepare a phosphorus-doped N + emitter junction 20, thereby forming a PN junction. Wherein the doping source is phosphorus oxychloride (POCl)3) The solution has a diffusion temperature of 750 deg.C, 780 deg.C,800 ℃, 820 ℃ or 850 ℃; the diffusion time may be 30min, 40min, 50min or 60 min. The thickness of the phosphorus doped N + emitter junction layer 20 formed is 0.2-0.4 μm. For example: the thickness of the phosphorus doped N + emitter junction layer 20 may be 0.2 μm, 0.3 μm, or 0.4 μm.
S30, heavily doped: local region doping diffusion is performed on the phosphorus-doped N + emitter junction layer 20, so that a phosphorus-doped N + + silicon layer 30 is formed between the N + emitter junction layer 20 and the silicon wafer (i.e., the P-type silicon substrate 10). High-concentration doping (phosphorus-doped N + + silicon layer 30) is carried out at the contact part of the metal grid line and the silicon wafer and the vicinity thereof, and low-concentration doping (phosphorus-doped N + emitter junction layer 20) is carried out in the region except the front electrode 90, so that the contact resistance between the silicon wafer and the electrode is reduced, the surface recombination is reduced, and the minority carrier lifetime is prolonged. Thereby reducing series resistance and improving filling factor; the carrier recombination is reduced, and the surface passivation effect is improved; the short-wave spectral response of the battery is enhanced, and the short-circuit current and the open-circuit voltage are improved.
Alternatively, a phosphorus doped N + + silicon layer 30 (heavily doped silicon layer) is formed using laser doping. In the laser doping process, the surface of a silicon wafer is melted by using the heat effect of laser, phosphorus atoms in phosphorosilicate glass covering the top of an emitter enter the surface layer of the silicon wafer to perform doping and diffusion in a local area, the diffusion coefficient of the phosphorus atoms in liquid silicon is higher than that in solid silicon, and the phosphorus atoms are doped to replace the positions of silicon atoms after solidification to form a heavily doped silicon layer. Wherein the laser power is 20-40W. For example: the laser power may be 20W, 25W, 30W, 35W or 40W. S40, etching and back polishing: and cleaning and back polishing the laser-doped silicon wafer. After the diffusion process, N-type layers are formed on the front surface, the back surface and the edge of the silicon wafer, and phosphorosilicate glass is arranged on the surface of the silicon wafer, so that the N-type layers on the edge and the back surface of the silicon wafer are removed through a wet etching process, the phosphorosilicate glass on the front surface is removed, and the back surface of the silicon wafer is polished. Wherein, the etching solution used in the wet etching is HNO3And a mixed solution of HF.
S50, annealing: putting the silicon chip into an annealing furnace, and introducing a certain amount of oxygen during annealing so as to be capable of forming a P-doped N + emitter junction layerGrowing a front side silicon dioxide layer 40 (SiO)2). Wherein the annealing temperature is 750-850 ℃. For example: the annealing temperature is 750 deg.C, 770 deg.C, 790 deg.C, 810 deg.C, 830 deg.C or 850 deg.C. The front-side silicon dioxide layer 40 is formed to a thickness of 2-5 nm. For example: the thickness of the front-side silicon dioxide layer 40 is 2nm, 3nm, 4nm or 5 nm.
S60, back coating: depositing a back silicon dioxide layer 50 (SiO) on the back of the silicon wafer2) A back aluminum oxide layer 60(AlOx), and a back silicon nitride layer 70 (SiNx). Optionally, the back silicon oxide layer 50 and the back aluminum oxide layer 60 are performed in the chamber of the same apparatus, for example: are all performed in the chamber of the ALD apparatus. And placing the annealed silicon wafer into a chamber of an ALD (atomic layer deposition) device, and introducing ozone gas into the chamber of the ALD device to perform oxidation treatment, so that a back silicon dioxide layer 50 is formed on the back of the polished silicon wafer. Then continuing to perform a passivation process in the ALD equipment, continuing to introduce ozone into the ALD equipment as an oxygen source, adding an aluminum source, and depositing a back aluminum oxide layer 60 on the surface of the back silicon dioxide layer 50 away from the silicon wafer. The back silicon dioxide layer 50 is deposited between the back aluminum oxide layer 60 and the silicon wafer, so that the comprehensive utilization rate of passivation and incident light can be effectively enhanced, and the loss of non-equilibrium carriers caused by surface defects can be reduced. The short-circuit current and the open-circuit voltage of the battery are improved, and the light attenuation resistance, the PID resistance and the reliability of the battery with the structure are improved.
The two processes of depositing the back silicon dioxide layer 50 and depositing the back aluminum oxide layer 60 are carried out in the same equipment, so that the compatibility of the processes is better, the formation of the back silicon dioxide layer 50 is carried out without additionally adding ozone oxidation equipment, the contact interface cleanliness of the back silicon dioxide layer 50 and the back aluminum oxide layer 60 can be kept, and the conversion efficiency of the battery is improved. Ozone gas is introduced into a cavity of the ALD device, so that the ozone gas and silicon are subjected to oxidation reaction, the obtained back silicon dioxide layer 50 is better in compactness, the back defects of the battery can be further improved, and the PID resistance of the battery is improved.
Wherein the thickness of the back silicon dioxide layer 50 is 2-5 nm. The thickness of the back alumina layer 60 is 2-6 nm. Alternatively, the thickness of the back side silicon dioxide layer 50 may be 2nm, 3nm, 4nm, or 5 nm; the thickness of the back aluminum oxide layer 60 may be 2nm, 3nm, 4nm, 5nm, or 6 nm.
In order to deposit the back silicon dioxide layer 50 on the back surface of the silicon wafer, the conditions for introducing ozone gas into the chamber of the ALD apparatus to perform the oxidation treatment include: the flow rate of the ozone is 5-150sccm, the oxidation time is 1-10min, and the oxidation temperature is 150-. For example: the flow rate of the introduced ozone gas can be 5sccm, 10sccm, 20sccm, 40sccm, 80sccm, 120sccm or 150 sccm; the oxidation time can be 1min, 3min, 5min, 7min, 9min or 10 min; the oxidation temperature may be 150 ℃, 200 ℃, 250 ℃ or 300 ℃.
Further, the deposition of the back side alumina layer 60 may continue in the chamber of the ALD apparatus. Wherein, in the process of depositing the back side alumina layer 60, the introduced ozone gas is directly used as an oxygen source, and the deposition is carried out at the temperature of 150 ℃ and 300 ℃.
The aluminum source for depositing the back aluminum oxide layer 60 is an aluminum-containing precursor, and may be one or more of aluminum trichloride, trimethylaluminum, triethylaluminum, dimethylaluminum chloride, aluminum ethoxide and aluminum isopropoxide, and is formed by an Atomic Layer Deposition (ALD) method. The Atomic Layer Deposition (ALD) method is carried out in the cavity of the ALD device, ozone gas is introduced into the cavity of the ALD device, two processes can be compatible in the same device, and the production cost is reduced.
Further, a back silicon nitride layer 70 is deposited on the back aluminum oxide layer 60. Alternatively, the deposition method of the back silicon nitride layer 70 may be an atomic layer deposition method or a Plasma Enhanced Chemical Vapor Deposition (PECVD) method.
With continued reference to fig. 1 and 2, if the prepared PERC cell is a single-sided cell, the thickness of the back silicon nitride layer 70 is 110-180 nm. For example: the thickness of the back side silicon nitride layer 70 may be 110nm, 130nm, 150nm, 170nm or 180 nm. If the prepared PERC cell is a bifacial cell, the thickness of the back silicon nitride layer 70 is 85-105 nm. For example: the thickness of the back side silicon nitride layer 70 may be 85nm, 90nm, 95nm, 100nm or 105 nm.
S70, front film coating: and forming a front silicon nitride layer on the front surface of the silicon wafer. A front silicon nitride (SiNx) layer (a front antireflection layer 80) is formed on a front silicon dioxide layer of a silicon wafer by adopting a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, so that the light reflectivity is reduced, and a certain passivation effect is achieved. Optionally, the front side silicon nitride layer has a thickness of 73-83 nm. For example: the thickness of the front side silicon nitride layer may be 73nm, 75nm, 77nm, 79nm, 81nm or 83 nm.
S80, laser grooving: and selectively etching part of the passivation layer (the back silicon dioxide layer, the back aluminum oxide layer and the back silicon nitride layer) on the back of the silicon chip by adopting laser etching, so as to open a groove or a hole on the back of the silicon chip and expose the structure of the P-type silicon substrate layer.
S90, screen printing and sintering: and printing silver paste on the front surface of the silicon wafer and aluminum paste on the back surface of the silicon wafer according to the screen printing plate pattern design by adopting a screen printing method, and forming ohmic contact after high-temperature sintering to manufacture the PERC battery.
Optionally, the front side printed silver paste is sintered to form the front side electrode 90, and the front side electrode 90 is in ohmic contact with the phosphorus doped N + + silicon layer 30. Wherein the front electrode 90 is a front grid line, the height of the front grid line is 18-25 μm, and the width is 35-45 μm. For example: the height of the front grating may be 18 μm, 20 μm, 22 μm, 24 μm or 25 μm and the width of the front grating may be 35 μm, 37 μm, 39 μm, 41 μm, 43 μm or 45 μm.
Referring to fig. 1, if the prepared PERC cell is a single-sided cell, the back surface of the cell is an aluminum back field 91, and the aluminum back field 91 is in ohmic contact with the P-type silicon substrate. Alternatively, the consumption of the aluminum paste in the formation of the aluminum back surface field 91 of the single-sided battery is between 0.8 and 0.9 g. For example: the consumption of the aluminum paste may be 0.8g, 0.82g, 0.84g, 0.86g, 0.88g, or 0.9 g. When the aluminum paste is printed, the aluminum paste enters the cell structure in S80, and the sintered aluminum back field 91 is brought into ohmic contact with the P-type silicon substrate 10.
Referring to fig. 2, if the prepared PERC cell is a double-sided cell, the back side of the cell is an aluminum gate line 92, and the aluminum gate line 92 is in ohmic contact with the P-type silicon substrate. Alternatively, the consumption of the aluminum paste in forming the aluminum grid line 92 of the double-sided battery is between 0.2 and 0.4 g. For example: the consumption of the aluminum paste may be 0.2g, 0.25g, 0.3g, 0.35g, or 0.4 g. When the aluminum paste is printed, the aluminum paste enters the trench structure in S80, and the sintered aluminum gate line 92 is brought into ohmic contact with the P-type silicon substrate 10.
The beneficial effects of the single-sided PERC cell (as shown in fig. 1) or the double-sided PERC cell (as shown in fig. 2) prepared by the above preparation method include:
(1) the two processes of depositing the back silicon dioxide layer 50 and depositing the back aluminum oxide layer 60 are all carried out in the cavity of the same ALD device, so that the compatibility of the processes is better, the ozone oxidation device is not required to be additionally arranged to form the back silicon dioxide, the cleanliness of a contact interface between the back silicon dioxide layer 50 and the back aluminum oxide layer 60 can be kept, the PID resistance performance and the conversion efficiency of the battery are improved, and the reliability of the battery is improved.
(2) And a phosphorus-doped N + + silicon layer 30 is formed between the N + emitter junction layer 20 and the P-type silicon substrate 10, so that the contact resistance between the silicon wafer and the electrode is reduced, the surface recombination is reduced, and the minority carrier lifetime is prolonged.
(3) The process has strong compatibility, and can meet the preparation requirements of both single-sided PERC batteries and double-sided PERC batteries.
Example 1
A preparation method of a single-sided PERC battery comprises the following steps:
(1) and (3) texturing: and cleaning and texturing the silicon wafer, removing a damage layer on the surface of the silicon wafer, and texturing the front side of the silicon wafer to form a pyramid textured surface with the height of 3 microns.
(2) And (3) diffusion: and placing the silicon wafer in a diffusion furnace, and diffusing for 40min at the diffusion temperature of 800 ℃ to deposit phosphorus oxychloride on the front surface of the silicon wafer and thermally diffuse to prepare a phosphorus-doped N + emitter junction with the thickness of 0.3 mu m.
(3) And heavy doping: and doping and diffusing local areas on the phosphorus-doped N + emitter junction layer in a laser doping mode, so that a phosphorus-doped N + + silicon layer is formed between the N + emitter junction layer and the P-type silicon substrate.
(4) Etching and back polishing: and removing the N-type layer corrosion on the edge and the back of the silicon wafer by a wet etching process, removing the phosphorosilicate glass on the front side, and polishing the back of the silicon wafer.
(5) And annealing: and putting the silicon wafer into an annealing furnace, introducing a certain amount of oxygen, and growing a front-side silicon dioxide layer with the thickness of 4nm at the temperature of 800 ℃.
(6) And back coating: and placing the annealed silicon wafer in a cavity of an ALD (atomic layer deposition) device, introducing ozone gas with the flow rate of 40sccm into the cavity of the ALD device, and oxidizing for 5min at the temperature of 200 ℃ to form a back silicon dioxide layer with the thickness of 3 nm. Then, under the condition of the temperature of 250 ℃, ozone gas is used as an oxygen source, and a back side alumina layer with the thickness of 4nm is continuously deposited. A backside silicon nitride layer was then deposited using a Plasma Enhanced Chemical Vapor Deposition (PECVD) process to a thickness of 150 nm.
(7) And coating the film on the front side: and forming a front silicon nitride layer with the thickness of 80nm on the front surface of the silicon wafer by adopting a Plasma Enhanced Chemical Vapor Deposition (PECVD) method.
(8) Laser grooving: and selectively etching part of the passivation layer (the back silicon dioxide layer, the back aluminum oxide layer and the back silicon nitride layer) on the back of the silicon chip by adopting laser etching, so as to open a groove or a hole on the back of the silicon chip and expose the structure of the P-type silicon substrate layer.
(9) Screen printing and sintering: and printing silver paste on the front surface of the silicon wafer and 0.85g of aluminum paste on the back surface of the silicon wafer according to the design of a screen printing plate graph by adopting a screen printing method, and sintering at high temperature to form a front electrode and an aluminum back field, wherein the front electrode is in ohmic contact with the phosphorus-doped N + + silicon layer, and the aluminum back field is in ohmic contact with the P-type silicon substrate.
Example 2
Example 2 is different from example 1 in that example 2 is not subjected to the heavy doping step of step (3) in example 1. The other step methods are the same as those of the embodiment.
Example 3
Example 3 differs from example 1 in that example 3 performs the preparation of a double-sided PERC cell. The difference lies in that:
(6) and back coating: and placing the annealed silicon wafer in a cavity of an ALD (atomic layer deposition) device, introducing ozone gas with the flow rate of 40sccm into the cavity of the ALD device, and oxidizing for 5min at the temperature of 200 ℃ to form a back silicon dioxide layer with the thickness of 3 nm. Then, under the condition of the temperature of 250 ℃, ozone gas is used as an oxygen source, and a back side alumina layer with the thickness of 4nm is continuously deposited. A backside silicon nitride layer was then deposited using Plasma Enhanced Chemical Vapor Deposition (PECVD) to a thickness of 95 nm.
(9) Screen printing and sintering: and printing silver paste on the front surface of the silicon wafer and 0.32g of aluminum paste on the back surface of the silicon wafer according to the design of a screen printing plate graph by adopting a screen printing method, and sintering at high temperature to form a front electrode and an aluminum grid line, wherein the front electrode is in ohmic contact with the phosphorus-doped N + + silicon layer, and the aluminum grid line is in ohmic contact with the P-type silicon substrate.
The other step methods are the same as those of the embodiment.
Comparative example 1
Comparative example 1 a single sided PERC cell was prepared, comparative example 1 differing from example 1 in that:
(6) and back coating: and (3) placing the annealed silicon wafer in an ozone machine for oxidation treatment to form a back silicon dioxide layer with the thickness of 3 nm. The wafer was then transferred to the ALD apparatus chamber and a 4nm thick backside aluminum oxide layer was deposited at a temperature of 400 c. A backside silicon nitride layer was then deposited using a Plasma Enhanced Chemical Vapor Deposition (PECVD) process to a thickness of 150 nm.
The other step methods are the same as those of the embodiment.
Examples of the experiments
The performance of the PERC cells obtained in examples 1 to 4 and the PERC cells provided in comparative examples 1 to 4 were measured as shown in table 1; the detection method comprises the following steps: a BERGER on-line I-V test system is selected to test the electrical performance parameters of the solar cell, such as open-circuit voltage, short-circuit current, filling factor, conversion efficiency and the like, under the conditions of 25 ℃, 1.5 AM and 1 standard sun.
TABLE 1PERC Battery Performance
| Item | Counting | Eta(％) | Uoc(V) | Isc(A) | Rs |
| Example 1 | 800 | 22.493 | 0.6774 | 10.382 | 0.0020 |
| Example 2 | 400 | 22.496 | 0.6778 | 10.378 | 0.0020 |
| Example 3 | 800 | 22.464 | 0.6767 | 10.375 | 0.0019 |
| Comparative example 1 | 1200 | 22.396 | 0.6757 | 10.360 | 0.0019 |
As can be seen from table 1, ozone gas is introduced into the chamber of the ALD apparatus to form a back silicon oxide layer, and ozone is continuously introduced into the same apparatus to form a back aluminum oxide layer, so that the conversion efficiency, open-circuit voltage, and short-circuit current of the obtained single-sided PERC cell and the double-sided PERC cell are increased to different degrees, which indicates that the PERC cell has better performance.
The embodiments described above are some, but not all embodiments of the present application. The detailed description of the embodiments of the present application is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Claims (10)
1. A preparation method of a PERC battery comprises the steps of texturing, diffusion, etching, back polishing, annealing, back film coating and front film coating, and is characterized in that,
the back surface coating step comprises:
introducing ozone gas into the equipment with the annealed silicon wafer for oxidation treatment to form a back silicon dioxide layer on the back of the silicon wafer;
then continuing to introduce ozone into the equipment as an oxygen source, adding an aluminum source, and depositing a back aluminum oxide layer on the back silicon dioxide layer;
depositing a back side silicon nitride layer on the back side aluminum oxide layer.
2. The production method according to claim 1, wherein the conditions for introducing ozone gas into the apparatus containing the annealed silicon wafer to perform the oxidation treatment comprise: the flow rate of the ozone is 5-150sccm, the oxidation time is 1-10min, and the oxidation temperature is 150-.
3. The method as claimed in claim 2, wherein the step of depositing the back alumina layer on the back silicon dioxide layer is performed at a deposition temperature of 150 ℃ to 300 ℃.
4. A production method according to any one of claims 1 to 3, characterized in that the apparatus is an ALD apparatus.
5. The method of manufacturing according to claim 4, wherein the diffusing includes: doping phosphorus on the textured silicon wafer to form a phosphorus-doped N + emitter junction layer;
the preparation method further comprises the following steps: and carrying out doping diffusion of a local area on the phosphorus-doped N + emitter junction layer to form a phosphorus-doped N + + silicon layer between the N + emitter junction layer and the silicon wafer.
6. The method of claim 5, wherein the phosphorus-doped N + + silicon layer is formed by laser doping.
7. A single sided PERC cell, comprising:
a P-type silicon substrate;
the front surface of the P-type silicon substrate is sequentially provided with a phosphorus-doped N + emitter junction layer, a front surface silicon dioxide layer, a front surface antireflection layer and a front surface electrode, a phosphorus-doped N + + silicon layer is arranged between the phosphorus-doped N + emitter junction layer and the P-type silicon substrate, and the front surface electrode is in ohmic contact with the phosphorus-doped N + + silicon layer;
the back surface of the silicon substrate is sequentially provided with a back silicon dioxide layer, a back aluminum oxide layer, a back silicon nitride layer and an aluminum back field, and the aluminum back field is in ohmic contact with the P-type silicon substrate.
8. The single sided PERC cell of claim 7, wherein the phosphorus doped N + emitter junction layer has a thickness of 0.2-0.4 μm, and wherein the back side silicon dioxide layer and the front side silicon dioxide layer each have a thickness of 2-5 nm.
9. A double-sided PERC battery, comprising:
a P-type silicon substrate;
the front surface of the P-type silicon substrate is sequentially provided with a phosphorus-doped N + emitter junction layer, a front surface silicon dioxide layer, a front surface antireflection layer and a front surface electrode, a phosphorus-doped N + + silicon layer is arranged between the phosphorus-doped N + emitter junction layer and the P-type silicon substrate, and the front surface electrode is in ohmic contact with the phosphorus-doped N + + silicon layer;
the back surface of the silicon substrate is sequentially provided with a back silicon dioxide layer, a back aluminum oxide layer, a back silicon nitride layer and an aluminum grid line, and the aluminum grid line is in ohmic contact with the P-type silicon substrate.
10. The dual sided PERC cell of claim 9, wherein the phosphorus doped N + emitter junction layer has a thickness of 0.2-0.4 μm, and wherein the back side silicon dioxide layer and the front side silicon dioxide layer each have a thickness of 2-5 nm.
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