CN110838318A - Method and system for improving data reliability of memory - Google Patents
Method and system for improving data reliability of memory Download PDFInfo
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- CN110838318A CN110838318A CN201810940767.0A CN201810940767A CN110838318A CN 110838318 A CN110838318 A CN 110838318A CN 201810940767 A CN201810940767 A CN 201810940767A CN 110838318 A CN110838318 A CN 110838318A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
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Abstract
The invention discloses a method and a system for improving the data reliability of a memory. The method for improving the data reliability of the memory comprises the following steps: applying a program voltage to a memory cell at a first timing; applying a verify voltage to the memory cell at a second timing; between the first timing and the second timing, a clear voltage is applied to the substrate of the memory cell. The method for improving the data reliability of the memory has the advantage of improving the reliability of read data.
Description
Technical Field
The embodiment of the invention relates to the technical field of memories, in particular to a method and a system for improving the data reliability of a memory.
Background
The Nand flash memory is a nonvolatile memory and has the advantages of high rewriting speed, large storage capacity and the like. When the Nand flash memory is programmed, part of electrons are trapped in a tunneling oxide film between a floating gate and a substrate of the Nand flash memory due to the fact that multiple programming verification operations are needed, the number of electrons trapped in the tunneling oxide film is increased along with the increase of the programming and erasing times, and when data is read, the threshold value of a storage unit of the Nand flash memory is reduced, and the reliability of the data is affected.
Therefore, how to provide a method or system for improving data reliability during memory programming is a need in the memory technology field.
Disclosure of Invention
The invention provides a method and a system for improving data reliability of a memory, which aim to solve the technical problems that the data reliability of the memory is reduced along with the increase of programming times.
In a first aspect, an embodiment of the present invention provides a method for improving reliability of memory data, including the following steps: applying a program voltage to a memory cell at a first timing; applying a verify voltage to the memory cell at a second timing; between the first timing and the second timing, a clear voltage is applied to the substrate of the memory cell.
Preferably, the dielectric constant between the source and drain of the memory cell and the floating gate is proportional to the magnitude of the erase voltage, and the dielectric constant between the source and drain of the memory cell and the floating gate is proportional to the duration of the erase voltage.
Preferably, the magnitude of the clearing voltage is 1-5V, and the duration of the clearing voltage is 0.1-1.5S.
Preferably, at the first timing, a program voltage is applied to the selected word line, a pass voltage is applied to the unselected word line, 0V is applied to the selected bit line, and a positive voltage is applied to the unselected bit line.
Preferably, the programming voltage ranges from 12V to 16V.
Preferably, at the second timing, the verification voltage is applied to the selected word line, the selected bit line is precharged to the precharge voltage, and the pass voltage is applied to the unselected word line; and then discharging the selected bit line for the first time, comparing the voltage of the discharged bit line with a first judgment voltage, finishing the operation if the voltage of at least one bit line is higher than the first judgment voltage, and storing data into the memory again if the voltage of at least one bit line is not higher than the first judgment voltage.
Preferably, the verifying voltage ranges from 0V to 1V.
Preferably, the precharge voltage ranges from 1v to 1.2 v.
In a second aspect, the present invention further provides a system for improving data reliability of a memory, where the system for improving data reliability of a memory includes: a programming module for applying a programming voltage to the memory cells at a first timing; the verifying module is used for applying verifying voltage to the storage unit at a second time sequence; and the clearing module is used for applying a clearing voltage to the substrate of the memory cell between the first time sequence and the second time sequence.
Preferably, the memory cell includes a substrate, a source, a drain, a tunneling oxide film, a floating gate, and a control gate, the substrate includes a P-well region, the source and the drain are disposed in the P-well region, a channel is formed between the source and the drain, the tunneling oxide film is formed on the channel between the source and the drain, the floating gate is disposed on the tunneling oxide film, and the control gate is disposed on the floating gate.
Compared with the prior art, the method and the system for improving the data reliability of the memory are provided, programming voltage is applied to the memory cell, after data is written, clearing voltage is applied to the substrate of the memory cell of the memory, electrons retained in the tunneling oxide film are effectively reduced, the threshold value during data reading is maintained, the reliability of the data reading is improved, data verification is continued subsequently, and data verification is not influenced.
Drawings
Fig. 1 is a flowchart illustrating a method for improving reliability of memory data according to an embodiment a of the present invention.
FIG. 2 is a schematic circuit diagram of a memory array according to an embodiment of the invention.
Fig. 3 is a schematic chip structure diagram of a memory cell in embodiment a of the invention.
FIG. 4 is a schematic diagram of waveforms at different times of a method for improving reliability of memory data according to embodiment A of the present invention.
FIG. 5 is a block diagram illustrating a system for improving reliability of data stored in a memory according to an embodiment B of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Before discussing exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the steps as a sequential process, many of the steps can be performed in parallel, concurrently or simultaneously. In addition, the order of the steps may be rearranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figure. The processes may correspond to methods, functions, procedures, subroutines, and the like.
Example A
Referring to fig. 1, fig. 1 is a schematic flow chart of a method for improving data reliability of a memory according to an embodiment a of the present invention, where the method for improving data reliability of a memory is used to improve durability and usability of read data of the memory so as to improve the lifetime of the memory, and the method for improving data reliability of a memory includes the following steps:
step S1: applying a program voltage to a memory cell at a first timing;
step S2: applying a verify voltage to the memory cell at a second timing;
step S3: between the first timing and the second timing, a clear voltage is applied to the substrate of the memory cell.
In step S1, step S1 is a programming step, and data is written into the memory. The memory is preferably a NAND type memory. Referring to fig. 2, fig. 2 is a circuit structure diagram of the memory array. The memory includes n word lines (WL1, WL2, …, WLn), m bit lines (BL1, BL2, …, BLm), a select gate line SGS, a select gate line SGD, and a common source line SL, and a memory cell portion identified by a dashed box 11 is referred to as a memory cell string. Each memory cell string includes a plurality of memory cells 111 (i.e., MC 1-MCn); a bit line side selection transistor TD connected to the memory cell MCn as one end portion; and a source-line-side selection transistor TS connected to the memory cell MC1 as the other end, the drain of the bit-line-side selection transistor TD being connected to the corresponding 1 bit line BL, and the source of the source-line-side selection transistor TS being connected to the common source line SL. The control gate of the memory cell 111 is connected to a word line WLi (i is 0 to n), the gate of the bit line side selection transistor TD is connected to the selection gate line SGD, and the gate of the source line side selection transistor TS is connected to the selection gate line SGS.
Referring to fig. 3, fig. 3 is a schematic diagram of a chip structure of the memory unit 111. The memory cell 111 includes a substrate 1111, a source 1112, a drain 1113, a tunnel oxide film 1114, a floating gate 1115, and a control gate 1116, the substrate 1111 includes a P-well region thereon, the source 1112 and the drain 1113 are disposed in the P-well region, a channel is formed between the source 1112 and the drain 1113, the tunnel oxide film 1114 is formed over the channel between the source 1112 and the drain 1113, the floating gate 1115 is disposed on the tunnel oxide film 1114, and the control gate 1116 is disposed on the floating gate 1115. It will be appreciated that a dielectric film 1117 is disposed between the control gate 1116 and the floating gate 1115. When no charge is accumulated in the floating gate 1115, that is, when data "1" is written, the threshold value is in a negative state, and the memory cell 111 is turned on by the control gate 1116 being 0V. When electrons are accumulated in the floating gate 1115, that is, when data "0" is written, the threshold shift is positive, and the memory cell is turned off by the control gate 1116 being 0V. However, the memory cell is not limited to storing a single bit, and may store a plurality of bits. During the operations of programming, verifying, erasing, etc., some electrons are trapped in the tunnel oxide film 1114, and as the number of times of programming, verifying, erasing increases, the more electrons are trapped in the tunnel oxide film 1114, which may cause a decrease in threshold value during reading data, and affect the reliability of the data.
Referring to fig. 4, fig. 4 is a waveform diagram illustrating different moments of the method for improving the reliability of memory data according to the present invention, and the present embodiment provides a specific programming step, in which data is written into the memory cell MC1, and in the programming timing B1, a programming voltage is applied to the selected word line WL1, a pass voltage is applied to the unselected word lines WL 2-WLn, 0V is applied to the selected bit line BLm, and a positive voltage is applied to the unselected bit lines BL 1-BLm-1 in the first timing. The range of the programming voltage is 10-18V, and preferably 12-16V. In a certain programming time, the memory cell with the lower initial threshold voltage has larger threshold voltage increment after being programmed, and conversely, the threshold voltage increment is smaller. Here, as will be understood by those skilled in the art, in the programming operation, it is usually necessary to apply a voltage of 0V to the select gate line SGS and a voltage of about 4V to the select gate line SGD to turn on the MOS transistor connected thereto.
At the second timing in step S2, a verify voltage is applied to the selected word line WL1 in the memory, the selected bit line BLm is precharged to the precharge voltage, and a pass voltage is applied to the unselected word lines WL2 to WLn; and then discharging the selected bit line BLm for the first time, comparing the voltage of the discharged bit line with a first judgment voltage, if the voltage of the selected bit line is higher than the first judgment voltage, indicating that the programming verification operation is successful, finishing the operation, otherwise, failing the verification, and storing data into the memory again. Preferably, the verify voltage ranges from 0V to 1V. The precharge voltage ranges from 1v to 1.2 v. It is understood that the first timing is a period of time for simultaneously writing data into a memory cell or a plurality of memory cells, and the second timing is a period of time for verifying the memory cell after the data is written in the first timing.
In step S3, the magnitude and time length of the erase voltage can be adjusted according to the characteristics of the dielectric material of the memory and the process. Specifically, the dielectric constant between the source 1112 and the drain 1113 of the memory cell 111 and the floating gate 1115 is proportional to the magnitude of the erase voltage, and the dielectric constant between the source 1112 and the drain 1113 of the memory cell 111 and the floating gate 1115 is proportional to the duration of the erase voltage. Preferably, the magnitude of the clearing voltage is 1-5V, and the duration of the clearing voltage is 0.1-1.5S. It is understood that when applying a clear voltage to the substrate of a memory cell of a memory, a clear voltage is applied to a selected memory cell. The application of the erase voltage can effectively reduce the electrons retained in the tunnel oxide film 1114 to maintain the threshold value during reading data, thereby improving the reliability of reading data. Through multiple tests, the operation of the step 2 is adopted, and the stability of the memory is improved by 2-5 times. If the memory can store data 100 ten thousand times and the reliability of the read data is obviously reduced when the memory is used according to the existing method, the reliability of the read data is obviously reduced when the memory can store data 200 ten thousand to 500 ten thousand times by adopting the method for improving the data reliability of the memory.
Example B
Referring to fig. 5, fig. 5 is a block diagram illustrating a system 12 for improving reliability of data stored in a memory according to the present invention. The system 12 for improving reliability of data in a memory can perform the method for improving reliability of data in a memory according to any embodiment of the present invention. The system 12 for improving reliability of memory data comprises:
a program module 121 for applying a program voltage to the memory cell at a first timing;
a verifying module 123 for applying a verifying voltage to the memory cell at the second timing;
a clear module 122 for applying a clear voltage to the substrate of the memory cell between the first timing and the second timing.
According to the system 12 for improving the reliability of the data of the memory, after the programming module 121 writes the data into the memory, the erasing module 122 applies an erasing voltage to the substrate of the memory cell of the memory to reduce electrons retained in the tunnel oxide film, maintain the threshold value when reading the data and improve the reliability of the read data, and then the verifying module 123 verifies whether the data is stored in the memory cell. If the verified data is confirmed to be stored, the subsequent operation is performed, and if the data is not stored, the programming module 121 stores the data into the memory again.
It is understood that the contents of embodiment a and embodiment B of the present invention can be supplemented and described.
Compared with the prior art, the method and the system for improving the data reliability of the memory are provided, programming voltage is applied to the memory cell, after data is written, clearing voltage is applied to the substrate of the memory cell of the memory, electrons retained in the tunneling oxide film are effectively reduced, the threshold value during data reading is maintained, the reliability of the data reading is improved, data verification is continued subsequently, and data verification is not influenced.
It should be noted that, in all the above embodiments, the included units and modules are only divided according to functional logic, but are not limited to the above division as long as the corresponding functions can be implemented; in addition, specific names of the functional units are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present invention.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A method for improving data reliability of a memory, comprising the steps of:
applying a program voltage to a memory cell at a first timing;
applying a verify voltage to the memory cell at a second timing;
between the first timing and the second timing, a clear voltage is applied to the substrate of the memory cell.
2. The method of improving memory data reliability of claim 1, wherein: the dielectric constant between the source and drain of the memory cell and the floating gate is proportional to the magnitude of the erase voltage, and the dielectric constant between the source and drain of the memory cell and the floating gate is proportional to the duration of the erase voltage.
3. The method of improving memory data reliability of claim 2, wherein: the magnitude of the clearing voltage is 1-5V, and the duration time of the clearing voltage is 0.1-1.5S.
4. The method of improving memory data reliability of claim 1, wherein: in the first timing, a program voltage is applied to the selected word line, a pass voltage is applied to the unselected word line, 0V is applied to the selected bit line, and a positive voltage is applied to the unselected bit line.
5. The method of improving memory data reliability of claim 1, wherein: the range of the programming voltage is 12V to 16V.
6. The method of improving memory data reliability of claim 1, wherein: in a second time sequence, applying a verification voltage to the selected word line, precharging the selected bit line to a precharge voltage, and applying a pass voltage to the unselected word line; and then discharging the selected bit line for the first time, comparing the voltage of the discharged bit line with a first judgment voltage, finishing the operation if the voltage of at least one bit line is higher than the first judgment voltage, and storing data into the memory again if the voltage of at least one bit line is not higher than the first judgment voltage.
7. The method of improving memory data reliability of claim 1, wherein: the range of the verification voltage is 0V-1V.
8. The method of improving reliability of memory data of claim 6, wherein: the precharge voltage ranges from 1v to 1.2 v.
9. A system for improving reliability of data stored in a memory, the system comprising:
a programming module for applying a programming voltage to the memory cells at a first timing;
the verifying module is used for applying verifying voltage to the storage unit at a second time sequence;
and the clearing module is used for applying a clearing voltage to the substrate of the memory cell between the first time sequence and the second time sequence.
10. The system for improving reliability of memory data of claim 9, wherein: the storage unit comprises a substrate, a source electrode, a drain electrode, a tunneling oxide film, a floating grid electrode and a control grid electrode, wherein the substrate comprises a P well region, the source electrode and the drain electrode are arranged in the P well region, a channel is formed between the source electrode and the drain electrode, the tunneling oxide film is formed on the channel between the source electrode and the drain electrode, the floating grid electrode is arranged on the tunneling oxide film, and the control grid electrode is arranged on the floating grid electrode.
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| CN201810940767.0A CN110838318A (en) | 2018-08-17 | 2018-08-17 | Method and system for improving data reliability of memory |
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| CN201810940767.0A CN110838318A (en) | 2018-08-17 | 2018-08-17 | Method and system for improving data reliability of memory |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111771243A (en) * | 2020-04-29 | 2020-10-13 | 长江存储科技有限责任公司 | Memory device and programming method thereof |
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Application publication date: 20200225 |